light.dtsi 56 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2021 Alibaba Group Holding Limited.
  4. */
  5. #include <dt-bindings/pinctrl/light-fm-left-pinctrl.h>
  6. #include <dt-bindings/pinctrl/light-fm-right-pinctrl.h>
  7. #include <dt-bindings/pinctrl/light-fm-aon-pinctrl.h>
  8. #include <dt-bindings/clock/light-fm-ap-clock.h>
  9. #include <dt-bindings/clock/light-vpsys.h>
  10. #include <dt-bindings/clock/light-vosys.h>
  11. #include <dt-bindings/clock/light-visys.h>
  12. #include <dt-bindings/clock/light-dspsys.h>
  13. #include <dt-bindings/firmware/thead/rsrc.h>
  14. #include <dt-bindings/soc/thead,light-iopmp.h>
  15. #include <dt-bindings/thermal/thermal.h>
  16. #include <dt-bindings/reset/light-reset.h>
  17. / {
  18. compatible = "thead,light";
  19. #address-cells = <2>;
  20. #size-cells = <2>;
  21. aliases {
  22. ethernet0 = &gmac0;
  23. ethernet1 = &gmac1;
  24. gpio0 = &gpio0;
  25. gpio1 = &gpio1;
  26. gpio2 = &gpio2;
  27. gpio3 = &gpio3;
  28. i2c0 = &i2c0;
  29. i2c1 = &i2c1;
  30. i2c2 = &i2c2;
  31. i2c3 = &i2c3;
  32. i2c4 = &i2c4;
  33. audio_i2c0 = &audio_i2c0;
  34. mmc0 = &emmc;
  35. mmc1 = &sdhci0;
  36. serial0 = &uart0;
  37. serial1 = &uart1;
  38. serial2 = &uart2;
  39. serial3 = &uart3;
  40. serial4 = &uart4;
  41. serial5 = &uart5;
  42. spi0 = &spi0;
  43. spi1 = &qspi0;
  44. spi2 = &qspi1;
  45. flash_led0 = &vvcam_flash_led0;
  46. vivcam0 = &vvcam_sensor0;
  47. vivcam1 = &vvcam_sensor1;
  48. vivcam2 = &vvcam_sensor2;
  49. vivcam3 = &vvcam_sensor3;
  50. vivcam4 = &vvcam_sensor4;
  51. vivcam5 = &vvcam_sensor5;
  52. vivcam6 = &vvcam_sensor6;
  53. viv_video0 = &video0;
  54. viv_video1 = &video1;
  55. viv_video2 = &video2;
  56. viv_video3 = &video3;
  57. viv_video4 = &video4;
  58. viv_video5 = &video5;
  59. viv_video6 = &video6;
  60. viv_video7 = &video7;
  61. viv_video8 = &video8;
  62. viv_video9 = &video9;
  63. viv_video10 = &video10;
  64. viv_video11 = &video11;
  65. viv_video12 = &video12;
  66. viv_video13 = &video13;
  67. viv_video14 = &video14;
  68. viv_video15 = &video15;
  69. };
  70. memory@0 {
  71. device_type = "memory";
  72. reg = <0x0 0x200000 0x0 0xffe00000>;
  73. };
  74. resmem: reserved-memory {
  75. #address-cells = <2>;
  76. #size-cells = <2>;
  77. ranges;
  78. /* global autoconfigured region for contiguous allocations */
  79. cmamem: linux,cma {
  80. compatible = "shared-dma-pool";
  81. reusable;
  82. size = <0 0x14000000>; // 320MB by default
  83. alloc-ranges = <0 0x64000000 0 0x14000000>; // [0x6400_0000 ~ 0x7800_0000]
  84. linux,cma-default;
  85. };
  86. };
  87. thermal-zones {
  88. cpu-thermal-zone {
  89. polling-delay-passive = <250>;
  90. polling-delay = <2000>;
  91. thermal-sensors = <&pvt 0>;
  92. trips {
  93. cpu_config0: trip0 {
  94. temperature = <85000>;
  95. hysteresis = <2000>;
  96. type = "passive";
  97. };
  98. cpu_config1: trip1 {
  99. temperature = <110000>;
  100. hysteresis = <2000>;
  101. type = "critical";
  102. };
  103. };
  104. cooling-maps {
  105. cpu_cdev {
  106. trip = <&cpu_config0>;
  107. cooling-device =
  108. <&c910_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  109. <&c910_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  110. <&c910_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  111. <&c910_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  112. };
  113. };
  114. };
  115. };
  116. cpus: cpus {
  117. #address-cells = <1>;
  118. #size-cells = <0>;
  119. timebase-frequency = <3000000>;
  120. c910_0: cpu@0 {
  121. device_type = "cpu";
  122. reg = <0>;
  123. status = "okay";
  124. compatible = "riscv";
  125. riscv,isa = "rv64imafdcvsu";
  126. mmu-type = "riscv,sv39";
  127. cpu-freq = "1.848Ghz";
  128. cpu-icache = "64KB";
  129. cpu-dcache = "64KB";
  130. cpu-l2cache = "1MB";
  131. cpu-tlb = "1024 4-ways";
  132. cpu-cacheline = "64Bytes";
  133. cpu-vector = "0.7.1";
  134. #cooling-cells = <2>;
  135. operating-points = <
  136. /* kHz uV */
  137. 300000 600000
  138. 800000 700000
  139. 1500000 800000
  140. 1848000 1000000
  141. >;
  142. light,dvddm-operating-points = <
  143. /* kHz uV */
  144. 300000 750000
  145. 800000 800000
  146. 1500000 800000
  147. 1848000 1000000
  148. >;
  149. clock-latency = <61036>;
  150. clocks = <&clk C910_CCLK>,
  151. <&clk C910_CCLK_I0>,
  152. <&clk CPU_PLL1_FOUTPOSTDIV>,
  153. <&clk CPU_PLL0_FOUTPOSTDIV>;
  154. clock-names = "c910_cclk", "c910_cclk_i0",
  155. "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
  156. dvdd-supply = <&dvdd_cpu_reg>;
  157. dvddm-supply = <&dvddm_cpu_reg>;
  158. cpu0_intc: interrupt-controller {
  159. #interrupt-cells = <1>;
  160. compatible = "riscv,cpu-intc";
  161. interrupt-controller;
  162. };
  163. };
  164. c910_1: cpu@1 {
  165. device_type = "cpu";
  166. reg = <1>;
  167. status = "okay";
  168. compatible = "riscv";
  169. riscv,isa = "rv64imafdcvsu";
  170. mmu-type = "riscv,sv39";
  171. cpu-freq = "1.848Ghz";
  172. cpu-icache = "64KB";
  173. cpu-dcache = "64KB";
  174. cpu-l2cache = "1MB";
  175. cpu-tlb = "1024 4-ways";
  176. cpu-cacheline = "64Bytes";
  177. cpu-vector = "0.7.1";
  178. #cooling-cells = <2>;
  179. operating-points = <
  180. /* kHz uV */
  181. 300000 600000
  182. 800000 700000
  183. 1500000 800000
  184. 1848000 1000000
  185. >;
  186. light,dvddm-operating-points = <
  187. /* kHz uV */
  188. 300000 750000
  189. 800000 800000
  190. 1500000 800000
  191. 1848000 1000000
  192. >;
  193. clock-latency = <61036>;
  194. clocks = <&clk C910_CCLK>,
  195. <&clk C910_CCLK_I0>,
  196. <&clk CPU_PLL1_FOUTPOSTDIV>,
  197. <&clk CPU_PLL0_FOUTPOSTDIV>;
  198. clock-names = "c910_cclk", "c910_cclk_i0",
  199. "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
  200. dvdd-supply = <&dvdd_cpu_reg>;
  201. dvddm-supply = <&dvddm_cpu_reg>;
  202. cpu1_intc: interrupt-controller {
  203. #interrupt-cells = <1>;
  204. compatible = "riscv,cpu-intc";
  205. interrupt-controller;
  206. };
  207. };
  208. c910_2: cpu@2 {
  209. device_type = "cpu";
  210. reg = <2>;
  211. status = "okay";
  212. compatible = "riscv";
  213. riscv,isa = "rv64imafdcvsu";
  214. mmu-type = "riscv,sv39";
  215. cpu-freq = "1.848Ghz";
  216. cpu-icache = "64KB";
  217. cpu-dcache = "64KB";
  218. cpu-l2cache = "1MB";
  219. cpu-tlb = "1024 4-ways";
  220. cpu-cacheline = "64Bytes";
  221. cpu-vector = "0.7.1";
  222. #cooling-cells = <2>;
  223. operating-points = <
  224. /* kHz uV */
  225. 300000 600000
  226. 800000 700000
  227. 1500000 800000
  228. 1848000 1000000
  229. >;
  230. light,dvddm-operating-points = <
  231. /* kHz uV */
  232. 300000 750000
  233. 800000 800000
  234. 1500000 800000
  235. 1848000 1000000
  236. >;
  237. clock-latency = <61036>;
  238. clocks = <&clk C910_CCLK>,
  239. <&clk C910_CCLK_I0>,
  240. <&clk CPU_PLL1_FOUTPOSTDIV>,
  241. <&clk CPU_PLL0_FOUTPOSTDIV>;
  242. clock-names = "c910_cclk", "c910_cclk_i0",
  243. "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
  244. dvdd-supply = <&dvdd_cpu_reg>;
  245. dvddm-supply = <&dvddm_cpu_reg>;
  246. cpu2_intc: interrupt-controller {
  247. #interrupt-cells = <1>;
  248. compatible = "riscv,cpu-intc";
  249. interrupt-controller;
  250. };
  251. };
  252. c910_3: cpu@3 {
  253. device_type = "cpu";
  254. reg = <3>;
  255. status = "okay";
  256. compatible = "riscv";
  257. riscv,isa = "rv64imafdcvsu";
  258. mmu-type = "riscv,sv39";
  259. cpu-freq = "1.848Ghz";
  260. cpu-icache = "64KB";
  261. cpu-dcache = "64KB";
  262. cpu-l2cache = "1MB";
  263. cpu-tlb = "1024 4-ways";
  264. cpu-cacheline = "64Bytes";
  265. cpu-vector = "0.7.1";
  266. #cooling-cells = <2>;
  267. operating-points = <
  268. /* kHz uV */
  269. 300000 600000
  270. 800000 700000
  271. 1500000 800000
  272. 1848000 1000000
  273. >;
  274. light,dvddm-operating-points = <
  275. /* kHz uV */
  276. 300000 750000
  277. 800000 800000
  278. 1500000 800000
  279. 1848000 1000000
  280. >;
  281. clock-latency = <61036>;
  282. clocks = <&clk C910_CCLK>,
  283. <&clk C910_CCLK_I0>,
  284. <&clk CPU_PLL1_FOUTPOSTDIV>,
  285. <&clk CPU_PLL0_FOUTPOSTDIV>;
  286. clock-names = "c910_cclk", "c910_cclk_i0",
  287. "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
  288. dvdd-supply = <&dvdd_cpu_reg>;
  289. dvddm-supply = <&dvddm_cpu_reg>;
  290. cpu3_intc: interrupt-controller {
  291. #interrupt-cells = <1>;
  292. compatible = "riscv,cpu-intc";
  293. interrupt-controller;
  294. };
  295. };
  296. };
  297. display-subsystem {
  298. compatible = "verisilicon,display-subsystem";
  299. ports = <&dpu_disp0>, <&dpu_disp1>;
  300. status = "disabled";
  301. };
  302. dpu-encoders {
  303. compatible = "simple-bus";
  304. #address-cells = <1>;
  305. #size-cells = <0>;
  306. dpu_enc0: dpu-encoder@0 {
  307. /* default encoder is DSI */
  308. compatible = "verisilicon,dsi-encoder";
  309. reg = <0>;
  310. status = "disabled";
  311. ports {
  312. #address-cells = <1>;
  313. #size-cells = <0>;
  314. /* input */
  315. port@0 {
  316. reg = <0>;
  317. enc0_in: endpoint {
  318. remote-endpoint = <&disp0_out>;
  319. };
  320. };
  321. };
  322. };
  323. dpu_enc1: dpu-encoder@1 {
  324. /* default encoder is DSI */
  325. compatible = "verisilicon,dsi-encoder";
  326. reg = <1>;
  327. status = "disabled";
  328. ports {
  329. #address-cells = <1>;
  330. #size-cells = <0>;
  331. /* input */
  332. port@0 {
  333. reg = <0>;
  334. enc1_in: endpoint {
  335. remote-endpoint = <&disp1_out>;
  336. };
  337. };
  338. };
  339. };
  340. };
  341. soc {
  342. compatible = "simple-bus";
  343. #address-cells = <2>;
  344. #size-cells = <2>;
  345. ranges;
  346. reset: reset-sample {
  347. compatible = "thead,reset-sample";
  348. plic-delegate = <0xff 0xd81ffffc>;
  349. entry-reg = <0xff 0xff019050>;
  350. entry-cnt = <4>;
  351. control-reg = <0xff 0xff015004>;
  352. control-val = <0x1c>;
  353. csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
  354. };
  355. clint0: clint@ffdc000000 {
  356. compatible = "riscv,clint0";
  357. interrupts-extended = <
  358. &cpu0_intc 3 &cpu0_intc 7
  359. &cpu1_intc 3 &cpu1_intc 7
  360. &cpu2_intc 3 &cpu2_intc 7
  361. &cpu3_intc 3 &cpu3_intc 7
  362. >;
  363. reg = <0xff 0xdc000000 0x0 0x04000000>;
  364. clint,has-no-64bit-mmio;
  365. };
  366. intc: interrupt-controller@ffd8000000 {
  367. #interrupt-cells = <1>;
  368. compatible = "riscv,plic0";
  369. interrupt-controller;
  370. interrupts-extended = <
  371. &cpu0_intc 0xffffffff &cpu0_intc 9
  372. &cpu1_intc 0xffffffff &cpu1_intc 9
  373. &cpu2_intc 0xffffffff &cpu2_intc 9
  374. &cpu3_intc 0xffffffff &cpu3_intc 9
  375. >;
  376. reg = <0xff 0xd8000000 0x0 0x04000000>;
  377. reg-names = "control";
  378. riscv,max-priority = <7>;
  379. riscv,ndev = <240>;
  380. };
  381. clocks {
  382. compatible = "simple-bus";
  383. #address-cells = <1>;
  384. #size-cells = <0>;
  385. dummy_clock_apb: apb-clock@0 {
  386. compatible = "fixed-clock";
  387. reg = <0>; /* Not address, just for index */
  388. clock-frequency = <62500000>;
  389. clock-output-names = "dummy_clock_apb";
  390. #clock-cells = <0>;
  391. };
  392. dummy_clock_ref: ref-clock@1 {
  393. compatible = "fixed-clock";
  394. reg = <1>; /* Not address, just for index */
  395. clock-frequency = <50000000>;
  396. clock-output-names = "dummy_clock_ref";
  397. #clock-cells = <0>;
  398. };
  399. dummy_clock_suspend: suspend-clock@2 {
  400. compatible = "fixed-clock";
  401. reg = <2>; /* Not address, just for index */
  402. clock-frequency = <50000000>;
  403. clock-output-names = "dummy_clock_suspend";
  404. #clock-cells = <0>;
  405. };
  406. dummy_clock_rtc: rtc-clock@3 {
  407. compatible = "fixed-clock";
  408. reg = <3>; /* Not address, just for index */
  409. clock-frequency = <32768>;
  410. clock-output-names = "dummy_clock_rtc";
  411. #clock-cells = <0>;
  412. };
  413. dummy_clock_ahb: ahb-clock@4 {
  414. compatible = "fixed-clock";
  415. reg = <4>; /* Not address, just for index */
  416. clock-frequency = <50000000>;
  417. clock-output-names = "dummy_clock_ahb";
  418. #clock-cells = <0>;
  419. };
  420. dummy_clock_gpu: gpu-clock@6 {
  421. compatible = "fixed-clock";
  422. reg = <6>; /* Not address, just for index */
  423. clock-frequency = <18000000>;
  424. clock-output-names = "dummy_clock_gpu";
  425. #clock-cells = <0>;
  426. };
  427. dummy_clock_dphy_ref: dphy-ref-clock@7 {
  428. compatible = "fixed-clock";
  429. reg = <7>; /* Not address, just for index */
  430. clock-frequency = <24000000>;
  431. clock-output-names = "dummy_clock_dphy_ref";
  432. #clock-cells = <0>;
  433. };
  434. dummy_clock_dphy_cfg: dphy-cfg-clock@8 {
  435. compatible = "fixed-clock";
  436. reg = <8>; /* Not address, just for index */
  437. clock-frequency = <24000000>;
  438. clock-output-names = "dummy_clock_dphy_cfg";
  439. #clock-cells = <0>;
  440. };
  441. dummy_clock_dpu_pixel0: dpu-pixel-clock@9 {
  442. compatible = "fixed-clock";
  443. reg = <9>;
  444. clock-frequency = <72000000>;
  445. clock-output-names = "dummy_clock_dpu_pixel0";
  446. #clock-cells = <0>;
  447. };
  448. dummy_clock_dpu_pixel1: dpu-pixel-clock@10 {
  449. compatible = "fixed-clock";
  450. reg = <10>;
  451. clock-frequency = <74250000>;
  452. clock-output-names = "dummy_clock_dpu_pixel1";
  453. #clock-cells = <0>;
  454. };
  455. osc_32k: clock-osc-32k@11 {
  456. compatible = "fixed-clock";
  457. reg = <11>;
  458. #clock-cells = <0>;
  459. clock-frequency = <32768>;
  460. clock-output-names = "osc_32k";
  461. };
  462. osc_24m: clock-osc-24m@12 {
  463. compatible = "fixed-clock";
  464. reg = <12>;
  465. #clock-cells = <0>;
  466. clock-frequency = <24000000>;
  467. clock-output-names = "osc_24m";
  468. };
  469. rc_24m: clock-rc-24m@13 {
  470. compatible = "fixed-clock";
  471. reg = <13>;
  472. #clock-cells = <0>;
  473. clock-frequency = <24000000>;
  474. clock-output-names = "rc_24m";
  475. };
  476. dummy_clock_eip: eip-clock@14 {
  477. compatible = "fixed-clock";
  478. reg = <14>; /* Not address, just for index */
  479. clock-frequency = <400000000>;
  480. clock-output-names = "dummy_clock_eip";
  481. #clock-cells = <0>;
  482. };
  483. dummy_clock_spi: spi-clock@15 {
  484. compatible = "fixed-clock";
  485. reg = <15>; /* Not address, just for index */
  486. clock-frequency = <396000000>;
  487. clock-output-names = "dummy_clock_spi";
  488. #clock-cells = <0>;
  489. };
  490. dummy_clock_qspi: spi-clock@16 {
  491. compatible = "fixed-clock";
  492. reg = <15>; /* Not address, just for index */
  493. clock-frequency = <792000000>;
  494. clock-output-names = "dummy_clock_qspi";
  495. #clock-cells = <0>;
  496. };
  497. dummy_gmac_ahb: gmac-ahb-clock@16 {
  498. compatible = "fixed-clock";
  499. reg = <16>;
  500. clock-frequency = <250000000>;
  501. clock-output-names = "dummy_gmac_ahb";
  502. #clock-cells = <0>;
  503. };
  504. dummy_clock_gmac: gmac-clock@17 {
  505. compatible = "fixed-clock";
  506. reg = <17>;
  507. clock-frequency = <500000000>;
  508. clock-output-names = "dummy_clock_gmac";
  509. #clock-cells = <0>;
  510. };
  511. dummy_clock_sdhci: sdhci-clock@18 {
  512. compatible = "fixed-clock";
  513. reg = <18>; /* Not address, just for index */
  514. clock-frequency = <198000000>;
  515. clock-output-names = "dummy_clock_sdhci";
  516. #clock-cells = <0>;
  517. };
  518. dummy_clock_aonsys_clk: aonsys-clk-clock@19 {
  519. compatible = "fixed-clock";
  520. reg = <19>; /* Not address, just for index */
  521. clock-frequency = <73728000>;
  522. clock-output-names = "dummy_clock_aonsys_clk";
  523. #clock-cells = <0>;
  524. };
  525. dummy_clock_uart_sclk: uart-sclk-clock@20 {
  526. compatible = "fixed-clock";
  527. reg = <20>; /* Not address, just for index */
  528. clock-frequency = <100000000>;
  529. clock-output-names = "dummy_clock_uart_sclk";
  530. #clock-cells = <0>;
  531. };
  532. dummy_clock_visys: visys-dummy-clock@21 {
  533. compatible = "fixed-clock";
  534. reg = <21>;
  535. clock-frequency = <24000000>;
  536. #clock-cells = <0>;
  537. };
  538. };
  539. iso7816: iso7816-card@fff7f30000 {
  540. compatible = "thead,light-iso7816-card";
  541. reg = <0xff 0xf7f30000 0x0 0x4000>;
  542. pinctrl-names = "default";
  543. pinctrl-0 = <&pinctrl_iso7816>;
  544. interrupts = <69>;
  545. interrupt-parent = <&intc>;
  546. status = "disabled";
  547. };
  548. teesys_syscon: teesys-reg@ffff200000 {
  549. compatible = "syscon";
  550. reg = <0xff 0xff200000 0x0 0x10000>;
  551. };
  552. visys_reg: visys-reg@ffe4040000 {
  553. compatible = "thead,light-visys-reg", "syscon";
  554. reg = <0xff 0xe4040000 0x0 0x1000>;
  555. status = "disabled";
  556. };
  557. dspsys_reg: dspsys-reg@ffef040000 {
  558. compatible = "thead,light-dspsys-reg", "syscon";
  559. reg = <0xff 0xef040000 0x0 0x1000>;
  560. status = "okay";
  561. };
  562. audio_ioctrl: audio_ioctrl@ffcb01d000 {
  563. compatible = "thead,light-audio-ioctrl-reg", "syscon";
  564. reg = <0xff 0xcb01d000 0x0 0x1000>;
  565. status = "okay";
  566. };
  567. audio_cpr: audio_cpr@ffcb000000 {
  568. compatible = "thead,light-audio-cpr-reg", "syscon";
  569. reg = <0xff 0xcb000000 0x0 0x1000>;
  570. status = "okay";
  571. };
  572. nvmem_controller: efuse@ffff210000 {
  573. compatible = "thead,light-fm-efuse", "syscon";
  574. reg = <0xff 0xff210000 0x0 0x10000>;
  575. thead,teesys = <&teesys_syscon>;
  576. #address-cells = <1>;
  577. #size-cells = <1>;
  578. gmac0_mac_address: mac-address@176 {
  579. reg = <0xb0 6>;
  580. };
  581. gmac1_mac_address: mac-address@184 {
  582. reg = <0xb8 6>;
  583. };
  584. };
  585. misc_sysreg: misc_sysreg@ffec02c000 {
  586. compatible = "thead,light-misc-sysreg", "syscon";
  587. reg = <0xff 0xec02c000 0x0 0x1000>;
  588. status = "okay";
  589. };
  590. usb3_drd: usb3_drd@ffec03f000 {
  591. compatible = "thead,light-usb3-drd", "syscon";
  592. reg = <0xff 0xec03f000 0x0 0x1000>;
  593. status = "okay";
  594. };
  595. gpio0: gpio@ffec005000 {
  596. compatible = "snps,dw-apb-gpio";
  597. reg = <0xff 0xec005000 0x0 0x1000>;
  598. #address-cells = <1>;
  599. #size-cells = <0>;
  600. gpio0_porta: gpio0-controller@0 {
  601. compatible = "snps,dw-apb-gpio-port";
  602. gpio-controller;
  603. #gpio-cells = <2>;
  604. nr-gpios-snps = <32>;
  605. reg = <0>;
  606. interrupt-controller;
  607. #interrupt-cells = <2>;
  608. interrupt-parent = <&intc>;
  609. interrupts = <56>;
  610. };
  611. };
  612. gpio1: gpio@ffec006000 {
  613. compatible = "snps,dw-apb-gpio";
  614. reg = <0xff 0xec006000 0x0 0x1000>;
  615. #address-cells = <1>;
  616. #size-cells = <0>;
  617. gpio1_porta: gpio1-controller@0 {
  618. compatible = "snps,dw-apb-gpio-port";
  619. gpio-controller;
  620. #gpio-cells = <2>;
  621. nr-gpios-snps = <32>;
  622. reg = <0>;
  623. interrupt-controller;
  624. #interrupt-cells = <2>;
  625. interrupt-parent = <&intc>;
  626. interrupts = <57>;
  627. };
  628. };
  629. gpio2: gpio@ffe7f34000 {
  630. compatible = "snps,dw-apb-gpio";
  631. reg = <0xff 0xe7f34000 0x0 0x1000>;
  632. #address-cells = <1>;
  633. #size-cells = <0>;
  634. gpio2_porta: gpio2-controller@0 {
  635. compatible = "snps,dw-apb-gpio-port";
  636. gpio-controller;
  637. #gpio-cells = <2>;
  638. nr-gpios-snps = <32>;
  639. reg = <0>;
  640. interrupt-controller;
  641. #interrupt-cells = <2>;
  642. interrupt-parent = <&intc>;
  643. interrupts = <58>;
  644. };
  645. };
  646. gpio3: gpio@ffe7f38000 {
  647. compatible = "snps,dw-apb-gpio";
  648. reg = <0xff 0xe7f38000 0x0 0x1000>;
  649. #address-cells = <1>;
  650. #size-cells = <0>;
  651. gpio3_porta: gpio3-controller@0 {
  652. compatible = "snps,dw-apb-gpio-port";
  653. gpio-controller;
  654. #gpio-cells = <2>;
  655. nr-gpios-snps = <32>;
  656. reg = <0>;
  657. interrupt-controller;
  658. #interrupt-cells = <2>;
  659. interrupt-parent = <&intc>;
  660. interrupts = <59>;
  661. };
  662. };
  663. ao_gpio: gpio@fffff41000 {
  664. compatible = "snps,dw-apb-gpio";
  665. reg = <0xff 0xfff41000 0x0 0x1000>;
  666. #address-cells = <1>;
  667. #size-cells = <0>;
  668. ao_gpio_porta: ao_gpio-controller@0 {
  669. compatible = "snps,dw-apb-gpio-port";
  670. gpio-controller;
  671. #gpio-cells = <2>;
  672. nr-gpios-snps = <32>;
  673. reg = <0>;
  674. interrupt-controller;
  675. #interrupt-cells = <2>;
  676. interrupt-parent = <&intc>;
  677. interrupts = <76>;
  678. };
  679. };
  680. ao_gpio4: gpio@fffff52000 {
  681. compatible = "snps,dw-apb-gpio";
  682. reg = <0xff 0xfff52000 0x0 0x1000>;
  683. #address-cells = <1>;
  684. #size-cells = <0>;
  685. ao_gpio4_porta: ao_gpio4-controller@0 {
  686. compatible = "snps,dw-apb-gpio-port";
  687. gpio-controller;
  688. #gpio-cells = <2>;
  689. nr-gpios-snps = <32>;
  690. reg = <0>;
  691. interrupt-controller;
  692. #interrupt-cells = <2>;
  693. interrupt-parent = <&intc>;
  694. interrupts = <55>;
  695. };
  696. };
  697. padctrl1_apsys: pinctrl1-apsys@ffe7f3c000 {
  698. compatible = "thead,light-fm-left-pinctrl";
  699. reg = <0xff 0xe7f3c000 0x0 0x1000>;
  700. status = "okay";
  701. };
  702. padctrl0_apsys: padctrl0-apsys@ffec007000 {
  703. compatible = "thead,light-fm-right-pinctrl";
  704. reg = <0xff 0xec007000 0x0 0x1000>;
  705. status = "okay";
  706. };
  707. pwm: pwm@ffec01c000 {
  708. compatible = "thead,pwm-light";
  709. reg = <0xff 0xec01c000 0x0 0x4000>;
  710. #pwm-cells = <2>;
  711. clocks = <&clk CLKGEN_PWM_PCLK>,
  712. <&clk CLKGEN_PWM_CCLK>;
  713. clock-names = "pclk", "cclk";
  714. pinctrl-names = "default";
  715. pinctrl-0 = <&pinctrl_pwm>;
  716. };
  717. timer0: timer@ffefc32000 {
  718. compatible = "snps,dw-apb-timer";
  719. reg = <0xff 0xefc32000 0x0 0x14>;
  720. clocks = <&dummy_clock_apb>;
  721. clock-names = "timer";
  722. clock-frequency = <62500000>;
  723. interrupts = <16>;
  724. interrupt-parent = <&intc>;
  725. status = "okay";
  726. };
  727. timer1: timer@ffefc32014 {
  728. compatible = "snps,dw-apb-timer";
  729. reg = <0xff 0xefc32014 0x0 0x14>;
  730. clocks = <&dummy_clock_apb>;
  731. clock-names = "timer";
  732. clock-frequency = <62500000>;
  733. interrupts = <17>;
  734. interrupt-parent = <&intc>;
  735. status = "okay";
  736. };
  737. timer2: timer@ffefc32028 {
  738. compatible = "snps,dw-apb-timer";
  739. reg = <0xff 0xefc32028 0x0 0x14>;
  740. clocks = <&dummy_clock_apb>;
  741. clock-names = "timer";
  742. clock-frequency = <62500000>;
  743. interrupts = <18>;
  744. interrupt-parent = <&intc>;
  745. status = "disabled";
  746. };
  747. timer3: timer@ffefc3203c {
  748. compatible = "snps,dw-apb-timer";
  749. reg = <0xff 0xefc3203c 0x0 0x14>;
  750. clocks = <&dummy_clock_apb>;
  751. clock-names = "timer";
  752. clock-frequency = <62500000>;
  753. interrupts = <19>;
  754. interrupt-parent = <&intc>;
  755. status = "disabled";
  756. };
  757. padctrl_aosys: padctrl-aosys@fffff4a000 {
  758. compatible = "thead,light-fm-aon-pinctrl";
  759. reg = <0xff 0xfff4a000 0x0 0x2000>;
  760. status = "okay";
  761. };
  762. timer4: timer@ffffc33000 {
  763. compatible = "snps,dw-apb-timer";
  764. reg = <0xff 0xffc33000 0x0 0x14>;
  765. clocks = <&dummy_clock_apb>;
  766. clock-names = "timer";
  767. clock-frequency = <62500000>;
  768. interrupts = <20>;
  769. interrupt-parent = <&intc>;
  770. status = "disabled";
  771. };
  772. timer5: timer@ffffc33014 {
  773. compatible = "snps,dw-apb-timer";
  774. reg = <0xff 0xffc33014 0x0 0x14>;
  775. clocks = <&dummy_clock_apb>;
  776. clock-names = "timer";
  777. clock-frequency = <62500000>;
  778. interrupts = <21>;
  779. interrupt-parent = <&intc>;
  780. status = "disabled";
  781. };
  782. timer6: timer@ffffc33028 {
  783. compatible = "snps,dw-apb-timer";
  784. reg = <0xff 0xffc33028 0x0 0x14>;
  785. clocks = <&dummy_clock_apb>;
  786. clock-names = "timer";
  787. clock-frequency = <62500000>;
  788. interrupts = <22>;
  789. interrupt-parent = <&intc>;
  790. status = "disabled";
  791. };
  792. timer7: timer@ffffc3303c {
  793. compatible = "snps,dw-apb-timer";
  794. reg = <0xff 0xffc3303c 0x0 0x14>;
  795. clocks = <&dummy_clock_apb>;
  796. clock-names = "timer";
  797. clock-frequency = <62500000>;
  798. interrupts = <23>;
  799. interrupt-parent = <&intc>;
  800. status = "disabled";
  801. };
  802. uart0: serial@ffe7014000 { /* Normal serial, for C910 log */
  803. compatible = "snps,dw-apb-uart";
  804. reg = <0xff 0xe7014000 0x0 0x4000>;
  805. interrupt-parent = <&intc>;
  806. interrupts = <36>;
  807. clocks = <&clk CLKGEN_UART0_SCLK>;
  808. clock-names = "baudclk";
  809. reg-shift = <2>;
  810. reg-io-width = <4>;
  811. hw-flow-control = "unsupport";
  812. status = "okay";
  813. };
  814. uart1: serial@ffe7f00000 { /* Normal serial, for C902 log */
  815. compatible = "snps,dw-apb-uart";
  816. reg = <0xff 0xe7f00000 0x0 0x4000>;
  817. interrupt-parent = <&intc>;
  818. interrupts = <37>;
  819. clocks = <&clk CLKGEN_UART1_SCLK>;
  820. clock-names = "baudclk";
  821. reg-shift = <2>;
  822. reg-io-width = <4>;
  823. hw-flow-control = "unsupport";
  824. status = "okay";
  825. };
  826. uart2: serial@ffec010000 { /* IRDA supported serial, not in 85P bit */
  827. compatible = "snps,dw-apb-uart";
  828. reg = <0xff 0xec010000 0x0 0x4000>;
  829. interrupt-parent = <&intc>;
  830. interrupts = <38>;
  831. clocks = <&clk CLKGEN_UART2_SCLK>;
  832. clock-names = "baudclk";
  833. reg-shift = <2>;
  834. reg-io-width = <4>;
  835. hw-flow-control = "unsupport";
  836. status = "disabled";
  837. };
  838. uart3: serial@ffe7f04000 { /* IRDA supported serial, not in 85P bit */
  839. compatible = "snps,dw-apb-uart";
  840. reg = <0xff 0xe7f04000 0x0 0x4000>;
  841. interrupt-parent = <&intc>;
  842. interrupts = <39>;
  843. clocks = <&clk CLKGEN_UART3_SCLK>;
  844. clock-names = "baudclk";
  845. reg-shift = <2>;
  846. reg-io-width = <4>;
  847. hw-flow-control = "unsupport";
  848. status = "disabled";
  849. };
  850. uart4: serial@fff7f08000 { /* High Speed with Flow Ctrol serial */
  851. compatible = "snps,dw-apb-uart";
  852. reg = <0xff 0xf7f08000 0x0 0x4000>;
  853. interrupt-parent = <&intc>;
  854. interrupts = <40>;
  855. clocks = <&clk CLKGEN_UART4_SCLK>;
  856. clock-names = "baudclk";
  857. reg-shift = <2>;
  858. reg-io-width = <4>;
  859. hw-flow-control = "support";
  860. status = "okay";
  861. };
  862. uart5: serial@fff7f0c000 { /* Normal serial, for external SE, not in 85P bit */
  863. compatible = "snps,dw-apb-uart";
  864. reg = <0xff 0xf7f0c000 0x0 0x4000>;
  865. interrupt-parent = <&intc>;
  866. interrupts = <41>;
  867. clocks = <&clk CLKGEN_UART5_SCLK>;
  868. clock-names = "baudclk";
  869. reg-shift = <2>;
  870. reg-io-width = <4>;
  871. hw-flow-control = "unsupport";
  872. status = "disabled";
  873. };
  874. adc: adc@0xfffff51000 {
  875. compatible = "thead,light-adc";
  876. reg = <0xff 0xfff51000 0x0 0x1000>;
  877. interrupt-parent = <&intc>;
  878. interrupts = <61>;
  879. clocks = <&dummy_clock_aonsys_clk>;
  880. clock-names = "adc";
  881. /* ADC pin is proprietary,no need to config pinctrl */
  882. status = "disabled";
  883. };
  884. spi0: spi@ffe700c000 {
  885. compatible = "snps,dw-apb-ssi";
  886. reg = <0xff 0xe700c000 0x0 0x1000>;
  887. pinctrl-names = "default";
  888. pinctrl-0 = <&pinctrl_spi0>;
  889. interrupt-parent = <&intc>;
  890. interrupts = <54>;
  891. clocks = <&dummy_clock_spi>;
  892. num-cs = <2>;
  893. #address-cells = <1>;
  894. #size-cells = <0>;
  895. };
  896. qspi0: spi@ffea000000 {
  897. compatible = "snps,dw-apb-ssi-quad";
  898. reg = <0xff 0xea000000 0x0 0x1000>;
  899. pinctrl-names = "default";
  900. pinctrl-0 = <&pinctrl_qspi0>;
  901. interrupt-parent = <&intc>;
  902. interrupts = <52>;
  903. clocks = <&dummy_clock_qspi>;
  904. #address-cells = <1>;
  905. #size-cells = <0>;
  906. };
  907. qspi1: spi@fff8000000 {
  908. compatible = "snps,dw-apb-ssi-quad";
  909. reg = <0xff 0xf8000000 0x0 0x1000>;
  910. pinctrl-names = "default";
  911. pinctrl-0 = <&pinctrl_qspi1>;
  912. interrupt-parent = <&intc>;
  913. interrupts = <53>;
  914. clocks = <&dummy_clock_spi>;
  915. #address-cells = <1>;
  916. #size-cells = <0>;
  917. };
  918. g2d: gc620@ffecc80000 {
  919. compatible = "thead,c910-gc620";
  920. reg = <0xff 0xecc80000 0x0 0x40000>;
  921. interrupt-parent = <&intc>;
  922. interrupts = <101>;
  923. interrupt-names = "irq_2d";
  924. clocks = <&vpsys_clk_gate LIGHT_VPSYS_G2D_PCLK>,
  925. <&vpsys_clk_gate LIGHT_VPSYS_G2D_ACLK>,
  926. <&vpsys_clk_gate LIGHT_VPSYS_G2D_CCLK>;
  927. clock-names = "pclk", "aclk", "cclk";
  928. status = "okay";
  929. };
  930. dsi0: dw-mipi-dsi0@ffef500000 {
  931. compatible = "thead,light-mipi-dsi", "simple-bus", "syscon";
  932. reg = <0xff 0xef500000 0x0 0x10000>;
  933. status = "disabled";
  934. dphy_0: dsi0-dphy {
  935. compatible = "thead,light-mipi-dphy";
  936. regmap = <&dsi0>;
  937. vosys-regmap = <&vosys_reg>;
  938. clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_REFCLK>,
  939. <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_CFG_CLK>,
  940. <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_PCLK>,
  941. <&clk OSC_24M>,
  942. <&clk OSC_24M>;
  943. clock-names = "refclk", "cfgclk", "pclk", "prefclk", "pcfgclk";
  944. #phy-cells = <0>;
  945. };
  946. dhost_0: dsi0-host {
  947. compatible = "verisilicon,dw-mipi-dsi";
  948. regmap = <&dsi0>;
  949. interrupt-parent = <&intc>;
  950. interrupts = <129>;
  951. clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_PCLK>,
  952. <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_PIXCLK>;
  953. clock-names = "pclk", "pixclk";
  954. phys = <&dphy_0>;
  955. phy-names = "dphy";
  956. #address-cells = <1>;
  957. #size-cells = <0>;
  958. };
  959. };
  960. dsi1: dw-mipi-dsi1@ffef510000 {
  961. compatible = "thead,light-mipi-dsi", "simple-bus", "syscon";
  962. reg = <0xff 0xef510000 0x0 0x10000>;
  963. status = "disabled";
  964. dphy_1: dsi1-dphy {
  965. compatible = "thead,light-mipi-dphy";
  966. regmap = <&dsi1>;
  967. vosys-regmap = <&vosys_reg>;
  968. clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_REFCLK>,
  969. <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_CFG_CLK>,
  970. <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_PCLK>,
  971. <&clk OSC_24M>,
  972. <&clk OSC_24M>;
  973. clock-names = "refclk", "cfgclk", "pclk", "prefclk", "pcfgclk";
  974. #phy-cells = <0>;
  975. };
  976. dhost_1: dsi1-host {
  977. compatible = "verisilicon,dw-mipi-dsi";
  978. regmap = <&dsi1>;
  979. interrupt-parent = <&intc>;
  980. interrupts = <129>;
  981. clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_PCLK>,
  982. <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_PIXCLK>;
  983. clock-names = "pclk", "pixclk";
  984. phys = <&dphy_1>;
  985. phy-names = "dphy";
  986. #address-cells = <1>;
  987. #size-cells = <0>;
  988. };
  989. };
  990. vosys_reg: vosys@ffef528000 {
  991. compatible = "thead,light-vo-subsys", "syscon";
  992. reg = <0xff 0xef528000 0x0 0x1000>;
  993. status = "okay";
  994. };
  995. hdmi_tx: dw-hdmi-tx@ffef540000 {
  996. compatible = "thead,light-hdmi-tx";
  997. reg = <0xff 0xef540000 0x0 0x40000>;
  998. interrupt-parent = <&intc>;
  999. interrupts = <111>;
  1000. clocks = <&vosys_clk_gate LIGHT_CLKGEN_HDMI_PCLK>,
  1001. <&vosys_clk_gate LIGHT_CLKGEN_HDMI_SFR_CLK>,
  1002. <&vosys_clk_gate LIGHT_CLKGEN_HDMI_CEC_CLK>,
  1003. <&vosys_clk_gate LIGHT_CLKGEN_HDMI_PIXCLK>,
  1004. <&vosys_clk_gate LIGHT_CLKGEN_HDMI_I2S_CLK>;
  1005. clock-names = "iahb", "isfr", "cec", "pixclk", "i2s";
  1006. reg-io-width = <4>;
  1007. phy_version = <301>;
  1008. /* TODO: add phy property */
  1009. status = "disabled";
  1010. };
  1011. dpu: dc8200@ffef600000 {
  1012. compatible = "verisilicon,dc8200";
  1013. #address-cells = <1>;
  1014. #size-cells = <0>;
  1015. reg = <0xff 0xef600000 0x0 0x100>,
  1016. <0xff 0xef600800 0x0 0x2000>,
  1017. <0xff 0xef630010 0x0 0x60>;
  1018. interrupt-parent = <&intc>;
  1019. interrupts = <93>;
  1020. clocks = <&vosys_clk_gate LIGHT_CLKGEN_DPU_CCLK>,
  1021. <&vosys_clk_gate LIGHT_CLKGEN_DPU_PIXCLK0>,
  1022. <&vosys_clk_gate LIGHT_CLKGEN_DPU_PIXCLK1>,
  1023. <&vosys_clk_gate LIGHT_CLKGEN_DPU_ACLK>,
  1024. <&vosys_clk_gate LIGHT_CLKGEN_DPU_HCLK>,
  1025. <&clk DPU0_PLL_DIV_CLK>,
  1026. <&clk DPU1_PLL_DIV_CLK>,
  1027. <&clk DPU0_PLL_FOUTPOSTDIV>,
  1028. <&clk DPU1_PLL_FOUTPOSTDIV>;
  1029. clock-names = "core_clk", "pix_clk0", "pix_clk1",
  1030. "axi_clk", "cfg_clk", "pixclk0",
  1031. "pixclk1", "dpu0_pll_foutpostdiv",
  1032. "dpu1_pll_foutpostdiv";
  1033. status = "disabled";
  1034. dpu_disp0: port@0 {
  1035. reg = <0>;
  1036. disp0_out: endpoint {
  1037. remote-endpoint = <&enc0_in>;
  1038. };
  1039. };
  1040. dpu_disp1: port@1 {
  1041. reg = <1>;
  1042. disp1_out: endpoint {
  1043. remote-endpoint = <&enc1_in>;
  1044. };
  1045. };
  1046. };
  1047. watchdog0: watchdog@ffefc30000 {
  1048. compatible = "snps,dw-wdt";
  1049. reg = <0xff 0xefc30000 0x0 0x1000>;
  1050. interrupt-parent = <&intc>;
  1051. interrupts = <24>;
  1052. clocks = <&clk CLKGEN_WDT0_PCLK>;
  1053. clock-names = "tclk";
  1054. resets = <&rst LIGHT_RESET_WDT0>;
  1055. status = "okay";
  1056. };
  1057. watchdog1: watchdog@ffefc31000 {
  1058. compatible = "snps,dw-wdt";
  1059. reg = <0xff 0xefc31000 0x0 0x1000>;
  1060. interrupt-parent = <&intc>;
  1061. interrupts = <25>;
  1062. clocks = <&clk CLKGEN_WDT1_PCLK>;
  1063. clock-names = "tclk";
  1064. resets = <&rst LIGHT_RESET_WDT1>;
  1065. status = "okay";
  1066. };
  1067. rtc: rtc@fffff40000 {
  1068. compatible = "apm,xgene-rtc";
  1069. reg = <0xff 0xfff40000 0x0 0x1000>;
  1070. interrupt-parent = <&intc>;
  1071. interrupts = <74>;
  1072. clocks = <&dummy_clock_rtc>;
  1073. clock-names = "rtc";
  1074. status = "okay";
  1075. };
  1076. usb_1: usb@ffec03f000 {
  1077. compatible = "thead,dwc3";
  1078. usb3-misc-regmap = <&misc_sysreg>;
  1079. usb3-drd-regmap = <&usb3_drd>;
  1080. #address-cells = <2>;
  1081. #size-cells = <2>;
  1082. ranges;
  1083. usb: dwc3@ffe7040000 {
  1084. compatible = "snps,dwc3";
  1085. reg = <0xff 0xe7040000 0x0 0x10000>;
  1086. interrupt-parent = <&intc>;
  1087. interrupts = <68>;
  1088. clocks = <&dummy_clock_ref>, <&dummy_clock_apb>, <&dummy_clock_suspend>;
  1089. clock-names = "ref", "bus_early", "suspend";
  1090. reg-shift = <2>;
  1091. reg-io-width = <4>;
  1092. maximum-speed = "super-speed";
  1093. dr_mode = "host";
  1094. dma-mask = <0xf 0xffffffff>;
  1095. snps,usb3_lpm_capable;
  1096. snps,usb_sofitpsync;
  1097. status = "okay";
  1098. };
  1099. };
  1100. pmu: pmu {
  1101. interrupt-parent = <&cpu0_intc>;
  1102. interrupts = <17>;
  1103. compatible = "riscv,c910_pmu";
  1104. };
  1105. clk: clock-controller@ffef010000 {
  1106. compatible = "thead,light-fm-ree-clk";
  1107. reg = <0xff 0xef010000 0x0 0x1000>;
  1108. #clock-cells = <1>;
  1109. clocks = <&osc_32k>, <&osc_24m>, <&rc_24m>;
  1110. clock-names = "osc_32k", "osc_24m", "rc_24m";
  1111. status = "okay";
  1112. };
  1113. rst: reset-controller@ffef014000 {
  1114. compatible = "thead,light-reset-src","syscon";
  1115. reg = <0xff 0xef014000 0x0 0x1000>;
  1116. #reset-cells = <1>;
  1117. status = "okay";
  1118. };
  1119. sys_reg: sys_reg@ffef010100 {
  1120. compatible = "thead,light_sys_reg";
  1121. reg = <0xff 0xef010100 0x0 0x100>;
  1122. status = "okay";
  1123. };
  1124. dmac0: dmac@ffefc00000 {
  1125. compatible = "snps,axi-dma-1.01a";
  1126. reg = <0xff 0xefc00000 0x0 0x1000>;
  1127. interrupt-parent = <&intc>;
  1128. interrupts = <27>;
  1129. clocks = <&dummy_clock_apb>, <&dummy_clock_apb>;
  1130. clock-names = "core-clk", "cfgr-clk";
  1131. #dma-cells = <1>;
  1132. dma-channels = <4>;
  1133. snps,block-size = <65536 65536 65536 65536>;
  1134. snps,priority = <0 1 2 3>;
  1135. snps,dma-masters = <1>;
  1136. snps,data-width = <4>;
  1137. snps,axi-max-burst-len = <16>;
  1138. status = "okay";
  1139. };
  1140. dmac1: tee_dmac@ffff340000 {
  1141. compatible = "snps,axi-dma-1.01a";
  1142. reg = <0xff 0xff340000 0x0 0x1000>;
  1143. interrupt-parent = <&intc>;
  1144. interrupts = <150>;
  1145. clocks = <&dummy_clock_apb>, <&dummy_clock_apb>;
  1146. clock-names = "core-clk", "cfgr-clk";
  1147. #dma-cells = <1>;
  1148. dma-channels = <4>;
  1149. snps,block-size = <65536 65536 65536 65536>;
  1150. snps,priority = <0 1 2 3>;
  1151. snps,dma-masters = <1>;
  1152. snps,data-width = <4>;
  1153. snps,axi-max-burst-len = <16>;
  1154. status = "disabled";
  1155. };
  1156. dmac2: audio_dmac@0xFFC8000000 {
  1157. compatible = "snps,axi-dma-1.01a";
  1158. reg = <0xff 0xc8000000 0x0 0x2000>;
  1159. interrupt-parent = <&intc>;
  1160. interrupts = <167>;
  1161. clocks = <&dummy_clock_apb>, <&dummy_clock_apb>;
  1162. clock-names = "core-clk", "cfgr-clk";
  1163. #dma-cells = <1>;
  1164. dma-channels = <16>;
  1165. snps,block-size = <65536 65536 65536 65536
  1166. 65536 65536 65536 65536
  1167. 65536 65536 65536 65536
  1168. 65536 65536 65536 65536>;
  1169. snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
  1170. snps,dma-masters = <1>;
  1171. snps,data-width = <4>;
  1172. snps,axi-max-burst-len = <16>;
  1173. status = "okay";
  1174. };
  1175. stmmac_axi_setup: stmmac-axi-config {
  1176. snps,wr_osr_lmt = <3>;
  1177. snps,rd_osr_lmt = <3>;
  1178. snps,blen = <16 8 4 0 0 0 0>;
  1179. };
  1180. gmac0: ethernet@ffe7070000 {
  1181. compatible = "thead,light-dwmac";
  1182. reg = <0xff 0xe7070000 0x0 0x2000
  1183. 0xff 0xec00301c 0x0 0x4
  1184. 0xff 0xec003020 0x0 0x4
  1185. 0xff 0xec003000 0x0 0x1c>;
  1186. reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg";
  1187. interrupt-parent = <&intc>;
  1188. interrupts = <66>;
  1189. interrupt-names = "macirq";
  1190. clocks = <&clk CLKGEN_GMAC0_CCLK>;
  1191. clock-names = "gmac_pll_clk";
  1192. snps,pbl = <32>;
  1193. snps,fixed-burst;
  1194. snps,axi-config = <&stmmac_axi_setup>;
  1195. nvmem-cells = <&gmac0_mac_address>;
  1196. nvmem-cell-names = "mac-address";
  1197. };
  1198. gmac1: ethernet@ffe7060000 {
  1199. compatible = "thead,light-dwmac";
  1200. reg = <0xff 0xe7060000 0x0 0x2000
  1201. 0xff 0xec00401c 0x0 0x4
  1202. 0xff 0xec004020 0x0 0x4
  1203. 0xff 0xec004000 0x0 0x1c>;
  1204. reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg";
  1205. interrupt-parent = <&intc>;
  1206. interrupts = <67>;
  1207. interrupt-names = "macirq";
  1208. clocks = <&clk CLKGEN_GMAC1_CCLK>;
  1209. clock-names = "gmac_pll_clk";
  1210. snps,pbl = <32>;
  1211. snps,fixed-burst;
  1212. snps,axi-config = <&stmmac_axi_setup>;
  1213. nvmem-cells = <&gmac1_mac_address>;
  1214. nvmem-cell-names = "mac-address";
  1215. };
  1216. emmc: sdhci@ffe7080000 {
  1217. compatible = "snps,dwcmshc-sdhci";
  1218. reg = <0xff 0xe7080000 0x0 0x10000
  1219. 0xff 0xef014060 0x0 0x4>;
  1220. interrupt-parent = <&intc>;
  1221. interrupts = <62>;
  1222. interrupt-names = "sdhciirq";
  1223. clocks = <&dummy_clock_sdhci>;
  1224. clock-names = "core";
  1225. };
  1226. sdhci0: sd@ffe7090000 {
  1227. compatible = "snps,dwcmshc-sdhci";
  1228. reg = <0xff 0xe7090000 0x0 0x10000
  1229. 0xff 0xef014064 0x0 0x4>;
  1230. interrupt-parent = <&intc>;
  1231. interrupts = <64>;
  1232. interrupt-names = "sdhci0irq";
  1233. clocks = <&dummy_clock_sdhci>;
  1234. clock-names = "core";
  1235. };
  1236. sdhci1: sd@ffe70a0000 {
  1237. compatible = "snps,dwcmshc-sdhci";
  1238. reg = <0xff 0xe70a0000 0x0 0x10000
  1239. 0xff 0xef014064 0x0 0x4>;
  1240. interrupt-parent = <&intc>;
  1241. interrupts = <71>;
  1242. interrupt-names = "sdhci1irq";
  1243. clocks = <&dummy_clock_sdhci>;
  1244. clock-names = "core";
  1245. };
  1246. hwspinlock: hwspinlock@ffefc10000 {
  1247. compatible = "light,hwspinlock";
  1248. reg = <0xff 0xefc10000 0x0 0x10000>;
  1249. status = "disabled";
  1250. };
  1251. npu: vha@fffc800000 {
  1252. compatible = "img,ax3386-nna";
  1253. reg = <0xff 0xfc800000 0x0 0x100000>;
  1254. interrupt-parent = <&intc>;
  1255. interrupts = <113>;
  1256. interrupt-names = "npuirq";
  1257. power-domains = <&pd LIGHT_AON_NPU_PD>;
  1258. clocks = <&clk CLKGEN_TOP_APB_SX_PCLK>,
  1259. <&clk CLKGEN_TOP_AXI4S_ACLK>;
  1260. clock-names = "pclk", "aclk";
  1261. vha_clk_rate = <1000000000>;
  1262. ldo_vha-supply = <&npu>;
  1263. dma-mask = <0xf 0xffffffff>;
  1264. status = "disabled";
  1265. };
  1266. gpu: gpu@ffef400000 {
  1267. compatible = "img,gpu";
  1268. reg = <0xff 0xef400000 0x0 0x100000>;
  1269. interrupt-parent = <&intc>;
  1270. interrupts = <102>;
  1271. interrupt-names = "gpuirq";
  1272. vosys-regmap = <&vosys_reg>;
  1273. power-domains = <&pd LIGHT_AON_GPU_PD>;
  1274. clocks = <&vosys_clk_gate LIGHT_CLKGEN_GPU_CORE_CLK>,
  1275. <&vosys_clk_gate LIGHT_CLKGEN_GPU_CFG_ACLK>;
  1276. clock-names = "cclk", "aclk";
  1277. gpu_clk_rate = <18000000>;
  1278. dma-mask = <0xf 0xffffffff>;
  1279. status = "disabled";
  1280. };
  1281. fce: fce@fffcc50000 {
  1282. compatible = "thead,light-fce";
  1283. reg = <0xff 0xfcc50000 0x0 0x10000>;
  1284. interrupt-parent = <&intc>;
  1285. interrupts = <100>;
  1286. interrupt-names = "fceirq";
  1287. clocks = <&vpsys_clk_gate LIGHT_VPSYS_FCE_ACLK>,
  1288. <&vpsys_clk_gate LIGHT_VPSYS_FCE_PCLK>;
  1289. clock-names = "aclk", "pclk";
  1290. dma-mask = <0xf 0xffffffff>;
  1291. status = "disabled";
  1292. };
  1293. vdec: vdec@ffecc00000 {
  1294. compatible = "thead,light-vc8000d";
  1295. reg = <0xff 0xecc00000 0x0 0x8000>;
  1296. interrupt-parent = <&intc>;
  1297. interrupts = <131>;
  1298. power-domains = <&pd LIGHT_AON_VDEC_PD>;
  1299. clocks = <&vpsys_clk_gate LIGHT_VPSYS_VDEC_ACLK>,
  1300. <&vpsys_clk_gate LIGHT_VPSYS_VDEC_CCLK>,
  1301. <&vpsys_clk_gate LIGHT_VPSYS_VDEC_PCLK>;
  1302. clock-names = "aclk", "cclk", "pclk";
  1303. status = "disabled";
  1304. };
  1305. venc: venc@ffecc10000 {
  1306. compatible = "thead,light-vc8000e";
  1307. reg = <0xff 0xecc10000 0x0 0x8000>;
  1308. interrupt-parent = <&intc>;
  1309. interrupts = <133>;
  1310. power-domains = <&pd LIGHT_AON_VENC_PD>;
  1311. clocks = <&vpsys_clk_gate LIGHT_VPSYS_VENC_ACLK>,
  1312. <&vpsys_clk_gate LIGHT_VPSYS_VENC_CCLK>,
  1313. <&vpsys_clk_gate LIGHT_VPSYS_VENC_PCLK>;
  1314. clock-names = "aclk", "cclk", "pclk";
  1315. status = "disabled";
  1316. };
  1317. isp_venc_shake: shake@ffe4078000 {
  1318. compatible = "thead,light-ivs";
  1319. reg = <0xff 0xe4078000 0x0 0x1000>;
  1320. interrupt-parent = <&intc>;
  1321. interrupts = <158>;
  1322. status = "disabled";
  1323. };
  1324. vidmem: vidmem@ffecc08000 {
  1325. compatible = "thead,light-vidmem";
  1326. reg = <0xff 0xecc08000 0x0 0x1000>;
  1327. status = "disabled";
  1328. };
  1329. light_i2s: light_i2s@ffe7034000 {
  1330. #sound-dai-cells = <1>;
  1331. compatible = "light,light-i2s";
  1332. reg = <0xff 0xe7034000 0x0 0x4000>;
  1333. pinctrl-names = "default";
  1334. pinctrl-0 = <&pinctrl_audio_i2s0>;
  1335. light,mode = "i2s-master";
  1336. light,sel = "ap_i2s";
  1337. interrupt-parent = <&intc>;
  1338. interrupts = <70>;
  1339. dmas = <&dmac0 35>, <&dmac0 40>;
  1340. dma-names = "tx", "rx";
  1341. light,dma_maxburst = <4>;
  1342. #dma-cells = <1>;
  1343. clocks = <&dummy_clock_apb>;
  1344. clock-names = "pclk";
  1345. status = "disabled";
  1346. };
  1347. i2s0: audio_i2s0@0xffcb014000 {
  1348. #sound-dai-cells = <1>;
  1349. compatible = "light,light-i2s";
  1350. reg = <0xff 0xcb014000 0x0 0x1000>;
  1351. audio-pin-regmap = <&audio_ioctrl>;
  1352. audio-cpr-regmap = <&audio_cpr>;
  1353. pinctrl-names = "default";
  1354. light,mode = "i2s-master";
  1355. light,sel = "i2s0";
  1356. interrupt-parent = <&intc>;
  1357. interrupts = <174>;
  1358. dmas = <&dmac2 9>, <&dmac2 16>;
  1359. dma-names = "tx", "rx";
  1360. light,dma_maxburst = <4>;
  1361. #dma-cells = <1>;
  1362. clocks = <&dummy_clock_apb>;
  1363. clock-names = "pclk";
  1364. status = "disabled";
  1365. };
  1366. i2s1: audio_i2s1@0xffcb015000 {
  1367. #sound-dai-cells = <1>;
  1368. compatible = "light,light-i2s";
  1369. reg = <0xff 0xcb015000 0x0 0x1000>;
  1370. audio-pin-regmap = <&audio_ioctrl>;
  1371. audio-cpr-regmap = <&audio_cpr>;
  1372. pinctrl-names = "default";
  1373. light,mode = "i2s-master";
  1374. light,sel = "i2s1";
  1375. interrupt-parent = <&intc>;
  1376. interrupts = <175>;
  1377. dmas = <&dmac2 11>, <&dmac2 17>;
  1378. dma-names = "tx", "rx";
  1379. light,dma_maxburst = <4>;
  1380. #dma-cells = <1>;
  1381. clocks = <&dummy_clock_apb>;
  1382. clock-names = "pclk";
  1383. status = "disabled";
  1384. };
  1385. i2s3: audio_i2s3@0xffcb017000 {
  1386. #sound-dai-cells = <1>;
  1387. compatible = "light,light-i2s";
  1388. reg = <0xff 0xcb017000 0x0 0x1000>;
  1389. pinctrl-names = "default";
  1390. light,mode = "i2s-master";
  1391. light,sel = "i2s3";
  1392. interrupt-parent = <&intc>;
  1393. interrupts = <177>;
  1394. dmas = <&dmac2 14>, <&dmac2 16>;
  1395. dma-names = "tx", "rx";
  1396. light,dma_maxburst = <4>;
  1397. #dma-cells = <1>;
  1398. clocks = <&dummy_clock_apb>;
  1399. clock-names = "pclk";
  1400. status = "disabled";
  1401. };
  1402. pvt: pvt@fffff4e000 {
  1403. compatible = "moortec,mr75203";
  1404. reg = <0xff 0xfff4e000 0x0 0x80>,
  1405. <0xff 0xfff4e080 0x0 0x100>,
  1406. <0xff 0xfff4e180 0x0 0x680>,
  1407. <0xff 0xfff4e800 0x0 0x600>;
  1408. reg-names = "common", "ts", "pd", "vm";
  1409. clocks = <&dummy_clock_aonsys_clk>;
  1410. #thermal-sensor-cells = <1>;
  1411. status = "okay";
  1412. };
  1413. i2c0: i2c@ffe7f20000 {
  1414. compatible = "snps,designware-i2c";
  1415. reg = <0xff 0xe7f20000 0x0 0x4000>;
  1416. interrupt-parent = <&intc>;
  1417. interrupts = <44>;
  1418. clocks = <&dummy_clock_apb>;
  1419. clock-frequency = <100000>;
  1420. ss_hcnt = /bits/ 16 <0x104>;
  1421. ss_lcnt = /bits/ 16 <0xec>;
  1422. fs_hcnt = /bits/ 16 <0x37>;
  1423. fs_lcnt = /bits/ 16 <0x42>;
  1424. fp_hcnt = /bits/ 16 <0x14>;
  1425. fp_lcnt = /bits/ 16 <0x1a>;
  1426. hs_hcnt = /bits/ 16 <0x9>;
  1427. hs_lcnt = /bits/ 16 <0x11>;
  1428. #address-cells = <1>;
  1429. #size-cells = <0>;
  1430. };
  1431. i2c1: i2c@ffe7f24000 {
  1432. compatible = "snps,designware-i2c";
  1433. reg = <0xff 0xe7f24000 0x0 0x4000>;
  1434. interrupt-parent = <&intc>;
  1435. interrupts = <45>;
  1436. clocks = <&dummy_clock_apb>;
  1437. clock-frequency = <100000>;
  1438. ss_hcnt = /bits/ 16 <0x104>;
  1439. ss_lcnt = /bits/ 16 <0xec>;
  1440. fs_hcnt = /bits/ 16 <0x37>;
  1441. fs_lcnt = /bits/ 16 <0x42>;
  1442. fp_hcnt = /bits/ 16 <0x14>;
  1443. fp_lcnt = /bits/ 16 <0x1a>;
  1444. hs_hcnt = /bits/ 16 <0x9>;
  1445. hs_lcnt = /bits/ 16 <0x11>;
  1446. #address-cells = <1>;
  1447. #size-cells = <0>;
  1448. };
  1449. i2c2: i2c@ffec00c000{
  1450. compatible = "snps,designware-i2c";
  1451. reg = <0xff 0xec00c000 0x0 0x4000>;
  1452. interrupt-parent = <&intc>;
  1453. interrupts = <46>;
  1454. clocks = <&dummy_clock_apb>;
  1455. clock-frequency = <100000>;
  1456. ss_hcnt = /bits/ 16 <0x104>;
  1457. ss_lcnt = /bits/ 16 <0xec>;
  1458. fs_hcnt = /bits/ 16 <0x37>;
  1459. fs_lcnt = /bits/ 16 <0x42>;
  1460. fp_hcnt = /bits/ 16 <0x14>;
  1461. fp_lcnt = /bits/ 16 <0x1a>;
  1462. hs_hcnt = /bits/ 16 <0x9>;
  1463. hs_lcnt = /bits/ 16 <0x11>;
  1464. status = "disabled";
  1465. #address-cells = <1>;
  1466. #size-cells = <0>;
  1467. };
  1468. i2c3: i2c@ffec014000{
  1469. compatible = "snps,designware-i2c";
  1470. reg = <0xff 0xec014000 0x0 0x4000>;
  1471. interrupt-parent = <&intc>;
  1472. interrupts = <47>;
  1473. clocks = <&dummy_clock_apb>;
  1474. clock-frequency = <100000>;
  1475. ss_hcnt = /bits/ 16 <0x104>;
  1476. ss_lcnt = /bits/ 16 <0xec>;
  1477. fs_hcnt = /bits/ 16 <0x37>;
  1478. fs_lcnt = /bits/ 16 <0x42>;
  1479. fp_hcnt = /bits/ 16 <0x14>;
  1480. fp_lcnt = /bits/ 16 <0x1a>;
  1481. hs_hcnt = /bits/ 16 <0x9>;
  1482. hs_lcnt = /bits/ 16 <0x11>;
  1483. status = "disabled";
  1484. #address-cells = <1>;
  1485. #size-cells = <0>;
  1486. };
  1487. i2c4: i2c@ffe7f28000{
  1488. compatible = "snps,designware-i2c";
  1489. reg = <0xff 0xe7f28000 0x0 0x4000>;
  1490. interrupt-parent = <&intc>;
  1491. interrupts = <48>;
  1492. clocks = <&dummy_clock_apb>;
  1493. clock-frequency = <100000>;
  1494. ss_hcnt = /bits/ 16 <0x104>;
  1495. ss_lcnt = /bits/ 16 <0xec>;
  1496. fs_hcnt = /bits/ 16 <0x37>;
  1497. fs_lcnt = /bits/ 16 <0x42>;
  1498. fp_hcnt = /bits/ 16 <0x14>;
  1499. fp_lcnt = /bits/ 16 <0x1a>;
  1500. hs_hcnt = /bits/ 16 <0x9>;
  1501. hs_lcnt = /bits/ 16 <0x11>;
  1502. status = "disabled";
  1503. #address-cells = <1>;
  1504. #size-cells = <0>;
  1505. };
  1506. audio_i2c0: i2c@0xffcb01a000 {
  1507. compatible = "snps,designware-i2c";
  1508. reg = <0xff 0xcb01a000 0x0 0x1000>;
  1509. interrupt-parent = <&intc>;
  1510. interrupts = <182>;
  1511. clocks = <&dummy_clock_apb>;
  1512. clock-frequency = <100000>;
  1513. ss_hcnt = /bits/ 16 <0x82>;
  1514. ss_lcnt = /bits/ 16 <0x78>;
  1515. fs_hcnt = /bits/ 16 <0x37>;
  1516. fs_lcnt = /bits/ 16 <0x42>;
  1517. fp_hcnt = /bits/ 16 <0x14>;
  1518. fp_lcnt = /bits/ 16 <0x1a>;
  1519. hs_hcnt = /bits/ 16 <0x5>;
  1520. hs_lcnt = /bits/ 16 <0x15>;
  1521. #address-cells = <1>;
  1522. #size-cells = <0>;
  1523. };
  1524. isp0: isp@ffe4100000 {
  1525. compatible = "thead,light-isp";
  1526. reg = <0xff 0xe4100000 0x0 0x10000>;
  1527. interrupt-parent = <&intc>;
  1528. interrupts = <117>,<118>;
  1529. clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP0_ACLK>,
  1530. <&visys_clk_gate LIGHT_CLKGEN_ISP0_HCLK>,
  1531. <&visys_clk_gate LIGHT_CLKGEN_ISP0_PIXELCLK>,
  1532. <&visys_clk_gate LIGHT_CLKGEN_ISP0_CLK>;
  1533. clock-names = "aclk", "hclk", "isp0_pclk", "cclk";
  1534. status = "disabled";
  1535. };
  1536. isp1: isp@ffe4110000 {
  1537. compatible = "thead,light-isp";
  1538. reg = <0xff 0xe4110000 0x0 0x10000>;
  1539. interrupt-parent = <&intc>;
  1540. interrupts = <120>,<121>;
  1541. clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP0_ACLK>,
  1542. <&visys_clk_gate LIGHT_CLKGEN_ISP0_HCLK>,
  1543. <&visys_clk_gate LIGHT_CLKGEN_ISP0_PIXELCLK>,
  1544. <&visys_clk_gate LIGHT_CLKGEN_ISP1_CLK>,
  1545. <&visys_clk_gate LIGHT_CLKGEN_ISP1_PIXELCLK>;
  1546. clock-names = "aclk", "hclk", "isp0_pclk", "cclk", "isp1_pclk";
  1547. status = "disabled";
  1548. };
  1549. isp_ry0: isp_ry@ffe4120000 {
  1550. compatible = "thead,light-isp_ry";
  1551. reg = <0xff 0xe4120000 0x0 0x10000>;
  1552. interrupt-parent = <&intc>;
  1553. interrupts = <123>,<124>;
  1554. clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_ACLK>,
  1555. <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_HCLK>,
  1556. <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_CCLK>;
  1557. clock-names = "aclk", "hclk", "cclk";
  1558. status = "disabled";
  1559. };
  1560. dewarp: dewarp@ffe4130000 {
  1561. compatible = "thead,light-dewarp";
  1562. reg = <0xff 0xe4130000 0x0 0x10000>;
  1563. interrupt-parent = <&intc>;
  1564. interrupts = <98>,<99>;
  1565. clocks = <&visys_clk_gate LIGHT_CLKGEN_DW200_ACLK>,
  1566. <&visys_clk_gate LIGHT_CLKGEN_DW200_HCLK>,
  1567. <&visys_clk_gate LIGHT_CLKGEN_DW200_CLK_VSE>,
  1568. <&visys_clk_gate LIGHT_CLKGEN_DW200_CLK_DWE>;
  1569. clock-names = "aclk", "hclk", "vseclk", "dweclk";
  1570. status = "disabled";
  1571. };
  1572. dec400_isp0: dec400@ffe4060000 {
  1573. compatible = "thead,dec400";
  1574. reg = <0xff 0xe4060000 0x0 0x8000>;
  1575. status = "disabled";
  1576. };
  1577. dec400_isp1: dec400@ffe4068000 {
  1578. compatible = "thead,dec400";
  1579. reg = <0xff 0xe4068000 0x0 0x8000>;
  1580. status = "disabled";
  1581. };
  1582. dec400_isp2: dec400@ffe4070000 {
  1583. compatible = "thead,dec400";
  1584. reg = <0xff 0xe4070000 0x0 0x8000>;
  1585. status = "disabled";
  1586. };
  1587. bm_visys: bm_visys@ffe4040000 {
  1588. compatible = "thead,light-bm-visys";
  1589. reg = <0xff 0xe4040000 0x0 0x1000>;
  1590. status = "disabled";
  1591. };
  1592. bm_csi0: csi@ffe4000000{ //CSI2
  1593. compatible = "thead,light-bm-csi";
  1594. reg = < 0xff 0xe4000000 0x0 0x10000>;
  1595. interrupt-parent = <&intc>;
  1596. interrupts = <128>;
  1597. dphyglueiftester = <0x180>;
  1598. sysreg_mipi_csi_ctrl = <0x140>;
  1599. clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PCLK>,
  1600. <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PIXCLK>,
  1601. <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>,
  1602. <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>,
  1603. <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>;
  1604. clock-names = "pclk", "pixclk", "cfg_clk0", "cfg_clk1", "cfg_clk2";
  1605. phy_name = "CSI_4LANE";
  1606. status = "disabled";
  1607. };
  1608. csia_reg: visys-reg@ffe4020000 {
  1609. compatible = "thead,light-visys-reg", "syscon";
  1610. reg = < 0xff 0xe4020000 0x0 0x10000>;
  1611. status = "okay";
  1612. };
  1613. bm_csi1: csi@ffe4010000{ //CSI2X2_B
  1614. compatible = "thead,light-bm-csi";
  1615. reg = < 0xff 0xe4010000 0x0 0x10000>;
  1616. interrupt-parent = <&intc>;
  1617. interrupts = <126>; // 110 + 16 int_mipi_csi2x2_int0
  1618. dphyglueiftester = <0x182>; // for FPGA PHY only. ASIC not needed.
  1619. sysreg_mipi_csi_ctrl = <0x148>;
  1620. visys-regmap = <&visys_reg>;
  1621. csia-regmap = <&csia_reg>;
  1622. clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PCLK>,
  1623. <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PIXCLK>,
  1624. <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>,
  1625. <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>,
  1626. <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>;
  1627. clock-names = "pclk", "pixclk", "cfg_clk0", "cfg_clk1", "cfg_clk2";
  1628. phy_name = "CSI_B";
  1629. status = "disabled";
  1630. };
  1631. bm_csi2: csi@ffe4020000{ //CSI2X2_A
  1632. compatible = "thead,light-bm-csi";
  1633. reg = < 0xff 0xe4020000 0x0 0x10000>;
  1634. interrupt-parent = <&intc>;
  1635. interrupts = <127>;
  1636. dphyglueiftester = <0x184>;
  1637. sysreg_mipi_csi_ctrl = <0x144>;
  1638. clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PCLK>,
  1639. <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PIXCLK>,
  1640. <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>,
  1641. <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>,
  1642. <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>;
  1643. clock-names = "pclk", "pixclk", "cfg_clk0", "cfg_clk1", "cfg_clk2";
  1644. phy_name = "CSI_A";
  1645. status = "disabled";
  1646. };
  1647. bm_isp0: bm_isp@ffe4100000 {
  1648. compatible = "thead,light-bm-isp";
  1649. reg = <0xff 0xe4100000 0x0 0x10000>;
  1650. status = "disabled";
  1651. };
  1652. bm_isp1: bm_isp@ffe4110000 {
  1653. compatible = "thead,light-bm-isp";
  1654. reg = <0xff 0xe4110000 0x0 0x10000>;
  1655. status = "disabled";
  1656. };
  1657. //isp-ry
  1658. bm_isp2: bm_isp@ffe4120000 {
  1659. compatible = "thead,light-bm-isp";
  1660. reg = <0xff 0xe4120000 0x0 0x10000>;
  1661. status = "disabled";
  1662. };
  1663. vi_pre: vi_pre@ffe4030000 {
  1664. compatible = "thead,vi_pre";
  1665. reg = <0xff 0xe4030000 0x0 0x1000>;
  1666. interrupt-parent = <&intc>;
  1667. interrupts = <134>;
  1668. clocks = <&visys_clk_gate LIGHT_CLKGEN_VIPRE_ACLK>,
  1669. <&visys_clk_gate LIGHT_CLKGEN_VIPRE_PCLK>,
  1670. <&visys_clk_gate LIGHT_CLKGEN_VIPRE_PIXELCLK>;
  1671. clock-names ="aclk", "pclk", "pixclk";
  1672. status = "disabled";
  1673. };
  1674. video0: cam_dev@100 {
  1675. compatible = "thead,video";
  1676. status = "disabled";
  1677. };
  1678. video1: cam_dev@200 {
  1679. compatible = "thead,video";
  1680. status = "disabled";
  1681. };
  1682. video2: cam_dev@300 {
  1683. compatible = "thead,video";
  1684. status = "disabled";
  1685. };
  1686. video3: cam_dev@400 {
  1687. compatible = "thead,video";
  1688. status = "disabled";
  1689. };
  1690. video4: cam_dev@500 {
  1691. compatible = "thead,video";
  1692. status = "disabled";
  1693. };
  1694. video5: cam_dev@600 {
  1695. compatible = "thead,video";
  1696. status = "disabled";
  1697. };
  1698. video6: cam_dev@700 {
  1699. compatible = "thead,video";
  1700. status = "disabled";
  1701. };
  1702. video7: cam_dev@800 {
  1703. compatible = "thead,video";
  1704. status = "disabled";
  1705. };
  1706. video8: cam_dev@900 {
  1707. compatible = "thead,video";
  1708. status = "disabled";
  1709. };
  1710. video9: cam_dev@a00 {
  1711. compatible = "thead,video";
  1712. status = "disabled";
  1713. };
  1714. video10: cam_dev@b00 {
  1715. compatible = "thead,video";
  1716. status = "disabled";
  1717. };
  1718. video11: cam_dev@c00 {
  1719. compatible = "thead,video";
  1720. status = "disabled";
  1721. };
  1722. video12: cam_dev@d00 {
  1723. compatible = "thead,video";
  1724. status = "disabled";
  1725. };
  1726. video13: cam_dev@e00 {
  1727. compatible = "thead,video";
  1728. status = "disabled";
  1729. };
  1730. video14: cam_dev@f00 {
  1731. compatible = "thead,video";
  1732. status = "disabled";
  1733. };
  1734. video15: cam_dev@f01 {
  1735. compatible = "thead,video";
  1736. status = "disabled";
  1737. };
  1738. vvcam_flash_led0: vvcam_flash_led@0 {
  1739. compatible = "thead,light-vvcam-flash_led";
  1740. status = "disabled";
  1741. };
  1742. vvcam_sensor0: vvcam_sensor@0 {
  1743. compatible = "thead,light-vvcam-sensor";
  1744. status = "disabled";
  1745. };
  1746. vvcam_sensor1: vvcam_sensor@1 {
  1747. compatible = "thead,light-vvcam-sensor";
  1748. status = "disabled";
  1749. };
  1750. vvcam_sensor2: vvcam_sensor@2 {
  1751. compatible = "thead,light-vvcam-sensor";
  1752. status = "disabled";
  1753. };
  1754. vvcam_sensor3: vvcam_sensor@3 {
  1755. compatible = "thead,light-vvcam-sensor";
  1756. status = "disabled";
  1757. };
  1758. vvcam_sensor4: vvcam_sensor@4 {
  1759. compatible = "thead,light-vvcam-sensor";
  1760. status = "disabled";
  1761. };
  1762. vvcam_sensor5: vvcam_sensor@5 {
  1763. compatible = "thead,light-vvcam-sensor";
  1764. status = "disabled";
  1765. };
  1766. vvcam_sensor6: vvcam_sensor@6 {
  1767. compatible = "thead,light-vvcam-sensor";
  1768. status = "disabled";
  1769. };
  1770. xtensa_dsp: dsp@01{
  1771. compatible = "thead,dsp-hw-common";
  1772. reg = <0xff 0xef040000 0x0 0x001000 >; /*DSP_SYSREG(0x0000-0xFFF) */
  1773. status = "disabled";
  1774. };
  1775. xtensa_dsp0: dsp@0 {
  1776. compatible = "cdns,xrp-hw-simple";
  1777. reg = <0xff 0xe4040190 0x0 0x000010 /* host irq DSP->CPU INT Register */
  1778. 0xff 0xe40401e0 0x0 0x000010 /* device irq CPU->DSP INT Register */
  1779. 0xff 0xef048000 0x0 0x008000>; /* DSP shared memory */
  1780. dsp = <0>;
  1781. dspsys-rst-bit = <8>; /*bit# in DSP_SYSREG*/
  1782. dspsys-bus-offset = <0x90>; /*in DSP_SYSREG*/
  1783. device-irq = <0x4 1 24>; /*0xff 0xe40401e4 offset to clear DSP I]RQ, bit#, IRQ# */
  1784. device-irq-host-offset = <0x8>; /*0xff 0xe40401e8 offset to trigger DSP IRQ*/
  1785. device-irq-mode = <1>; /*level trigger*/
  1786. host-irq = <0x4 1>; /*0xff 0xe4040194 offset to clear, bit# */
  1787. host-irq-mode = <1>; /*level trigger */
  1788. host-irq-offset = <0x8>; /* 0xff 0xe4040198 offset to trigger ,device side*/
  1789. interrupt-parent = <&intc>;
  1790. interrupts = <156>;
  1791. firmware-name = "xrp0.elf";
  1792. clocks = <&dummy_clock_visys>,
  1793. <&dummy_clock_visys>;
  1794. clock-names = "pclk", "cclk";
  1795. status = "disabled";
  1796. #address-cells = <2>;
  1797. #size-cells = <1>;
  1798. ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000
  1799. 0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000
  1800. 0x00 0xfa000000 0xff 0xe0000000 0x00180000
  1801. 0x00 0xe0180000 0xff 0xe0180000 0x00040000
  1802. 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */
  1803. dsp@0 {
  1804. ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000
  1805. 0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000
  1806. 0x00 0xfa000000 0xff 0xe0000000 0x00180000
  1807. 0x00 0xe0180000 0xff 0xe0180000 0x00040000
  1808. 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */
  1809. };
  1810. };
  1811. xtensa_dsp1: dsp@1 {
  1812. compatible = "cdns,xrp-hw-simple";
  1813. reg = <0xff 0xe40401a0 0x0 0x000010 /* host irq DSP->CPU INT Register */
  1814. 0xff 0xe40401d0 0x0 0x000010 /* device irq CPU->DSP INT Register */
  1815. 0xff 0xef050000 0x0 0x008000>; /* DSP shared memory */
  1816. dsp = <1>;
  1817. dspsys-rst-bit = <8>; /*bit# in DSP_SYSREG*/
  1818. dspsys-bus-offset = <0x90>; /*in DSP_SYSREG*/
  1819. device-irq = <0x4 1 24>; /*0xff 0xe40401e4 offset to clear DSP I]RQ, bit#, IRQ# */
  1820. device-irq-host-offset = <0x8>; /*0xff 0xe40401e8 offset to trigger DSP IRQ*/
  1821. device-irq-mode = <1>; /*level trigger*/
  1822. host-irq = <0x4 1>; /*0xff 0xe4040194 offset to clear, bit# */
  1823. host-irq-mode = <1>; /*level trigger */
  1824. host-irq-offset = <0x8>; /* 0xff 0xe4040198 offset to trigger ,device side*/
  1825. interrupt-parent = <&intc>;
  1826. interrupts = <157>;
  1827. firmware-name = "xrp1.elf";
  1828. clocks = <&dummy_clock_visys>,
  1829. <&dummy_clock_visys>;
  1830. clock-names = "pclk", "cclk";
  1831. status = "disabled";
  1832. #address-cells = <2>;
  1833. #size-cells = <1>;
  1834. ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000
  1835. 0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000
  1836. 0x00 0xfa000000 0xff 0xe0000000 0x00180000
  1837. 0x00 0xe0180000 0xff 0xe01C0000 0x00040000
  1838. 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */
  1839. dsp@0 {
  1840. ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000
  1841. 0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000
  1842. 0x00 0xfa000000 0xff 0xe0000000 0x00180000
  1843. 0x00 0xe0180000 0xff 0xe01C0000 0x00040000
  1844. 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */
  1845. };
  1846. };
  1847. pmp: pmp@ffdc020000 {
  1848. compatible = "pmp";
  1849. reg = <0xff 0xdc020000 0x0 0x1000>;
  1850. };
  1851. mrvbr: mrvbr@ffff018050 {
  1852. compatible = "mrvbr";
  1853. reg = <0xff 0xff019050 0x0 0x1000>;
  1854. };
  1855. mrmr: mrmr@ffff014004 {
  1856. compatible = "mrmr";
  1857. reg = <0xff 0xff015004 0x0 0x1000>;
  1858. };
  1859. bmu: ddr-pmu@ffff008000 {
  1860. compatible = "thead,light-ddr-pmu";
  1861. reg = <0xff 0xff008000 0x0 0x800
  1862. 0xff 0xff008800 0x0 0x800
  1863. 0xff 0xff009000 0x0 0x800
  1864. 0xff 0xff009800 0x0 0x800
  1865. 0xff 0xff00a000 0x0 0x800>;
  1866. interrupt-parent = <&intc>;
  1867. interrupts = <87>;
  1868. status = "okay";
  1869. };
  1870. mbox_910t: mbox@ffffc38000 {
  1871. compatible = "thead,light-mbox";
  1872. reg = <0xff 0xffc38000 0x0 0x4000>,
  1873. <0xff 0xffc44000 0x0 0x1000>,
  1874. <0xff 0xffc4c000 0x0 0x1000>,
  1875. <0xff 0xffc54000 0x0 0x1000>;
  1876. reg-names = "local_base", "remote_icu0", "remote_icu1", "remote_icu2";
  1877. interrupt-parent = <&intc>;
  1878. interrupts = <28>;
  1879. clocks = <&dummy_clock_apb>;
  1880. clock-names = "ipg";
  1881. icu_cpu_id = <0>;
  1882. #mbox-cells = <2>;
  1883. };
  1884. trng: rng@ffff300000 {
  1885. compatible = "inside-secure,safexcel-eip76";
  1886. reg = <0xff 0xff300000 0x0 0x7d>;
  1887. interrupt-parent = <&intc>;
  1888. interrupts = <149>;
  1889. clocks = <&dummy_clock_eip>;
  1890. status = "disabled";
  1891. };
  1892. eip_28: eip-28@ffff300000 {
  1893. compatible = "xlnx,sunrise-fpga-1.0", "safexcel-eip-28";
  1894. reg = <0xff 0xff300000 0x0 0x40000>;
  1895. interrupt-parent = <&intc>;
  1896. interrupts = <144>,<145>,<146>,<147>;
  1897. clocks = <&dummy_clock_eip>;
  1898. status = "disabled";
  1899. };
  1900. khvhost: khvhost {
  1901. compatible = "thead,khv-host";
  1902. interrupt-parent = <&intc>;
  1903. interrupts = <215>; /* TEE INT SRC_7 */
  1904. };
  1905. visys_clk_gate: visys-clk-gate { /* VI_SYSREG_R */
  1906. compatible = "thead,visys-gate-controller";
  1907. visys-regmap = <&visys_reg>;
  1908. #clock-cells = <1>;
  1909. status = "okay";
  1910. };
  1911. vpsys_clk_gate: vpsys-clk-gate@ffecc30000 { /* VP_SYSREG_R */
  1912. compatible = "thead,vpsys-gate-controller";
  1913. reg = <0xff 0xecc30000 0x0 0x1000>;
  1914. #clock-cells = <1>;
  1915. status = "okay";
  1916. };
  1917. vosys_clk_gate: vosys-clk-gate@ffef528000 { /* VO_SYSREG_R */
  1918. compatible = "thead,vosys-gate-controller";
  1919. reg = <0xff 0xef528000 0x0 0x1000>;
  1920. #clock-cells = <1>;
  1921. status = "okay";
  1922. };
  1923. dspsys_clk_gate: dspsys-clk-gate {
  1924. compatible = "thead,dspsys-gate-controller";
  1925. dspsys-regmap = <&dspsys_reg>;
  1926. #clock-cells = <1>;
  1927. status = "okay";
  1928. };
  1929. };
  1930. };