light-crash.dts 15 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2021 Alibaba Group Holding Limited.
  4. */
  5. /dts-v1/;
  6. #include "light.dtsi"
  7. #include <dt-bindings/input/linux-event-codes.h>
  8. #include <dt-bindings/gpio/gpio.h>
  9. #include "light-vi-devices.dtsi"
  10. / {
  11. model = "T-HEAD Light val board";
  12. compatible = "thead,light-val", "thead,light";
  13. chosen {
  14. bootargs = "console=ttyS0,115200 earlycon";
  15. stdout-path = "serial0:115200n8";
  16. };
  17. leds {
  18. compatible = "gpio-leds";
  19. status = "disabled";
  20. led0 {
  21. label = "SYS_STATUS";
  22. gpios = <&gpio1_porta 15 0>; /* GPIO_ACTIVE_HIGH: 0 */
  23. default-state = "off";
  24. };
  25. };
  26. display-subsystem {
  27. status = "okay";
  28. };
  29. lcd0_backlight: pwm-backlight@0 {
  30. status = "disabled";
  31. compatible = "pwm-backlight";
  32. pwms = <&pwm 0 5000000>;
  33. brightness-levels = <0 4 8 16 32 64 128 255>;
  34. default-brightness-level = <7>;
  35. };
  36. light_iopmp: iopmp {
  37. status = "disabled";
  38. compatible = "thead,light-iopmp";
  39. /* config#1: multiple valid regions */
  40. iopmp_emmc: IOPMP_EMMC {
  41. regions = <0x000000 0x100000>,
  42. <0x100000 0x200000>;
  43. attr = <0xFFFFFFFF>;
  44. dummy_slave= <0x800000>;
  45. };
  46. /* config#2: iopmp bypass */
  47. iopmp_sdio0: IOPMP_SDIO0 {
  48. bypass_en;
  49. };
  50. /* config#3: iopmp default region set */
  51. iopmp_sdio1: IOPMP_SDIO1 {
  52. attr = <0xFFFFFFFF>;
  53. is_default_region;
  54. };
  55. iopmp_usb0: IOPMP_USB0 {
  56. attr = <0xFFFFFFFF>;
  57. is_default_region;
  58. };
  59. iopmp_ao: IOPMP_AO {
  60. is_default_region;
  61. };
  62. iopmp_aud: IOPMP_AUD {
  63. is_default_region;
  64. };
  65. iopmp_chip_dbg: IOPMP_CHIP_DBG {
  66. is_default_region;
  67. };
  68. iopmp_eip120i: IOPMP_EIP120I {
  69. is_default_region;
  70. };
  71. iopmp_eip120ii: IOPMP_EIP120II {
  72. is_default_region;
  73. };
  74. iopmp_eip120iii: IOPMP_EIP120III {
  75. is_default_region;
  76. };
  77. iopmp_isp0: IOPMP_ISP0 {
  78. is_default_region;
  79. };
  80. iopmp_isp1: IOPMP_ISP1 {
  81. is_default_region;
  82. };
  83. iopmp_dw200: IOPMP_DW200 {
  84. is_default_region;
  85. };
  86. iopmp_vipre: IOPMP_VIPRE {
  87. is_default_region;
  88. };
  89. iopmp_venc: IOPMP_VENC {
  90. is_default_region;
  91. };
  92. iopmp_vdec: IOPMP_VDEC {
  93. is_default_region;
  94. };
  95. iopmp_g2d: IOPMP_G2D {
  96. is_default_region;
  97. };
  98. iopmp_fce: IOPMP_FCE {
  99. is_default_region;
  100. };
  101. iopmp_npu: IOPMP_NPU {
  102. is_default_region;
  103. };
  104. iopmp0_dpu: IOPMP0_DPU {
  105. bypass_en;
  106. };
  107. iopmp1_dpu: IOPMP1_DPU {
  108. bypass_en;
  109. };
  110. iopmp_gpu: IOPMP_GPU {
  111. is_default_region;
  112. };
  113. iopmp_gmac1: IOPMP_GMAC1 {
  114. is_default_region;
  115. };
  116. iopmp_gmac2: IOPMP_GMAC2 {
  117. is_default_region;
  118. };
  119. iopmp_dmac: IOPMP_DMAC {
  120. is_default_region;
  121. };
  122. iopmp_tee_dmac: IOPMP_TEE_DMAC {
  123. is_default_region;
  124. };
  125. iopmp_dsp0: IOPMP_DSP0 {
  126. is_default_region;
  127. };
  128. iopmp_dsp1: IOPMP_DSP1 {
  129. is_default_region;
  130. };
  131. };
  132. mbox_910t_client1: mbox_910t_client1 {
  133. compatible = "thead,light-mbox-client";
  134. mbox-names = "902";
  135. mboxes = <&mbox_910t 1 0>;
  136. status = "disabled";
  137. };
  138. mbox_910t_client2: mbox_910t_client2 {
  139. compatible = "thead,light-mbox-client";
  140. mbox-names = "906";
  141. mboxes = <&mbox_910t 2 0>;
  142. status = "disabled";
  143. };
  144. lightsound: lightsound@1 {
  145. compatible = "simple-audio-card";
  146. simple-audio-card,name = "Light-Sound-Card";
  147. #address-cells = <1>;
  148. #size-cells = <0>;
  149. status = "disabled";
  150. };
  151. dummy_codec: dummy_codec {
  152. #sound-dai-cells = <1>;
  153. compatible = "linux,bt-sco";
  154. status = "okay";
  155. };
  156. reg_vref_1v8: regulator-adc-verf {
  157. compatible = "regulator-fixed";
  158. regulator-name = "vref-1v8";
  159. regulator-min-microvolt = <1800000>;
  160. regulator-max-microvolt = <1800000>;
  161. status = "okay";
  162. };
  163. reg_tp_pwr_en: regulator-pwr-en {
  164. compatible = "regulator-fixed";
  165. regulator-name = "PWR_EN";
  166. regulator-min-microvolt = <2800000>;
  167. regulator-max-microvolt = <2800000>;
  168. gpio = <&gpio1_porta 12 1>;
  169. enable-active-high;
  170. regulator-always-on;
  171. };
  172. wcn_wifi: wireless-wlan {
  173. compatible = "wlan-platdata";
  174. clock-names = "clk_wifi";
  175. ref-clock-frequency = <24000000>;
  176. keep_wifi_power_on;
  177. pinctrl-names = "default";
  178. wifi_chip_type = "rtl8723ds";
  179. WIFI,poweren_gpio = <&gpio2_porta 29 0>;
  180. WIFI,reset_n = <&gpio2_porta 24 0>;
  181. status = "okay";
  182. };
  183. wcn_bt: wireless-bluetooth {
  184. compatible = "bluetooth-platdata";
  185. pinctrl-names = "default", "rts_gpio";
  186. BT,power_gpio = <&gpio2_porta 25 0>;
  187. status = "okay";
  188. };
  189. gpio-keys {
  190. compatible = "gpio-keys";
  191. pinctrl-0 = <&pinctrl_volume>;
  192. pinctrl-names = "default";
  193. key-volumedown {
  194. label = "Volume Down Key";
  195. linux,code = <KEY_VOLUMEDOWN>;
  196. debounce-interval = <1>;
  197. gpios = <&ao_gpio_porta 11 0x1>;
  198. };
  199. key-volumeup {
  200. label = "Volume Up Key";
  201. linux,code = <KEY_VOLUMEUP>;
  202. debounce-interval = <1>;
  203. gpios = <&ao_gpio_porta 10 0x1>;
  204. };
  205. };
  206. aon: light-aon {
  207. compatible = "thead,light-aon";
  208. mbox-names = "aon";
  209. mboxes = <&mbox_910t 1 0>;
  210. status = "okay";
  211. pd: light-aon-pd {
  212. compatible = "thead,light-aon-pd";
  213. #power-domain-cells = <1>;
  214. };
  215. c910_cpufreq {
  216. compatible = "thead,light-mpw-cpufreq";
  217. status = "okay";
  218. };
  219. test: light-aon-test {
  220. compatible = "thead,light-aon-test";
  221. };
  222. };
  223. };
  224. &resmem {
  225. #address-cells = <2>;
  226. #size-cells = <2>;
  227. ranges;
  228. tee_mem: memory@1a000000 {
  229. reg = <0x0 0x1a000000 0 0x4000000>;
  230. no-map;
  231. };
  232. dsp0_mem: memory@20000000 { /**0x2000_0000~0x2040_0000 4M**/
  233. reg = <0x0 0x20000000 0x0 0x00280000 /* DSP FW code&data section 2.5M*/
  234. 0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/
  235. 0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */
  236. 0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/
  237. no-map;
  238. };
  239. dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/
  240. reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */
  241. 0x0 0x20680000 0x0 0x00001000 /* DSP communication area */
  242. 0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/
  243. 0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */
  244. no-map;
  245. };
  246. vi_mem: framebuffer@10000000 {
  247. reg = <0x0 0x10000000 0x0 0x02C00000 /* vi_mem_pool_region[0] 44 MB (default) */
  248. 0x0 0x12C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */
  249. 0x0 0x14900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */
  250. no-map;
  251. };
  252. facelib_mem: memory@17000000 {
  253. reg = <0x0 0x17000000 0 0x02000000>;
  254. no-map;
  255. };
  256. };
  257. &adc {
  258. vref-supply = <&reg_vref_1v8>;
  259. status = "okay";
  260. };
  261. &i2c0 {
  262. clock-frequency = <100000>;
  263. status = "okay";
  264. touch@5d {
  265. #gpio-cells = <2>;
  266. compatible = "goodix,gt911";
  267. reg = <0x5d>;
  268. interrupt-parent = <&gpio1_porta>;
  269. interrupts = <8 0>;
  270. irq-gpios = <&gpio1_porta 8 0>;
  271. reset-gpios = <&gpio1_porta 7 0>;
  272. AVDD28-supply = <&reg_tp_pwr_en>;
  273. touchscreen-size-x = <720>;
  274. touchscreen-size-y = <1280>;
  275. };
  276. };
  277. &audio_i2c0 {
  278. clock-frequency = <100000>;
  279. status = "okay";
  280. es8156_audio_codec: es8156@8 {
  281. #sound-dai-cells = <0>;
  282. compatible = "everest,es8156";
  283. reg = <0x08>;
  284. };
  285. es7210_audio_codec: es7210@40 {
  286. #sound-dai-cells = <0>;
  287. compatible = "MicArray_0";
  288. reg = <0x40>;
  289. };
  290. audio_aw87519_pa@58 {
  291. compatible = "awinic,aw87519_pa";
  292. reg = <0x58>;
  293. reset-gpio = <&ao_gpio4_porta 9 0x1>;
  294. status = "okay";
  295. };
  296. };
  297. &i2c1 {
  298. clock-frequency = <100000>;
  299. status = "okay";
  300. };
  301. &spi0 {
  302. num-cs = <1>;
  303. cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0
  304. rx-sample-delay-ns = <10>;
  305. status = "disabled";
  306. spi_norflash@0 {
  307. #address-cells = <1>;
  308. #size-cells = <1>;
  309. compatible = "winbond,w25q64jwm", "jedec,spi-nor";
  310. reg = <0>;
  311. spi-max-frequency = <50000000>;
  312. w25q,fast-read;
  313. };
  314. spidev@1 {
  315. compatible = "spidev";
  316. #address-cells = <0x1>;
  317. #size-cells = <0x1>;
  318. reg = <0x1>;
  319. spi-max-frequency = <50000000>;
  320. };
  321. };
  322. &uart0 {
  323. clocks = <&dummy_clock_uart_sclk>;
  324. clock-names = "baudclk";
  325. clock-frequency = <100000000>;
  326. };
  327. &qspi0 {
  328. num-cs = <1>;
  329. cs-gpios = <&gpio2_porta 3 0>;
  330. rx-sample-dly = <4>;
  331. status = "disabled";
  332. spi-flash@0 {
  333. #address-cells = <1>;
  334. #size-cells = <1>;
  335. compatible = "spi-nand";
  336. spi-max-frequency = <100000000>;
  337. spi-tx-bus-width = <4>;
  338. spi-rx-bus-width = <4>;
  339. reg = <0>;
  340. partition@0 {
  341. label = "ubi1";
  342. reg = <0x00000000 0x08000000>;
  343. };
  344. };
  345. };
  346. &qspi1 {
  347. compatible = "snps,dw-apb-ssi";
  348. num-cs = <1>;
  349. cs-gpios = <&gpio0_porta 1 0>;
  350. status = "disabled";
  351. spidev@0 {
  352. compatible = "spidev";
  353. #address-cells = <0x1>;
  354. #size-cells = <0x1>;
  355. reg = <0x0>;
  356. spi-max-frequency = <50000000>;
  357. };
  358. };
  359. &gmac0 {
  360. phy-mode = "rgmii-id";
  361. rx-clk-delay = <0x00>; /* for RGMII */
  362. tx-clk-delay = <0x00>; /* for RGMII */
  363. phy-handle = <&phy_88E1111_0>;
  364. status = "okay";
  365. mdio0 {
  366. #address-cells = <1>;
  367. #size-cells = <0>;
  368. compatible = "snps,dwmac-mdio";
  369. phy_88E1111_0: ethernet-phy@0 {
  370. reg = <0x1>;
  371. };
  372. phy_88E1111_1: ethernet-phy@1 {
  373. reg = <0x2>;
  374. };
  375. };
  376. };
  377. &gmac1 {
  378. phy-mode = "rgmii-id";
  379. rx-clk-delay = <0x00>; /* for RGMII */
  380. tx-clk-delay = <0x00>; /* for RGMII */
  381. phy-handle = <&phy_88E1111_1>;
  382. status = "disabled";
  383. };
  384. &emmc {
  385. max-frequency = <198000000>;
  386. non-removable;
  387. mmc-hs400-1_8v;
  388. io_fixed_1v8;
  389. is_emmc;
  390. no-sdio;
  391. no-sd;
  392. pull_up;
  393. bus-width = <8>;
  394. status = "okay";
  395. };
  396. &sdhci0 {
  397. max-frequency = <198000000>;
  398. bus-width = <4>;
  399. pull_up;
  400. wprtn_ignore;
  401. status = "okay";
  402. };
  403. &sdhci1 {
  404. max-frequency = <100000000>;
  405. bus-width = <4>;
  406. pull_up;
  407. no-sd;
  408. no-mmc;
  409. non-removable;
  410. io_fixed_1v8;
  411. post-power-on-delay-ms = <50>;
  412. wprtn_ignore;
  413. cap-sd-highspeed;
  414. keep-power-in-suspend;
  415. wakeup-source;
  416. status = "okay";
  417. };
  418. &padctrl0_apsys { /* right-pinctrl */
  419. light-evb-padctrl0 {
  420. /*
  421. * Pin Configuration Node:
  422. * Format: <pin_id mux_node config>
  423. */
  424. pinctrl_uart0: uart0grp {
  425. thead,pins = <
  426. FM_UART0_TXD 0x0 0x72
  427. FM_UART0_RXD 0x0 0x72
  428. >;
  429. };
  430. pinctrl_spi0: spi0grp {
  431. thead,pins = <
  432. FM_SPI_CSN 0x3 0x20a
  433. FM_SPI_SCLK 0x0 0x20a
  434. FM_SPI_MISO 0x0 0x23a
  435. FM_SPI_MOSI 0x0 0x23a
  436. >;
  437. };
  438. pinctrl_qspi0: qspi0grp {
  439. thead,pins = <
  440. FM_QSPI0_SCLK 0x0 0x20f
  441. FM_QSPI0_CSN0 0x3 0x20f
  442. FM_QSPI0_CSN1 0x0 0x20f
  443. FM_QSPI0_D0_MOSI 0x0 0x23f
  444. FM_QSPI0_D1_MISO 0x0 0x23f
  445. FM_QSPI0_D2_WP 0x0 0x23f
  446. FM_QSPI0_D3_HOLD 0x0 0x23f
  447. >;
  448. };
  449. pinctrl_audio_i2s0: i2s0grp {
  450. thead,pins = <
  451. FM_QSPI0_SCLK 0x2 0x208
  452. FM_QSPI0_CSN0 0x2 0x238
  453. FM_QSPI0_CSN1 0x2 0x208
  454. FM_QSPI0_D0_MOSI 0x2 0x238
  455. FM_QSPI0_D1_MISO 0x2 0x238
  456. FM_QSPI0_D2_WP 0x2 0x238
  457. FM_QSPI0_D3_HOLD 0x2 0x238
  458. >;
  459. };
  460. pinctrl_pwm: pwmgrp {
  461. thead,pins = <
  462. FM_GPIO3_2 0x1 0x208 /* pwm0 */
  463. >;
  464. };
  465. };
  466. };
  467. &padctrl1_apsys { /* left-pinctrl */
  468. light-evb-padctrl1 {
  469. /*
  470. * Pin Configuration Node:
  471. * Format: <pin_id mux_node config>
  472. */
  473. pinctrl_uart3: uart3grp {
  474. thead,pins = <
  475. FM_UART3_TXD 0x0 0x72
  476. FM_UART3_RXD 0x0 0x72
  477. >;
  478. };
  479. pinctrl_uart4: uart4grp {
  480. thead,pins = <
  481. FM_UART4_TXD 0x0 0x72
  482. FM_UART4_RXD 0x0 0x72
  483. FM_UART4_CTSN 0x0 0x72
  484. FM_UART4_RTSN 0x0 0x72
  485. >;
  486. };
  487. pinctrl_qspi1: qspi1grp {
  488. thead,pins = <
  489. FM_QSPI1_SCLK 0x0 0x20a
  490. FM_QSPI1_CSN0 0x3 0x20a
  491. FM_QSPI1_D0_MOSI 0x0 0x23a
  492. FM_QSPI1_D1_MISO 0x0 0x23a
  493. FM_QSPI1_D2_WP 0x0 0x23a
  494. FM_QSPI1_D3_HOLD 0x0 0x23a
  495. >;
  496. };
  497. pinctrl_iso7816: iso7816grp {
  498. thead,pins = <
  499. FM_QSPI1_SCLK 0x1 0x208
  500. FM_QSPI1_D0_MOSI 0x1 0x238
  501. FM_QSPI1_D1_MISO 0x1 0x238
  502. FM_QSPI1_D2_WP 0x1 0x238
  503. FM_QSPI1_D3_HOLD 0x1 0x238
  504. >;
  505. };
  506. };
  507. };
  508. &padctrl_aosys {
  509. light-aon-padctrl {
  510. /*
  511. * Pin Configuration Node:
  512. * Format: <pin_id mux_node config>
  513. */
  514. pinctrl_audiopa1: audiopa1_grp {
  515. thead,pins = <
  516. FM_AUDIO_PA1 0x3 0x72
  517. >;
  518. };
  519. pinctrl_audiopa2: audiopa2_grp {
  520. thead,pins = <
  521. FM_AUDIO_PA2 0x0 0x72
  522. >;
  523. };
  524. pinctrl_volume: volume_grp {
  525. thead,pins = <
  526. FM_AOGPIO_11 0x0 0x208
  527. FM_AOGPIO_10 0x3 0x208
  528. >;
  529. };
  530. };
  531. };
  532. &i2c0 {
  533. clock-frequency = <400000>;
  534. status = "okay";
  535. };
  536. &i2c1 {
  537. clock-frequency = <400000>;
  538. status = "okay";
  539. };
  540. &i2c2 {
  541. clock-frequency = <400000>;
  542. status = "okay";
  543. };
  544. &i2c3 {
  545. clock-frequency = <400000>;
  546. status = "okay";
  547. };
  548. &i2c4 {
  549. clock-frequency = <400000>;
  550. status = "okay";
  551. };
  552. &isp0 {
  553. status = "disabled";
  554. };
  555. &isp1 {
  556. status = "disabled";
  557. };
  558. &isp_ry0 {
  559. status = "disabled";
  560. };
  561. &dewarp {
  562. status = "disabled";
  563. };
  564. &dec400_isp0 {
  565. status = "disabled";
  566. };
  567. &dec400_isp1 {
  568. status = "disabled";
  569. };
  570. &dec400_isp2 {
  571. status = "disabled";
  572. };
  573. &bm_visys {
  574. status = "disabled";
  575. };
  576. &bm_csi0 {
  577. status = "disabled";
  578. };
  579. &bm_csi1 {
  580. status = "disabled";
  581. };
  582. &bm_csi2 {
  583. status = "disabled";
  584. };
  585. &vi_pre {
  586. status = "disabled";
  587. };
  588. &xtensa_dsp {
  589. status = "disabled";
  590. };
  591. &xtensa_dsp0 {
  592. status = "disabled";
  593. };
  594. &xtensa_dsp1 {
  595. status = "disabled";
  596. };
  597. &vvcam_flash_led0{
  598. status = "disabled";
  599. };
  600. &vvcam_sensor0 {
  601. status = "disabled";
  602. };
  603. &vvcam_sensor1 {
  604. status = "disabled";
  605. };
  606. &vvcam_sensor2 {
  607. status = "disabled";
  608. };
  609. &vvcam_sensor3 {
  610. status = "disabled";
  611. };
  612. &vvcam_sensor4 {
  613. status = "disabled";
  614. };
  615. &vvcam_sensor5 {
  616. status = "disabled";
  617. };
  618. &video0{
  619. status = "disabled";
  620. };
  621. &video1{
  622. status = "disabled";
  623. };
  624. &video2{
  625. status = "disabled";
  626. };
  627. &video3{
  628. status = "disabled";
  629. };
  630. &video4{
  631. status = "disabled";
  632. };
  633. &video5{
  634. status = "disabled";
  635. };
  636. &video6{
  637. status = "disabled";
  638. };
  639. &video7{
  640. status = "disabled";
  641. };
  642. &video8{
  643. status = "disabled";
  644. };
  645. &video9{
  646. status = "disabled";
  647. };
  648. &video10{
  649. status = "disabled";
  650. };
  651. &video11{
  652. status = "disabled";
  653. };
  654. &video12{
  655. status = "disabled";
  656. };
  657. &trng {
  658. status = "disabled";
  659. };
  660. &eip_28 {
  661. status = "disabled";
  662. };
  663. &vdec {
  664. status = "disabled";
  665. };
  666. &venc {
  667. status = "disabled";
  668. };
  669. &isp_venc_shake {
  670. status = "disabled";
  671. };
  672. &vidmem {
  673. status = "disabled";
  674. };
  675. &gpu {
  676. status = "disabled";
  677. };
  678. &npu {
  679. status = "disabled";
  680. };
  681. &fce {
  682. status = "disabled";
  683. };
  684. &dpu_enc0 {
  685. status = "disabled";
  686. };
  687. &dpu_enc1 {
  688. status = "disabled";
  689. };
  690. &dpu {
  691. status = "disabled";
  692. };
  693. &dsi0 {
  694. status = "disabled";
  695. };
  696. &dhost_0 {
  697. status = "disabled";
  698. };
  699. &disp1_out {
  700. status = "disabled";
  701. };
  702. &hdmi_tx {
  703. status = "disabled";
  704. };
  705. &lightsound {
  706. status = "disabled";
  707. };
  708. &light_i2s {
  709. status = "okay";
  710. };
  711. &i2s0 {
  712. status = "okay";
  713. };
  714. &i2s1 {
  715. status = "okay";
  716. };
  717. &i2s3 {
  718. status = "okay";
  719. };
  720. &khvhost {
  721. status = "disabled";
  722. };