light-ant-ref.dts 47 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2021 Alibaba Group Holding Limited.
  4. */
  5. /dts-v1/;
  6. #include "light.dtsi"
  7. #include <dt-bindings/input/linux-event-codes.h>
  8. #include <dt-bindings/gpio/gpio.h>
  9. #include "light-vi-devices.dtsi"
  10. / {
  11. model = "T-HEAD Light val board";
  12. compatible = "thead,light-val", "thead,light";
  13. memory@0 {
  14. device_type = "memory";
  15. reg = <0x0 0x00000000 0x0 0x80000000>;
  16. };
  17. chosen {
  18. bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000";
  19. stdout-path = "serial0:115200n8";
  20. };
  21. leds {
  22. compatible = "gpio-leds";
  23. status = "disabled";
  24. led0 {
  25. label = "SYS_STATUS";
  26. gpios = <&gpio1_porta 15 0>; /* GPIO_ACTIVE_HIGH: 0 */
  27. default-state = "off";
  28. };
  29. };
  30. display-subsystem {
  31. status = "okay";
  32. };
  33. lcd0_backlight: pwm-backlight@0 {
  34. compatible = "pwm-backlight";
  35. pwms = <&pwm 0 5000000>;
  36. brightness-levels = <0 4 8 16 32 64 128 255>;
  37. default-brightness-level = <7>;
  38. };
  39. light_iopmp: iopmp {
  40. compatible = "thead,light-iopmp";
  41. /* config#1: multiple valid regions */
  42. iopmp_emmc: IOPMP_EMMC {
  43. regions = <0x000000 0x100000>,
  44. <0x100000 0x200000>;
  45. attr = <0xFFFFFFFF>;
  46. dummy_slave= <0x800000>;
  47. };
  48. /* config#2: iopmp bypass */
  49. iopmp_sdio0: IOPMP_SDIO0 {
  50. bypass_en;
  51. };
  52. /* config#3: iopmp default region set */
  53. iopmp_sdio1: IOPMP_SDIO1 {
  54. attr = <0xFFFFFFFF>;
  55. is_default_region;
  56. };
  57. iopmp_usb0: IOPMP_USB0 {
  58. attr = <0xFFFFFFFF>;
  59. is_default_region;
  60. };
  61. iopmp_ao: IOPMP_AO {
  62. is_default_region;
  63. };
  64. iopmp_aud: IOPMP_AUD {
  65. is_default_region;
  66. };
  67. iopmp_chip_dbg: IOPMP_CHIP_DBG {
  68. is_default_region;
  69. };
  70. iopmp_eip120i: IOPMP_EIP120I {
  71. is_default_region;
  72. };
  73. iopmp_eip120ii: IOPMP_EIP120II {
  74. is_default_region;
  75. };
  76. iopmp_eip120iii: IOPMP_EIP120III {
  77. is_default_region;
  78. };
  79. iopmp_isp0: IOPMP_ISP0 {
  80. is_default_region;
  81. };
  82. iopmp_isp1: IOPMP_ISP1 {
  83. is_default_region;
  84. };
  85. iopmp_dw200: IOPMP_DW200 {
  86. is_default_region;
  87. };
  88. iopmp_vipre: IOPMP_VIPRE {
  89. is_default_region;
  90. };
  91. iopmp_venc: IOPMP_VENC {
  92. is_default_region;
  93. };
  94. iopmp_vdec: IOPMP_VDEC {
  95. is_default_region;
  96. };
  97. iopmp_g2d: IOPMP_G2D {
  98. is_default_region;
  99. };
  100. iopmp_fce: IOPMP_FCE {
  101. is_default_region;
  102. };
  103. iopmp_npu: IOPMP_NPU {
  104. is_default_region;
  105. };
  106. iopmp0_dpu: IOPMP0_DPU {
  107. bypass_en;
  108. };
  109. iopmp1_dpu: IOPMP1_DPU {
  110. bypass_en;
  111. };
  112. iopmp_gpu: IOPMP_GPU {
  113. is_default_region;
  114. };
  115. iopmp_gmac1: IOPMP_GMAC1 {
  116. is_default_region;
  117. };
  118. iopmp_gmac2: IOPMP_GMAC2 {
  119. is_default_region;
  120. };
  121. iopmp_dmac: IOPMP_DMAC {
  122. is_default_region;
  123. };
  124. iopmp_tee_dmac: IOPMP_TEE_DMAC {
  125. is_default_region;
  126. };
  127. iopmp_dsp0: IOPMP_DSP0 {
  128. is_default_region;
  129. };
  130. iopmp_dsp1: IOPMP_DSP1 {
  131. is_default_region;
  132. };
  133. };
  134. mbox_910t_client1: mbox_910t_client1 {
  135. compatible = "thead,light-mbox-client";
  136. mbox-names = "902";
  137. mboxes = <&mbox_910t 1 0>;
  138. status = "disabled";
  139. };
  140. mbox_910t_client2: mbox_910t_client2 {
  141. compatible = "thead,light-mbox-client";
  142. mbox-names = "906";
  143. mboxes = <&mbox_910t 2 0>;
  144. status = "disabled";
  145. };
  146. lightsound: lightsound@1 {
  147. compatible = "simple-audio-card";
  148. simple-audio-card,name = "Light-Sound-Card";
  149. #address-cells = <1>;
  150. #size-cells = <0>;
  151. status = "disabled";
  152. };
  153. dummy_codec: dummy_codec {
  154. #sound-dai-cells = <1>;
  155. compatible = "linux,bt-sco";
  156. status = "okay";
  157. };
  158. reg_vref_1v8: regulator-adc-verf {
  159. compatible = "regulator-fixed";
  160. regulator-name = "vref-1v8";
  161. regulator-min-microvolt = <1800000>;
  162. regulator-max-microvolt = <1800000>;
  163. status = "okay";
  164. };
  165. reg_tp_pwr_en: regulator-pwr-en {
  166. compatible = "regulator-fixed";
  167. regulator-name = "PWR_EN";
  168. regulator-min-microvolt = <2800000>;
  169. regulator-max-microvolt = <2800000>;
  170. gpio = <&gpio1_porta 12 1>;
  171. enable-active-high;
  172. regulator-always-on;
  173. };
  174. wcn_wifi: wireless-wlan {
  175. compatible = "wlan-platdata";
  176. clock-names = "clk_wifi";
  177. ref-clock-frequency = <24000000>;
  178. keep_wifi_power_on;
  179. pinctrl-names = "default";
  180. wifi_chip_type = "rtl8723ds";
  181. WIFI,poweren_gpio = <&gpio2_porta 29 0>;
  182. WIFI,reset_n = <&gpio2_porta 22 0>;
  183. status = "okay";
  184. };
  185. wcn_bt: wireless-bluetooth {
  186. compatible = "bluetooth-platdata";
  187. pinctrl-names = "default", "rts_gpio";
  188. BT,power_gpio = <&gpio2_porta 29 0>;
  189. status = "okay";
  190. };
  191. gpio-keys {
  192. compatible = "gpio-keys";
  193. pinctrl-0 = <&pinctrl_volume>;
  194. pinctrl-names = "default";
  195. key-volumedown {
  196. label = "Volume Down Key";
  197. linux,code = <KEY_VOLUMEDOWN>;
  198. debounce-interval = <1>;
  199. gpios = <&gpio1_porta 19 0x1>;
  200. };
  201. key-volumeup {
  202. label = "Volume Up Key";
  203. linux,code = <KEY_VOLUMEUP>;
  204. debounce-interval = <1>;
  205. gpios = <&gpio2_porta 25 0x1>;
  206. };
  207. };
  208. aon: aon {
  209. compatible = "thead,light-aon";
  210. mbox-names = "aon";
  211. mboxes = <&mbox_910t 1 0>;
  212. status = "okay";
  213. pd: light-aon-pd {
  214. compatible = "thead,light-aon-pd";
  215. #power-domain-cells = <1>;
  216. };
  217. soc_aud_3v3_en_reg: soc_aud_3v3_en {
  218. compatible = "regulator-fixed";
  219. regulator-name = "soc_aud_3v3_en";
  220. regulator-min-microvolt = <3300000>;
  221. regulator-max-microvolt = <3300000>;
  222. gpio = <&ao_gpio_porta 7 1>;
  223. enable-active-high;
  224. regulator-always-on;
  225. };
  226. soc_aud_1v8_en_reg: soc_aud_1v8_en {
  227. compatible = "regulator-fixed";
  228. regulator-name = "soc_aud_1v8_en";
  229. regulator-min-microvolt = <1800000>;
  230. regulator-max-microvolt = <1800000>;
  231. gpio = <&ao_gpio_porta 8 1>;
  232. enable-active-high;
  233. regulator-always-on;
  234. };
  235. soc_vdd_3v3_en_reg: soc_vdd_3v3_en {
  236. compatible = "regulator-fixed";
  237. regulator-name = "soc_vdd_3v3_en";
  238. regulator-min-microvolt = <3300000>;
  239. regulator-max-microvolt = <3300000>;
  240. gpio = <&gpio0_porta 30 1>;
  241. enable-active-high;
  242. regulator-always-on;
  243. };
  244. soc_lcd0_bias_en_reg: soc_lcd0_bias_en {
  245. compatible = "regulator-fixed";
  246. regulator-name = "soc_lcd0_bias_en";
  247. regulator-min-microvolt = <5700000>;
  248. regulator-max-microvolt = <5700000>;
  249. gpio = <&gpio1_porta 10 1>;
  250. enable-active-high;
  251. };
  252. soc_vdd18_lcd0_en_reg: soc_lcd0_en {
  253. compatible = "regulator-fixed";
  254. regulator-name = "soc_lcd0_en";
  255. regulator-min-microvolt = <1800000>;
  256. regulator-max-microvolt = <1800000>;
  257. gpio = <&gpio1_porta 9 1>;
  258. enable-active-high;
  259. };
  260. soc_vdd5v_se_en_reg: soc_vdd5v_se_en {
  261. compatible = "regulator-fixed";
  262. regulator-name = "soc_vdd5v_se_en";
  263. regulator-min-microvolt = <5000000>;
  264. regulator-max-microvolt = <5000000>;
  265. gpio = <&gpio2_porta 14 1>;
  266. enable-active-high;
  267. regulator-always-on;
  268. };
  269. soc_wcn33_en_reg: soc_wcn33_en {
  270. compatible = "regulator-fixed";
  271. regulator-name = "soc_wcn33_en";
  272. regulator-min-microvolt = <3300000>;
  273. regulator-max-microvolt = <3300000>;
  274. gpio = <&gpio2_porta 29 1>;
  275. enable-active-high;
  276. regulator-always-on;
  277. };
  278. soc_vbus_en_reg: soc_vbus_en {
  279. compatible = "regulator-fixed";
  280. regulator-name = "soc_vbus_en";
  281. regulator-min-microvolt = <3300000>;
  282. regulator-max-microvolt = <3300000>;
  283. gpio = <&gpio2_porta 28 1>;
  284. enable-active-high;
  285. regulator-always-on;
  286. };
  287. soc_avdd28_rgb_reg: soc_avdd28_rgb {
  288. compatible = "regulator-fixed";
  289. regulator-name = "soc_avdd28_rgb";
  290. regulator-min-microvolt = <2800000>;
  291. regulator-max-microvolt = <2800000>;
  292. gpio = <&gpio1_porta 15 1>;
  293. enable-active-high;
  294. };
  295. soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
  296. compatible = "regulator-fixed";
  297. regulator-name = "soc_dovdd18_rgb";
  298. regulator-min-microvolt = <2800000>;
  299. regulator-max-microvolt = <2800000>;
  300. gpio = <&gpio1_porta 13 1>;
  301. enable-active-high;
  302. };
  303. soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
  304. compatible = "regulator-fixed";
  305. regulator-name = "soc_dvdd12_rgb";
  306. regulator-min-microvolt = <2800000>;
  307. regulator-max-microvolt = <2800000>;
  308. gpio = <&gpio1_porta 14 1>;
  309. enable-active-high;
  310. };
  311. soc_avdd25_ir_reg: soc_avdd25_ir {
  312. compatible = "regulator-fixed";
  313. regulator-name = "soc_avdd25_ir";
  314. regulator-min-microvolt = <2500000>;
  315. regulator-max-microvolt = <2500000>;
  316. gpio = <&gpio0_porta 28 1>;
  317. enable-active-high;
  318. };
  319. soc_dovdd18_ir_reg: soc_dovdd18_ir {
  320. compatible = "regulator-fixed";
  321. regulator-name = "soc_dovdd18_ir";
  322. regulator-min-microvolt = <1800000>;
  323. regulator-max-microvolt = <1800000>;
  324. gpio = <&gpio1_porta 13 1>;
  325. enable-active-high;
  326. };
  327. soc_dvdd12_ir_reg: soc_dvdd12_ir {
  328. compatible = "regulator-fixed";
  329. regulator-name = "soc_dvdd12_ir";
  330. regulator-min-microvolt = <1200000>;
  331. regulator-max-microvolt = <1200000>;
  332. gpio = <&gpio0_porta 29 1>;
  333. enable-active-high;
  334. };
  335. aon_reg_dialog: light-dialog-reg {
  336. compatible = "thead,light-dialog-pmic-ant";
  337. status = "okay";
  338. dvdd_cpu_reg: appcpu_dvdd {
  339. regulator-name = "appcpu_dvdd";
  340. regulator-min-microvolt = <300000>;
  341. regulator-max-microvolt = <1570000>;
  342. regulator-boot-on;
  343. regulator-always-on;
  344. };
  345. dvddm_cpu_reg: appcpu_dvddm {
  346. regulator-name = "appcpu_dvddm";
  347. regulator-min-microvolt = <300000>;
  348. regulator-max-microvolt = <1570000>;
  349. regulator-boot-on;
  350. regulator-always-on;
  351. };
  352. soc_dvdd18_aon_reg: soc_dvdd18_aon {
  353. regulator-name = "soc_dvdd18_aon";
  354. regulator-boot-on;
  355. regulator-always-on;
  356. };
  357. soc_avdd33_usb3_reg: soc_avdd33_usb3 {
  358. regulator-name = "soc_avdd33_usb3";
  359. regulator-boot-on;
  360. regulator-always-on;
  361. };
  362. soc_dvdd08_aon_reg: soc_dvdd08_aon {
  363. regulator-name = "soc_dvdd08_aon";
  364. regulator-boot-on;
  365. regulator-always-on;
  366. };
  367. soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
  368. regulator-name = "soc_dvdd08_ddr";
  369. regulator-boot-on;
  370. regulator-always-on;
  371. };
  372. soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
  373. regulator-name = "soc_vdd_ddr_1v8";
  374. regulator-boot-on;
  375. regulator-always-on;
  376. };
  377. soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
  378. regulator-name = "soc_vdd_ddr_1v1";
  379. regulator-boot-on;
  380. regulator-always-on;
  381. };
  382. soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
  383. regulator-name = "soc_vdd_ddr_0v6";
  384. regulator-boot-on;
  385. regulator-always-on;
  386. };
  387. soc_dvdd18_ap_reg: soc_dvdd18_ap {
  388. regulator-name = "soc_dvdd18_ap";
  389. regulator-boot-on;
  390. regulator-always-on;
  391. };
  392. soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
  393. regulator-name = "soc_avdd08_mipi_hdmi";
  394. regulator-boot-on;
  395. regulator-always-on;
  396. };
  397. soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
  398. regulator-name = "soc_avdd18_mipi_hdmi";
  399. regulator-boot-on;
  400. regulator-always-on;
  401. };
  402. soc_vdd33_emmc_reg: soc_vdd33_emmc {
  403. regulator-name = "soc_vdd33_emmc";
  404. regulator-boot-on;
  405. regulator-always-on;
  406. };
  407. soc_vdd18_emmc_reg: soc_vdd18_emmc {
  408. regulator-name = "soc_vdd18_emmc";
  409. regulator-boot-on;
  410. regulator-always-on;
  411. };
  412. soc_dovdd18_scan_reg: soc_dovdd18_scan {
  413. regulator-name = "soc_dovdd18_scan";
  414. regulator-min-microvolt = <900000>;
  415. regulator-max-microvolt = <3600000>;
  416. };
  417. soc_dvdd12_scan_reg: soc_dvdd12_scan {
  418. regulator-name = "soc_dvdd12_scan";
  419. regulator-min-microvolt = <900000>;
  420. regulator-max-microvolt = <3600000>;
  421. };
  422. soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
  423. regulator-name = "soc_avdd28_scan_en";
  424. regulator-min-microvolt = <900000>;
  425. regulator-max-microvolt = <3600000>;
  426. };
  427. };
  428. c910_cpufreq {
  429. compatible = "thead,light-mpw-cpufreq";
  430. status = "okay";
  431. };
  432. test: light-aon-test {
  433. compatible = "thead,light-aon-test";
  434. };
  435. };
  436. };
  437. &resmem {
  438. #address-cells = <2>;
  439. #size-cells = <2>;
  440. ranges;
  441. tee_mem: memory@1c000000 {
  442. reg = <0x0 0x1c000000 0 0x2000000>;
  443. no-map;
  444. };
  445. dsp0_mem: memory@20000000 { /**0x2000_0000~0x2040_0000 4M**/
  446. reg = <0x0 0x20000000 0x0 0x00280000 /* DSP FW code&data section 2.5M*/
  447. 0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/
  448. 0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */
  449. 0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/
  450. no-map;
  451. };
  452. dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/
  453. reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */
  454. 0x0 0x20680000 0x0 0x00001000 /* DSP communication area */
  455. 0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/
  456. 0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */
  457. no-map;
  458. };
  459. vi_mem: framebuffer@10000000 {
  460. reg = <0x0 0x10000000 0x0 0x02C00000 /* vi_mem_pool_region[0] 44 MB (default) */
  461. 0x0 0x12C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */
  462. 0x0 0x14900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */
  463. no-map;
  464. };
  465. facelib_mem: memory@17000000 {
  466. reg = <0x0 0x17000000 0 0x02000000>;
  467. no-map;
  468. };
  469. };
  470. &adc {
  471. vref-supply = <&reg_vref_1v8>;
  472. #io-channel-cells = <1>;
  473. status = "okay";
  474. };
  475. &i2c0 {
  476. clock-frequency = <100000>;
  477. status = "okay";
  478. touch@5d {
  479. #gpio-cells = <2>;
  480. compatible = "goodix,gt911";
  481. reg = <0x5d>;
  482. interrupt-parent = <&gpio1_porta>;
  483. interrupts = <8 0>;
  484. irq-gpios = <&gpio1_porta 8 0>;
  485. reset-gpios = <&gpio1_porta 7 0>;
  486. AVDD28-supply = <&reg_tp_pwr_en>;
  487. touchscreen-size-x = <720>;
  488. touchscreen-size-y = <1280>;
  489. };
  490. };
  491. &audio_i2c0 {
  492. clock-frequency = <100000>;
  493. status = "okay";
  494. es8156_audio_codec: es8156@8 {
  495. #sound-dai-cells = <0>;
  496. compatible = "everest,es8156";
  497. reg = <0x08>;
  498. };
  499. es7210_audio_codec: es7210@40 {
  500. #sound-dai-cells = <0>;
  501. compatible = "MicArray_0";
  502. reg = <0x40>;
  503. };
  504. audio_aw87519_pa@58 {
  505. compatible = "awinic,aw87519_pa";
  506. reg = <0x58>;
  507. reset-gpio = <&ao_gpio4_porta 9 0x1>;
  508. status = "okay";
  509. };
  510. };
  511. &i2c1 {
  512. clock-frequency = <100000>;
  513. status = "okay";
  514. };
  515. &spi0 {
  516. num-cs = <1>;
  517. cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0
  518. rx-sample-delay-ns = <10>;
  519. status = "disabled";
  520. spi_norflash@0 {
  521. #address-cells = <1>;
  522. #size-cells = <1>;
  523. compatible = "winbond,w25q64jwm", "jedec,spi-nor";
  524. reg = <0>;
  525. spi-max-frequency = <50000000>;
  526. w25q,fast-read;
  527. };
  528. spidev@1 {
  529. compatible = "spidev";
  530. #address-cells = <0x1>;
  531. #size-cells = <0x1>;
  532. reg = <0x1>;
  533. spi-max-frequency = <50000000>;
  534. };
  535. };
  536. &uart0 {
  537. clock-frequency = <100000000>;
  538. };
  539. &qspi0 {
  540. num-cs = <1>;
  541. cs-gpios = <&gpio2_porta 3 0>;
  542. rx-sample-dly = <4>;
  543. status = "disabled";
  544. spi-flash@0 {
  545. #address-cells = <1>;
  546. #size-cells = <1>;
  547. compatible = "spi-nand";
  548. spi-max-frequency = <100000000>;
  549. spi-tx-bus-width = <4>;
  550. spi-rx-bus-width = <4>;
  551. reg = <0>;
  552. partition@0 {
  553. label = "ubi1";
  554. reg = <0x00000000 0x08000000>;
  555. };
  556. };
  557. };
  558. &qspi1 {
  559. compatible = "snps,dw-apb-ssi";
  560. num-cs = <1>;
  561. cs-gpios = <&gpio0_porta 1 0>;
  562. status = "okay";
  563. spidev@0 {
  564. compatible = "spidev";
  565. #address-cells = <0x1>;
  566. #size-cells = <0x1>;
  567. reg = <0x0>;
  568. spi-max-frequency = <50000000>;
  569. };
  570. };
  571. &gmac0 {
  572. phy-mode = "rgmii-id";
  573. rx-clk-delay = <0x00>; /* for RGMII */
  574. tx-clk-delay = <0x00>; /* for RGMII */
  575. phy-handle = <&phy_88E1111_0>;
  576. status = "okay";
  577. mdio0 {
  578. #address-cells = <1>;
  579. #size-cells = <0>;
  580. compatible = "snps,dwmac-mdio";
  581. phy_88E1111_0: ethernet-phy@0 {
  582. reg = <0x1>;
  583. };
  584. phy_88E1111_1: ethernet-phy@1 {
  585. reg = <0x2>;
  586. };
  587. };
  588. };
  589. &gmac1 {
  590. phy-mode = "rgmii-id";
  591. rx-clk-delay = <0x00>; /* for RGMII */
  592. tx-clk-delay = <0x00>; /* for RGMII */
  593. phy-handle = <&phy_88E1111_1>;
  594. status = "disabled";
  595. };
  596. &emmc {
  597. max-frequency = <198000000>;
  598. non-removable;
  599. mmc-hs400-1_8v;
  600. io_fixed_1v8;
  601. is_emmc;
  602. no-sdio;
  603. no-sd;
  604. pull_up;
  605. bus-width = <8>;
  606. status = "okay";
  607. };
  608. &sdhci0 {
  609. max-frequency = <198000000>;
  610. bus-width = <4>;
  611. pull_up;
  612. wprtn_ignore;
  613. status = "okay";
  614. };
  615. &sdhci1 {
  616. max-frequency = <100000000>;
  617. bus-width = <4>;
  618. pull_up;
  619. no-sd;
  620. no-mmc;
  621. non-removable;
  622. io_fixed_1v8;
  623. post-power-on-delay-ms = <50>;
  624. wprtn_ignore;
  625. cap-sd-highspeed;
  626. keep-power-in-suspend;
  627. wakeup-source;
  628. status = "okay";
  629. };
  630. &padctrl0_apsys { /* right-pinctrl */
  631. light-evb-padctrl0 {
  632. /*
  633. * Pin Configuration Node:
  634. * Format: <pin_id mux_node config>
  635. */
  636. pinctrl_uart0: uart0grp {
  637. thead,pins = <
  638. FM_UART0_TXD 0x0 0x72
  639. FM_UART0_RXD 0x0 0x72
  640. >;
  641. };
  642. pinctrl_spi0: spi0grp {
  643. thead,pins = <
  644. FM_SPI_CSN 0x3 0x20a
  645. FM_SPI_SCLK 0x0 0x20a
  646. FM_SPI_MISO 0x0 0x23a
  647. FM_SPI_MOSI 0x0 0x23a
  648. >;
  649. };
  650. pinctrl_qspi0: qspi0grp {
  651. thead,pins = <
  652. FM_QSPI0_SCLK 0x0 0x20f
  653. FM_QSPI0_CSN0 0x3 0x20f
  654. FM_QSPI0_CSN1 0x0 0x20f
  655. FM_QSPI0_D0_MOSI 0x0 0x23f
  656. FM_QSPI0_D1_MISO 0x0 0x23f
  657. FM_QSPI0_D2_WP 0x0 0x23f
  658. FM_QSPI0_D3_HOLD 0x0 0x23f
  659. >;
  660. };
  661. pinctrl_audio_i2s0: i2s0grp {
  662. thead,pins = <
  663. FM_QSPI0_SCLK 0x2 0x208
  664. FM_QSPI0_CSN0 0x2 0x238
  665. FM_QSPI0_CSN1 0x2 0x208
  666. FM_QSPI0_D0_MOSI 0x2 0x238
  667. FM_QSPI0_D1_MISO 0x2 0x238
  668. FM_QSPI0_D2_WP 0x2 0x238
  669. FM_QSPI0_D3_HOLD 0x2 0x238
  670. >;
  671. };
  672. pinctrl_pwm: pwmgrp {
  673. thead,pins = <
  674. FM_GPIO3_2 0x1 0x208 /* pwm0 */
  675. >;
  676. };
  677. };
  678. };
  679. &padctrl1_apsys { /* left-pinctrl */
  680. light-evb-padctrl1 {
  681. /*
  682. * Pin Configuration Node:
  683. * Format: <pin_id mux_node config>
  684. */
  685. pinctrl_uart3: uart3grp {
  686. thead,pins = <
  687. FM_UART3_TXD 0x0 0x72
  688. FM_UART3_RXD 0x0 0x72
  689. >;
  690. };
  691. pinctrl_uart4: uart4grp {
  692. thead,pins = <
  693. FM_UART4_TXD 0x0 0x72
  694. FM_UART4_RXD 0x0 0x72
  695. FM_UART4_CTSN 0x0 0x72
  696. FM_UART4_RTSN 0x0 0x72
  697. >;
  698. };
  699. pinctrl_qspi1: qspi1grp {
  700. thead,pins = <
  701. FM_QSPI1_SCLK 0x0 0x20a
  702. FM_QSPI1_CSN0 0x3 0x20a
  703. FM_QSPI1_D0_MOSI 0x0 0x23a
  704. FM_QSPI1_D1_MISO 0x0 0x23a
  705. >;
  706. };
  707. pinctrl_iso7816: iso7816grp {
  708. thead,pins = <
  709. FM_QSPI1_SCLK 0x1 0x208
  710. FM_QSPI1_D0_MOSI 0x1 0x238
  711. FM_QSPI1_D1_MISO 0x1 0x238
  712. FM_QSPI1_D2_WP 0x1 0x238
  713. FM_QSPI1_D3_HOLD 0x1 0x238
  714. >;
  715. };
  716. pinctrl_volume: volume_grp {
  717. thead,pins = <
  718. FM_CLK_OUT_2 0x3 0x208
  719. >;
  720. };
  721. };
  722. };
  723. &padctrl_aosys {
  724. light-aon-padctrl {
  725. /*
  726. * Pin Configuration Node:
  727. * Format: <pin_id mux_node config>
  728. */
  729. pinctrl_audiopa1: audiopa1_grp {
  730. thead,pins = <
  731. FM_AUDIO_PA1 0x3 0x72
  732. >;
  733. };
  734. pinctrl_audiopa2: audiopa2_grp {
  735. thead,pins = <
  736. FM_AUDIO_PA2 0x0 0x72
  737. >;
  738. };
  739. };
  740. };
  741. &i2c0 {
  742. clock-frequency = <400000>;
  743. status = "okay";
  744. };
  745. &i2c1 {
  746. clock-frequency = <400000>;
  747. status = "okay";
  748. };
  749. &i2c2 {
  750. clock-frequency = <400000>;
  751. status = "okay";
  752. };
  753. &i2c3 {
  754. clock-frequency = <400000>;
  755. status = "okay";
  756. };
  757. &i2c4 {
  758. clock-frequency = <400000>;
  759. status = "okay";
  760. };
  761. &isp0 {
  762. status = "okay";
  763. };
  764. &isp1 {
  765. status = "okay";
  766. };
  767. &isp_ry0 {
  768. status = "okay";
  769. };
  770. &dewarp {
  771. status = "okay";
  772. };
  773. &dec400_isp0 {
  774. status = "okay";
  775. };
  776. &dec400_isp1 {
  777. status = "okay";
  778. };
  779. &dec400_isp2 {
  780. status = "okay";
  781. };
  782. &bm_visys {
  783. status = "okay";
  784. };
  785. &bm_csi0 {
  786. status = "okay";
  787. };
  788. &bm_csi1 {
  789. status = "okay";
  790. };
  791. &bm_csi2 {
  792. status = "okay";
  793. };
  794. &vi_pre {
  795. //vi_pre_irq_en = <1>;
  796. status = "okay";
  797. };
  798. &xtensa_dsp {
  799. status = "okay";
  800. };
  801. &xtensa_dsp0 {
  802. status = "okay";
  803. memory-region = <&dsp0_mem>;
  804. };
  805. &xtensa_dsp1 {
  806. status = "okay";
  807. memory-region = <&dsp1_mem>;
  808. };
  809. &vvcam_flash_led0{
  810. flash_led_name = "aw36413_aw36515";
  811. floodlight_i2c_bus = /bits/ 8 <2>;
  812. floodlight_en_pin = <&gpio1_porta 26 0>;
  813. projection_i2c_bus = /bits/ 8 <1>;
  814. flash_led_touch_pin = <&gpio1_porta 27 0>; //flash led touch pin
  815. io-channels = <&adc 2>;
  816. io-channel-names = "projection_adc";
  817. status = "okay";
  818. };
  819. &vvcam_sensor0 {
  820. sensor_name = "SC2310";
  821. sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB";
  822. sensor_regulator_timing_us = <70 50 20>;
  823. sensor_pdn = <&gpio1_porta 21 0>; //powerdown pin / shutdown pin
  824. sensor_rst = <&gpio1_porta 16 0>;
  825. sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready
  826. DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
  827. DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
  828. AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>;
  829. i2c_reg_width = /bits/ 8 <2>;
  830. i2c_data_width = /bits/ 8 <1>;
  831. i2c_addr = /bits/ 8 <0x30>;
  832. i2c_bus = /bits/ 8 <3>;
  833. status = "okay";
  834. };
  835. &vvcam_sensor1 {
  836. sensor_name = "SC132GS";
  837. sensor_regulators = "DOVDD18_IR", "DVDD12_IR", "AVDD25_IR";
  838. sensor_regulator_timing_us = <70 1000 2000>;
  839. i2c_addr = /bits/ 8 <0x31>;
  840. sensor_pdn = <&gpio1_porta 28 0>; //powerdown pin / shutdown pin
  841. sensor_rst = <&gpio1_porta 24 0>;
  842. sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready
  843. DOVDD18_IR-supply = <&soc_dovdd18_ir_reg>;
  844. DVDD12_IR-supply = <&soc_dvdd12_ir_reg>;
  845. AVDD25_IR-supply = <&soc_avdd25_ir_reg>;
  846. i2c_reg_width = /bits/ 8 <2>;
  847. i2c_data_width = /bits/ 8 <1>;
  848. i2c_bus = /bits/ 8 <2>;
  849. status = "okay";
  850. };
  851. &vvcam_sensor2 {
  852. sensor_name = "GC5035";
  853. sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN";
  854. sensor_regulator_timing_us = <100 50 0>;
  855. sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin
  856. sensor_rst = <&gpio1_porta 29 0>;
  857. sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready
  858. DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>;
  859. DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>;
  860. AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>;
  861. i2c_addr = /bits/ 8 <0x37>;
  862. i2c_bus = /bits/ 8 <4>;
  863. i2c_reg_width = /bits/ 8 <1>;
  864. i2c_data_width = /bits/ 8 <1>;
  865. status = "okay";
  866. };
  867. &vvcam_sensor3 {
  868. sensor_name = "GC02M1B";
  869. sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN";
  870. sensor_regulator_timing_us = <100 50 0>;
  871. sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin
  872. sensor_rst = <&gpio1_porta 29 0>;
  873. sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready
  874. DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>;
  875. DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>;
  876. AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>;
  877. i2c_addr = /bits/ 8 <0x37>;
  878. i2c_bus = /bits/ 8 <4>;
  879. i2c_reg_width = /bits/ 8 <1>;
  880. i2c_data_width = /bits/ 8 <1>;
  881. status = "okay";
  882. };
  883. &video0{
  884. vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2]
  885. pipline0 {
  886. sensor0 {
  887. subdev_name = "vivcam";
  888. idx = <2>; //<2>=vivcam2 : gc5035
  889. csi_idx = <0>; //<0>=CSI2
  890. mode_idx = <3>;
  891. path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
  892. };
  893. sensor1 {
  894. subdev_name = "vivcam";
  895. idx = <3>; //<3>=vivcam3 : gc02m1b
  896. csi_idx = <0>; //<0>=CSI2
  897. mode_idx = <0>;
  898. path_type = "SENSOR_1600x1200_RAW10_LINER";
  899. };
  900. dma {
  901. path_type = "VIPRE_CSI0_ISP0";
  902. };
  903. isp {
  904. subdev_name = "isp";
  905. idx = <0>;
  906. path_type = "ISP_MI_PATH_MP";
  907. output {
  908. max_width = <1920>;
  909. max_height = <1088>;
  910. bit_per_pixel = <12>;
  911. frame_count = <3>;
  912. };
  913. };
  914. };
  915. pipline1 {
  916. sensor0 {
  917. subdev_name = "vivcam";
  918. idx = <2>; //<2>=vivcam2 : gc5035
  919. csi_idx = <0>; //<0>=CSI2
  920. mode_idx = <3>;
  921. path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
  922. };
  923. sensor1 {
  924. subdev_name = "vivcam";
  925. idx = <3>; //<3>=vivcam3 : gc02m1b
  926. csi_idx = <0>; //<0>=CSI2
  927. mode_idx = <0>;
  928. path_type = "SENSOR_1600x1200_RAW10_LINER";
  929. };
  930. dma {
  931. path_type = "VIPRE_CSI0_ISP0";
  932. };
  933. isp {
  934. subdev_name = "isp";
  935. idx = <0>;
  936. path_type = "ISP_MI_PATH_SP";
  937. output {
  938. max_width = <1920>;
  939. max_height = <1088>;
  940. bit_per_pixel = <12>;
  941. frame_count = <3>;
  942. };
  943. };
  944. };
  945. pipline2 {
  946. sensor0 {
  947. subdev_name = "vivcam";
  948. idx = <2>; //<2>=vivcam2 : gc5035
  949. csi_idx = <0>; //<0>=CSI2
  950. mode_idx = <3>;
  951. path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
  952. };
  953. sensor1 {
  954. subdev_name = "vivcam";
  955. idx = <3>; //<3>=vivcam3 : gc02m1b
  956. csi_idx = <0>; //<0>=CSI2
  957. mode_idx = <0>;
  958. path_type = "SENSOR_1600x1200_RAW10_LINER";
  959. };
  960. dma {
  961. path_type = "VIPRE_CSI0_ISP0";
  962. };
  963. isp {
  964. subdev_name = "isp";
  965. idx = <0>;
  966. path_type = "ISP_MI_PATH_SP2_BP";
  967. output {
  968. max_width = <1920>;
  969. max_height = <1088>;
  970. bit_per_pixel = <12>;
  971. frame_count = <3>;
  972. };
  973. };
  974. };
  975. };
  976. &video1{
  977. vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2]
  978. pipline0 {
  979. sensor0 {
  980. subdev_name = "vivcam";
  981. idx = <2>; //<2>=vivcam2 : gc5035
  982. csi_idx = <0>; //<0>=CSI2
  983. mode_idx = <3>;
  984. path_type = "SENSOR_1296x972_RAW10_LINER";
  985. };
  986. sensor1 {
  987. subdev_name = "vivcam";
  988. idx = <3>; //<3>=vivcam3 : gc02m1b
  989. csi_idx = <0>; //<0>=CSI2
  990. mode_idx = <0>;
  991. path_type = "SENSOR_1600x1200_RAW10_LINER";
  992. };
  993. dma {
  994. path_type = "VIPRE_CSI0_ISP0";
  995. };
  996. isp {
  997. subdev_name = "isp";
  998. idx = <0>;
  999. path_type = "ISP_MI_PATH_MP";
  1000. output {
  1001. max_width = <1920>;
  1002. max_height = <1088>;
  1003. bit_per_pixel = <12>;
  1004. frame_count = <3>;
  1005. };
  1006. };
  1007. dw {
  1008. subdev_name = "dw";
  1009. idx = <0>;
  1010. path_type = "DW_DWE_VSE0";
  1011. dw_dst_depth = <2>;
  1012. };
  1013. };
  1014. pipline1 {
  1015. sensor0 {
  1016. subdev_name = "vivcam";
  1017. idx = <2>; //<2>=vivcam2 : gc5035
  1018. csi_idx = <0>; //<0>=CSI2
  1019. mode_idx = <3>;
  1020. path_type = "SENSOR_1296x972_RAW10_LINER";
  1021. };
  1022. sensor1 {
  1023. subdev_name = "vivcam";
  1024. idx = <3>; //<3>=vivcam3 : gc02m1b
  1025. csi_idx = <0>; //<0>=CSI2
  1026. mode_idx = <0>;
  1027. path_type = "SENSOR_1600x1200_RAW10_LINER";
  1028. };
  1029. dma {
  1030. path_type = "VIPRE_CSI0_ISP0";
  1031. };
  1032. isp {
  1033. subdev_name = "isp";
  1034. idx = <0>;
  1035. path_type = "ISP_MI_PATH_MP";
  1036. output {
  1037. max_width = <1920>;
  1038. max_height = <1088>;
  1039. bit_per_pixel = <12>;
  1040. frame_count = <3>;
  1041. };
  1042. };
  1043. dw {
  1044. subdev_name = "dw";
  1045. idx = <0>;
  1046. path_type = "DW_DWE_VSE1";
  1047. dw_dst_depth = <2>;
  1048. };
  1049. };
  1050. pipline2 {
  1051. sensor0 {
  1052. subdev_name = "vivcam";
  1053. idx = <2>; //<2>=vivcam2 : gc5035
  1054. csi_idx = <0>; //<0>=CSI2
  1055. mode_idx = <3>;
  1056. path_type = "SENSOR_1296x972_RAW10_LINER";
  1057. };
  1058. sensor1 {
  1059. subdev_name = "vivcam";
  1060. idx = <3>; //<3>=vivcam3 : gc02m1b
  1061. csi_idx = <0>; //<0>=CSI2
  1062. mode_idx = <0>;
  1063. path_type = "SENSOR_1600x1200_RAW10_LINER";
  1064. };
  1065. dma {
  1066. path_type = "VIPRE_CSI0_ISP0";
  1067. };
  1068. isp {
  1069. subdev_name = "isp";
  1070. idx = <0>;
  1071. path_type = "ISP_MI_PATH_MP";
  1072. output {
  1073. max_width = <1920>;
  1074. max_height = <1088>;
  1075. bit_per_pixel = <12>;
  1076. frame_count = <3>;
  1077. };
  1078. };
  1079. dw {
  1080. subdev_name = "dw";
  1081. idx = <0>;
  1082. path_type = "DW_DWE_VSE2";
  1083. dw_dst_depth = <2>;
  1084. };
  1085. };
  1086. };
  1087. &video2{
  1088. vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
  1089. pipline0 {
  1090. sensor0 {
  1091. subdev_name = "vivcam";
  1092. idx = <0>; //vivcam0 sc2310
  1093. csi_idx = <1>; //<1>=CSI2_B
  1094. mode_idx = <1>;
  1095. path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
  1096. };
  1097. dma {
  1098. path_type = "VIPRE_CSI1_ISP1";
  1099. };
  1100. isp {
  1101. subdev_name = "isp";
  1102. idx = <1>;
  1103. path_type = "ISP_MI_PATH_MP";
  1104. output {
  1105. max_width = <1920>;
  1106. max_height = <1088>;
  1107. bit_per_pixel = <12>;
  1108. frame_count = <3>;
  1109. };
  1110. };
  1111. };
  1112. pipline1 {
  1113. sensor0 {
  1114. subdev_name = "vivcam";
  1115. idx = <0>; //vivcam0 sc2310
  1116. csi_idx = <1>; //<1>=CSI2_B
  1117. mode_idx = <1>;
  1118. path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
  1119. };
  1120. dma {
  1121. path_type = "VIPRE_CSI1_ISP1";
  1122. };
  1123. isp {
  1124. subdev_name = "isp";
  1125. idx = <1>;
  1126. path_type = "ISP_MI_PATH_SP";
  1127. output {
  1128. max_width = <1920>;
  1129. max_height = <1088>;
  1130. bit_per_pixel = <12>;
  1131. frame_count = <3>;
  1132. };
  1133. };
  1134. };
  1135. pipline2 {
  1136. sensor0 {
  1137. subdev_name = "vivcam";
  1138. idx = <0>; //vivcam0 sc2310
  1139. csi_idx = <1>; //<1>=CSI2_B
  1140. mode_idx = <1>;
  1141. path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
  1142. };
  1143. dma {
  1144. path_type = "VIPRE_CSI1_ISP1";
  1145. };
  1146. isp {
  1147. subdev_name = "isp";
  1148. idx = <1>;
  1149. path_type = "ISP_MI_PATH_SP2_BP";
  1150. output {
  1151. max_width = <1920>;
  1152. max_height = <1088>;
  1153. bit_per_pixel = <12>;
  1154. frame_count = <3>;
  1155. };
  1156. };
  1157. };
  1158. };
  1159. &video3{
  1160. vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
  1161. pipline0 {
  1162. sensor0 {
  1163. subdev_name = "vivcam";
  1164. idx = <0>; //vivcam0 sc2310
  1165. csi_idx = <1>; //<1>=CSI2B
  1166. mode_idx = <1>;
  1167. path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
  1168. };
  1169. dma {
  1170. path_type = "VIPRE_CSI1_ISP1";
  1171. };
  1172. isp {
  1173. subdev_name = "isp";
  1174. idx = <1>;
  1175. path_type = "ISP_MI_PATH_MP";
  1176. output {
  1177. max_width = <1920>;
  1178. max_height = <1088>;
  1179. bit_per_pixel = <12>;
  1180. frame_count = <3>;
  1181. };
  1182. };
  1183. dw {
  1184. subdev_name = "dw";
  1185. idx = <0>;
  1186. path_type = "DW_DWE_VSE0";
  1187. dw_dst_depth = <2>;
  1188. };
  1189. };
  1190. pipline1 {
  1191. sensor0 {
  1192. subdev_name = "vivcam";
  1193. idx = <0>; //vivcam0 sc2310
  1194. csi_idx = <1>; //<1>=CSI2B
  1195. mode_idx = <1>;
  1196. path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
  1197. };
  1198. dma {
  1199. path_type = "VIPRE_CSI1_ISP1";
  1200. };
  1201. isp {
  1202. subdev_name = "isp";
  1203. idx = <1>;
  1204. path_type = "ISP_MI_PATH_MP";
  1205. output {
  1206. max_width = <1920>;
  1207. max_height = <1088>;
  1208. bit_per_pixel = <12>;
  1209. frame_count = <3>;
  1210. };
  1211. };
  1212. dw {
  1213. subdev_name = "dw";
  1214. idx = <0>;
  1215. path_type = "DW_DWE_VSE1";
  1216. dw_dst_depth = <2>;
  1217. };
  1218. };
  1219. pipline2 {
  1220. sensor0 {
  1221. subdev_name = "vivcam";
  1222. idx = <0>; //vivcam0 sc2310
  1223. csi_idx = <1>; //<1>=CSI2_B
  1224. mode_idx = <1>;
  1225. path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
  1226. };
  1227. dma {
  1228. path_type = "VIPRE_CSI1_ISP1";
  1229. };
  1230. isp {
  1231. subdev_name = "isp";
  1232. idx = <1>;
  1233. path_type = "ISP_MI_PATH_MP";
  1234. output {
  1235. max_width = <1920>;
  1236. max_height = <1088>;
  1237. bit_per_pixel = <12>;
  1238. frame_count = <3>;
  1239. };
  1240. };
  1241. dw {
  1242. subdev_name = "dw";
  1243. idx = <0>;
  1244. path_type = "DW_DWE_VSE2";
  1245. dw_dst_depth = <2>;
  1246. };
  1247. };
  1248. };
  1249. &video4{
  1250. vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
  1251. pipline0 {
  1252. sensor0 {
  1253. subdev_name = "vivcam";
  1254. idx = <0>; //vivcam0 sc2310
  1255. csi_idx = <1>; //<1>=CSI2_B
  1256. mode_idx = <1>;
  1257. path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
  1258. };
  1259. dma {
  1260. path_type = "VIPRE_CSI1_ISP1";
  1261. };
  1262. isp {
  1263. subdev_name = "isp";
  1264. idx = <1>;
  1265. path_type = "ISP_MI_PATH_PP";
  1266. output {
  1267. max_width = <1920>;
  1268. max_height = <1088>;
  1269. bit_per_pixel = <12>;
  1270. frame_count = <3>;
  1271. };
  1272. };
  1273. dsp {
  1274. subdev_name = "dsp";
  1275. idx = <0>;
  1276. path_type = "DSP_PATH_ISP_RY";
  1277. output {
  1278. max_width = <1920>;
  1279. max_height = <1088>;
  1280. bit_per_pixel = <12>;
  1281. frame_count = <3>;
  1282. };
  1283. };
  1284. ry {
  1285. subdev_name = "ry";
  1286. idx = <0>;
  1287. path_type = "ISP_RY_MI_PATH_MP";
  1288. output {
  1289. max_width = <1920>;
  1290. max_height = <1088>;
  1291. bit_per_pixel = <12>;
  1292. frame_count = <3>;
  1293. };
  1294. };
  1295. };
  1296. pipline1 {
  1297. sensor0 {
  1298. subdev_name = "vivcam";
  1299. idx = <0>; //vivcam0 sc2310
  1300. csi_idx = <1>; //<1>=CSI2_B
  1301. mode_idx = <1>;
  1302. path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
  1303. };
  1304. dma {
  1305. path_type = "VIPRE_CSI1_ISP1";
  1306. };
  1307. isp {
  1308. subdev_name = "isp";
  1309. idx = <1>;
  1310. path_type = "ISP_MI_PATH_PP";
  1311. output {
  1312. max_width = <1920>;
  1313. max_height = <1088>;
  1314. bit_per_pixel = <12>;
  1315. frame_count = <3>;
  1316. };
  1317. };
  1318. dsp {
  1319. subdev_name = "dsp";
  1320. idx = <0>;
  1321. path_type = "DSP_PATH_ISP_RY";
  1322. output {
  1323. max_width = <1920>;
  1324. max_height = <1088>;
  1325. bit_per_pixel = <12>;
  1326. frame_count = <3>;
  1327. };
  1328. };
  1329. ry {
  1330. subdev_name = "ry";
  1331. idx = <0>;
  1332. path_type = "ISP_RY_MI_PATH_SP";
  1333. output {
  1334. max_width = <1920>;
  1335. max_height = <1088>;
  1336. bit_per_pixel = <12>;
  1337. frame_count = <3>;
  1338. };
  1339. };
  1340. };
  1341. pipline2 {
  1342. sensor0 {
  1343. subdev_name = "vivcam";
  1344. idx = <0>; //vivcam0 sc2310
  1345. csi_idx = <1>; //<1>=CSI2_B
  1346. mode_idx = <1>;
  1347. path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
  1348. };
  1349. dma {
  1350. path_type = "VIPRE_CSI1_ISP1";
  1351. };
  1352. isp {
  1353. subdev_name = "isp";
  1354. idx = <1>;
  1355. path_type = "ISP_MI_PATH_PP";
  1356. output {
  1357. max_width = <1920>;
  1358. max_height = <1088>;
  1359. bit_per_pixel = <12>;
  1360. frame_count = <3>;
  1361. };
  1362. };
  1363. dsp {
  1364. subdev_name = "dsp";
  1365. idx = <0>;
  1366. path_type = "DSP_PATH_ISP_RY";
  1367. output {
  1368. max_width = <1920>;
  1369. max_height = <1088>;
  1370. bit_per_pixel = <12>;
  1371. frame_count = <3>;
  1372. };
  1373. };
  1374. ry {
  1375. subdev_name = "ry";
  1376. idx = <0>;
  1377. path_type = "ISP_RY_MI_PATH_SP2_BP";
  1378. output {
  1379. max_width = <1920>;
  1380. max_height = <1088>;
  1381. bit_per_pixel = <12>;
  1382. frame_count = <3>;
  1383. };
  1384. };
  1385. };
  1386. };
  1387. &video5{
  1388. vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
  1389. pipline0 {
  1390. sensor0 {
  1391. subdev_name = "vivcam";
  1392. idx = <0>; //vivcam0 sc2310
  1393. csi_idx = <1>; //<1>=CSI2_B
  1394. mode_idx = <1>;
  1395. path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
  1396. };
  1397. dma {
  1398. path_type = "VIPRE_CSI1_ISP1";
  1399. };
  1400. isp {
  1401. subdev_name = "isp";
  1402. idx = <1>;
  1403. path_type = "ISP_MI_PATH_PP";
  1404. output {
  1405. max_width = <1920>;
  1406. max_height = <1088>;
  1407. bit_per_pixel = <12>;
  1408. frame_count = <3>;
  1409. };
  1410. };
  1411. dsp {
  1412. subdev_name = "dsp";
  1413. idx = <0>;
  1414. path_type = "DSP_PATH_ISP_RY";
  1415. output {
  1416. max_width = <1920>;
  1417. max_height = <1088>;
  1418. bit_per_pixel = <12>;
  1419. frame_count = <3>;
  1420. };
  1421. };
  1422. ry {
  1423. subdev_name = "ry";
  1424. idx = <0>;
  1425. path_type = "ISP_RY_MI_PATH_MP";
  1426. output {
  1427. max_width = <1920>;
  1428. max_height = <1088>;
  1429. bit_per_pixel = <12>;
  1430. frame_count = <3>;
  1431. };
  1432. };
  1433. dw {
  1434. subdev_name = "dw";
  1435. idx = <0>;
  1436. path_type = "DW_DWE_VSE0";
  1437. dw_dst_depth = <2>;
  1438. };
  1439. };
  1440. pipline1 {
  1441. sensor0 {
  1442. subdev_name = "vivcam";
  1443. idx = <0>; //vivcam0 sc2310
  1444. csi_idx = <1>; //<1>=CSI2_B
  1445. mode_idx = <1>;
  1446. path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
  1447. };
  1448. dma {
  1449. path_type = "VIPRE_CSI1_ISP1";
  1450. };
  1451. isp {
  1452. subdev_name = "isp";
  1453. idx = <1>;
  1454. path_type = "ISP_MI_PATH_PP";
  1455. output {
  1456. max_width = <1920>;
  1457. max_height = <1088>;
  1458. bit_per_pixel = <12>;
  1459. frame_count = <3>;
  1460. };
  1461. };
  1462. dsp {
  1463. subdev_name = "dsp";
  1464. idx = <0>;
  1465. path_type = "DSP_PATH_ISP_RY";
  1466. output {
  1467. max_width = <1920>;
  1468. max_height = <1088>;
  1469. bit_per_pixel = <12>;
  1470. frame_count = <3>;
  1471. };
  1472. };
  1473. ry {
  1474. subdev_name = "ry";
  1475. idx = <0>;
  1476. path_type = "ISP_RY_MI_PATH_MP";
  1477. output {
  1478. max_width = <1920>;
  1479. max_height = <1088>;
  1480. bit_per_pixel = <12>;
  1481. frame_count = <3>;
  1482. };
  1483. };
  1484. dw {
  1485. subdev_name = "dw";
  1486. idx = <0>;
  1487. path_type = "DW_DWE_VSE1";
  1488. dw_dst_depth = <2>;
  1489. };
  1490. };
  1491. pipline2 {
  1492. sensor0 {
  1493. subdev_name = "vivcam";
  1494. idx = <0>; //vivcam0 sc2310
  1495. csi_idx = <1>; //<1>=CSI2_B
  1496. mode_idx = <1>;
  1497. path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
  1498. };
  1499. dma {
  1500. path_type = "VIPRE_CSI1_ISP1";
  1501. };
  1502. isp {
  1503. subdev_name = "isp";
  1504. idx = <1>;
  1505. path_type = "ISP_MI_PATH_PP";
  1506. output {
  1507. max_width = <1920>;
  1508. max_height = <1088>;
  1509. bit_per_pixel = <12>;
  1510. frame_count = <3>;
  1511. };
  1512. };
  1513. dsp {
  1514. subdev_name = "dsp";
  1515. idx = <0>;
  1516. path_type = "DSP_PATH_ISP_RY";
  1517. output {
  1518. max_width = <1920>;
  1519. max_height = <1088>;
  1520. bit_per_pixel = <12>;
  1521. frame_count = <3>;
  1522. };
  1523. };
  1524. ry {
  1525. subdev_name = "ry";
  1526. idx = <0>;
  1527. path_type = "ISP_RY_MI_PATH_MP";
  1528. output {
  1529. max_width = <1920>;
  1530. max_height = <1088>;
  1531. bit_per_pixel = <12>;
  1532. frame_count = <3>;
  1533. };
  1534. };
  1535. dw {
  1536. subdev_name = "dw";
  1537. idx = <0>;
  1538. path_type = "DW_DWE_VSE2";
  1539. dw_dst_depth = <2>;
  1540. };
  1541. };
  1542. };
  1543. &video6{
  1544. vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1]
  1545. pipline0 {
  1546. sensor0 {
  1547. subdev_name = "vivcam";
  1548. idx = <1>; // vivcam1 sc132gs
  1549. csi_idx = <2>; //<2>=CSI2X2_A
  1550. flash_led_idx = <0>;
  1551. mode_idx = <0>;
  1552. path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
  1553. };
  1554. dsp{
  1555. output {
  1556. max_width = <1080>;
  1557. max_height = <1280>;
  1558. bit_per_pixel = <16>;
  1559. frame_count = <3>;
  1560. };
  1561. };
  1562. };
  1563. pipline1 {
  1564. sensor0 {
  1565. subdev_name = "vivcam";
  1566. idx = <1>; //vivcam1 sc132gs
  1567. csi_idx = <2>; //<2>=CSI2X2_A
  1568. flash_led_idx = <0>;
  1569. mode_idx = <0>;
  1570. path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
  1571. };
  1572. dsp{
  1573. output {
  1574. max_width = <1080>;
  1575. max_height = <1280>;
  1576. bit_per_pixel = <16>;
  1577. frame_count = <3>;
  1578. };
  1579. };
  1580. };
  1581. };
  1582. &video7{
  1583. pipline0 {
  1584. sensor0 {
  1585. subdev_name = "vivcam";
  1586. idx = <2>; //<2>=vivcam2 : gc5035
  1587. csi_idx = <0>; //<0>=CSI2
  1588. mode_idx = <3>;
  1589. path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
  1590. };
  1591. sensor1 {
  1592. subdev_name = "vivcam";
  1593. idx = <3>; //<3>=vivcam3 : gc02m1b
  1594. csi_idx = <0>; //<0>=CSI2
  1595. mode_idx = <0>;
  1596. path_type = "SENSOR_1600x1200_RAW10_LINER";
  1597. };
  1598. dma {
  1599. path_type = "VIPRE_CSI0_ISP0";
  1600. };
  1601. isp {
  1602. subdev_name = "isp";
  1603. idx = <0>;
  1604. path_type = "ISP_MI_PATH_PP";
  1605. output {
  1606. max_width = <1920>;
  1607. max_height = <1088>;
  1608. bit_per_pixel = <12>;
  1609. frame_count = <3>;
  1610. };
  1611. };
  1612. dsp {
  1613. subdev_name = "dsp";
  1614. idx = <1>;
  1615. path_type = "DSP_PATH_ISP_RY";
  1616. output {
  1617. max_width = <1920>;
  1618. max_height = <1088>;
  1619. bit_per_pixel = <12>;
  1620. frame_count = <3>;
  1621. };
  1622. };
  1623. ry {
  1624. subdev_name = "ry";
  1625. idx = <0>;
  1626. path_type = "ISP_RY_MI_PATH_MP";
  1627. output {
  1628. max_width = <1920>;
  1629. max_height = <1088>;
  1630. bit_per_pixel = <12>;
  1631. frame_count = <3>;
  1632. };
  1633. };
  1634. dw {
  1635. subdev_name = "dw";
  1636. idx = <0>;
  1637. path_type = "DW_DWE_VSE0";
  1638. dw_dst_depth = <2>;
  1639. };
  1640. };
  1641. pipline1 {
  1642. sensor0 {
  1643. subdev_name = "vivcam";
  1644. idx = <2>; //<2>=vivcam2 : gc5035
  1645. csi_idx = <0>; //<0>=CSI2
  1646. mode_idx = <3>;
  1647. path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
  1648. };
  1649. sensor1 {
  1650. subdev_name = "vivcam";
  1651. idx = <3>; //<3>=vivcam3 : gc02m1b
  1652. csi_idx = <0>; //<0>=CSI2
  1653. mode_idx = <0>;
  1654. path_type = "SENSOR_1600x1200_RAW10_LINER";
  1655. };
  1656. dma {
  1657. path_type = "VIPRE_CSI0_ISP0";
  1658. };
  1659. isp {
  1660. subdev_name = "isp";
  1661. idx = <0>;
  1662. path_type = "ISP_MI_PATH_PP";
  1663. output {
  1664. max_width = <1920>;
  1665. max_height = <1088>;
  1666. bit_per_pixel = <12>;
  1667. frame_count = <3>;
  1668. };
  1669. };
  1670. dsp {
  1671. subdev_name = "dsp";
  1672. idx = <1>;
  1673. path_type = "DSP_PATH_ISP_RY";
  1674. output {
  1675. max_width = <1920>;
  1676. max_height = <1088>;
  1677. bit_per_pixel = <12>;
  1678. frame_count = <3>;
  1679. };
  1680. };
  1681. ry {
  1682. subdev_name = "ry";
  1683. idx = <0>;
  1684. path_type = "ISP_RY_MI_PATH_MP";
  1685. output {
  1686. max_width = <1920>;
  1687. max_height = <1088>;
  1688. bit_per_pixel = <12>;
  1689. frame_count = <3>;
  1690. };
  1691. };
  1692. dw {
  1693. subdev_name = "dw";
  1694. idx = <0>;
  1695. path_type = "DW_DWE_VSE1";
  1696. dw_dst_depth = <2>;
  1697. };
  1698. };
  1699. pipline2 {
  1700. sensor0 {
  1701. subdev_name = "vivcam";
  1702. idx = <2>; //<2>=vivcam2 : gc5035
  1703. csi_idx = <0>; //<0>=CSI2
  1704. mode_idx = <3>;
  1705. path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
  1706. };
  1707. sensor1 {
  1708. subdev_name = "vivcam";
  1709. idx = <3>; //<3>=vivcam3 : gc02m1b
  1710. csi_idx = <0>; //<0>=CSI2
  1711. mode_idx = <0>;
  1712. path_type = "SENSOR_1600x1200_RAW10_LINER";
  1713. };
  1714. dma {
  1715. path_type = "VIPRE_CSI0_ISP0";
  1716. };
  1717. isp {
  1718. subdev_name = "isp";
  1719. idx = <0>;
  1720. path_type = "ISP_MI_PATH_PP";
  1721. output {
  1722. max_width = <1920>;
  1723. max_height = <1088>;
  1724. bit_per_pixel = <12>;
  1725. frame_count = <3>;
  1726. };
  1727. };
  1728. dsp {
  1729. subdev_name = "dsp";
  1730. idx = <1>;
  1731. path_type = "DSP_PATH_ISP_RY";
  1732. output {
  1733. max_width = <1920>;
  1734. max_height = <1088>;
  1735. bit_per_pixel = <12>;
  1736. frame_count = <3>;
  1737. };
  1738. };
  1739. ry {
  1740. subdev_name = "ry";
  1741. idx = <0>;
  1742. path_type = "ISP_RY_MI_PATH_MP";
  1743. output {
  1744. max_width = <1920>;
  1745. max_height = <1088>;
  1746. bit_per_pixel = <12>;
  1747. frame_count = <3>;
  1748. };
  1749. };
  1750. dw {
  1751. subdev_name = "dw";
  1752. idx = <0>;
  1753. path_type = "DW_DWE_VSE2";
  1754. dw_dst_depth = <2>;
  1755. };
  1756. };
  1757. };
  1758. &video8{
  1759. vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1]
  1760. pipline0 {
  1761. sensor0 {
  1762. subdev_name = "vivcam";
  1763. idx = <2>; //<2>=vivcam2 : gc5035
  1764. csi_idx = <0>; //<0>=CSI2
  1765. mode_idx = <3>;
  1766. path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
  1767. };
  1768. sensor1 {
  1769. subdev_name = "vivcam";
  1770. idx = <3>; //<3>=vivcam3 : gc02m1b
  1771. csi_idx = <0>; //<0>=CSI2
  1772. mode_idx = <0>;
  1773. path_type = "SENSOR_1600x1200_RAW10_LINER";
  1774. };
  1775. dma {
  1776. path_type = "VIPRE_CSI0_DSP";
  1777. };
  1778. dsp {
  1779. subdev_name = "dsp";
  1780. idx = <0>;
  1781. path_type = "DSP_PATH_VIPRE_DDR";
  1782. output {
  1783. max_width = <1920>;
  1784. max_height = <1088>;
  1785. bit_per_pixel = <12>;
  1786. frame_count = <3>;
  1787. };
  1788. };
  1789. };
  1790. };
  1791. &video9{
  1792. pipline0 {
  1793. sensor0 {
  1794. subdev_name = "vivcam";
  1795. idx = <1>; //vivcam1 sc132gs
  1796. csi_idx = <2>; //<2>=CSI2X2_A
  1797. mode_idx = <0>;
  1798. path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
  1799. };
  1800. dsp{
  1801. output {
  1802. max_width = <1080>;
  1803. max_height = <1280>;
  1804. bit_per_pixel = <16>;
  1805. frame_count = <3>;
  1806. };
  1807. };
  1808. };
  1809. };
  1810. &video10{ // TUNINGTOOL
  1811. pipline0 {
  1812. sensor0 {
  1813. subdev_name = "vivcam";
  1814. idx = <2>; //<2>=vivcam2 : gc5035
  1815. csi_idx = <0>; //<0>=CSI2
  1816. mode_idx = <1>;
  1817. path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
  1818. skip_init = <1>;
  1819. };
  1820. sensor1 {
  1821. subdev_name = "vivcam";
  1822. idx = <3>; //<3>=vivcam3 : gc02m1b
  1823. csi_idx = <0>; //<0>=CSI2
  1824. mode_idx = <0>;
  1825. path_type = "SENSOR_1600x1200_RAW10_LINER";
  1826. skip_init = <1>;
  1827. };
  1828. dma {
  1829. path_type = "VIPRE_CSI0_ISP0";
  1830. };
  1831. };
  1832. };
  1833. &video11{
  1834. pipline0 {
  1835. pipline_id = <0>;
  1836. status = "okay";
  1837. sensor0 {
  1838. subdev_name = "vivcam";
  1839. idx = <1>; //sc132gs
  1840. csi_idx = <2>; //<2>=CSI2X2_A
  1841. flash_led_idx = <0>;
  1842. mode_idx = <0>;
  1843. path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
  1844. };
  1845. isp {
  1846. subdev_name = "isp";
  1847. idx = <0>;
  1848. path_type = "ISP_MI_PATH_MP";
  1849. output {
  1850. max_width = <1920>;
  1851. max_height = <1088>;
  1852. bit_per_pixel = <12>;
  1853. frame_count = <3>;
  1854. };
  1855. };
  1856. };
  1857. };
  1858. &video12{ // TUNINGTOOL
  1859. pipline0 { // CSI2
  1860. sensor0 {
  1861. subdev_name = "vivcam";
  1862. idx = <0>; //sc2310
  1863. csi_idx = <1>; //<1>=CSI2_B
  1864. mode_idx = <1>;
  1865. path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
  1866. skip_init = <1>;
  1867. };
  1868. sensor1 {
  1869. subdev_name = "vivcam";
  1870. idx = <6>; //gc02m1b
  1871. csi_idx = <1>; //<1>=CSI2_B
  1872. mode_idx = <0>;
  1873. path_type = "SENSOR_1600x1200_RAW10_LINER";
  1874. skip_init = <1>;
  1875. };
  1876. };
  1877. dma {
  1878. path_type = "VIPRE_CSI1_ISP0";
  1879. };
  1880. };
  1881. &video13{
  1882. status = "okay";
  1883. //vi_mem_pool_region = <0>;
  1884. pipline0 {
  1885. pipline_id = <0>;
  1886. status = "okay";
  1887. sensor0 {
  1888. subdev_name = "vivcam";
  1889. idx = <0>; //sc2310
  1890. csi_idx = <1>; //<1>=CSI2_B
  1891. mode_idx = <1>;
  1892. path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
  1893. };
  1894. dma {
  1895. subdev_name = "vipre";
  1896. idx = <0>;
  1897. path_type = "VIPRE_CSI0_ISP0";
  1898. };
  1899. isp {
  1900. subdev_name = "isp";
  1901. idx = <0>;
  1902. path_type = "ISP_MI_MCM_WR0";
  1903. output {
  1904. max_width = <1920>;
  1905. max_height = <1088>;
  1906. bit_per_pixel = <16>;
  1907. frame_count = <3>;
  1908. };
  1909. };
  1910. };
  1911. };
  1912. &video14{
  1913. vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[0]
  1914. status = "okay";
  1915. pipline0 {
  1916. pipline_id = <0>;
  1917. status = "okay";
  1918. sensor0 {
  1919. subdev_name = "vivcam";
  1920. idx = <1>; //sc132gs
  1921. csi_idx = <2>; //<2>=CSI2X2_A
  1922. flash_led_idx = <0>;
  1923. mode_idx = <0>;
  1924. path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
  1925. };
  1926. dma {
  1927. subdev_name = "vipre";
  1928. idx = <0>;
  1929. path_type = "VIPRE_CSI2_ISP1";
  1930. };
  1931. isp {
  1932. subdev_name = "isp";
  1933. idx = <1>;
  1934. path_type = "ISP_MI_MCM_WR0";
  1935. output {
  1936. max_width = <1080>;
  1937. max_height = <1280>;
  1938. bit_per_pixel = <16>;
  1939. frame_count = <3>;
  1940. };
  1941. };
  1942. };
  1943. };
  1944. &video15{
  1945. status = "okay";
  1946. //vi_mem_pool_region = <0>;
  1947. pipline0 {
  1948. pipline_id = <0>;
  1949. status = "okay";
  1950. sensor0 {
  1951. subdev_name = "vivcam";
  1952. idx = <0>; //<0>=vivcam0 :2310
  1953. csi_idx = <1>; //<1>=CSI2_B
  1954. flash_led_idx = <0>;
  1955. mode_idx = <1>;
  1956. path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
  1957. };
  1958. dma {
  1959. subdev_name = "vipre";
  1960. idx = <0>;
  1961. path_type = "VIPRE_CSI0_DDR";
  1962. };
  1963. };
  1964. };
  1965. &trng {
  1966. status = "disabled";
  1967. };
  1968. &eip_28 {
  1969. status = "okay";
  1970. };
  1971. &vdec {
  1972. status = "okay";
  1973. };
  1974. &venc {
  1975. status = "okay";
  1976. };
  1977. &isp_venc_shake {
  1978. status = "okay";
  1979. };
  1980. &vidmem {
  1981. status = "okay";
  1982. memory-region = <&vi_mem>;
  1983. };
  1984. &gpu {
  1985. status = "okay";
  1986. };
  1987. &npu {
  1988. vha_clk_rate = <1000000000>;
  1989. status = "okay";
  1990. };
  1991. &fce {
  1992. memory-region = <&facelib_mem>;
  1993. status = "okay";
  1994. };
  1995. &dpu_enc0 {
  1996. status = "okay";
  1997. ports {
  1998. /* output */
  1999. port@1 {
  2000. reg = <1>;
  2001. enc0_out: endpoint {
  2002. remote-endpoint = <&dsi0_in>;
  2003. };
  2004. };
  2005. };
  2006. };
  2007. &dpu_enc1 {
  2008. ports {
  2009. /delete-node/ port@0;
  2010. };
  2011. };
  2012. &dpu {
  2013. status = "okay";
  2014. };
  2015. &dsi0 {
  2016. status = "okay";
  2017. };
  2018. &dhost_0 {
  2019. ports {
  2020. #address-cells = <1>;
  2021. #size-cells = <0>;
  2022. port@0 {
  2023. reg = <0>;
  2024. dsi0_in: endpoint {
  2025. remote-endpoint = <&enc0_out>;
  2026. };
  2027. };
  2028. port@1 {
  2029. reg = <1>;
  2030. dsi0_out: endpoint {
  2031. remote-endpoint = <&panel0_in>;
  2032. };
  2033. };
  2034. };
  2035. panel0@0 {
  2036. compatible = "txd,dy800qwxpab";
  2037. reg = <0>;
  2038. backlight = <&lcd0_backlight>;
  2039. reset-gpio = <&gpio1_porta 5 1>; /* active low */
  2040. vdd1v8-supply = <&soc_vdd18_lcd0_en_reg>;
  2041. vspn5v7-supply = <&soc_lcd0_bias_en_reg>;
  2042. port {
  2043. panel0_in: endpoint {
  2044. remote-endpoint = <&dsi0_out>;
  2045. };
  2046. };
  2047. };
  2048. };
  2049. &disp1_out {
  2050. remote-endpoint = <&hdmi_tx_in>;
  2051. };
  2052. &hdmi_tx {
  2053. status = "okay";
  2054. port@0 {
  2055. /* input */
  2056. hdmi_tx_in: endpoint {
  2057. remote-endpoint = <&disp1_out>;
  2058. };
  2059. };
  2060. };
  2061. &lightsound {
  2062. status = "okay";
  2063. simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/
  2064. reg = <0>;
  2065. format = "i2s";
  2066. cpu {
  2067. sound-dai = <&i2s1 0>;
  2068. };
  2069. codec {
  2070. sound-dai = <&es8156_audio_codec>;
  2071. };
  2072. };
  2073. simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/
  2074. reg = <1>;
  2075. format = "i2s";
  2076. cpu {
  2077. sound-dai = <&i2s3 0>;
  2078. };
  2079. codec {
  2080. sound-dai = <&es7210_audio_codec>;
  2081. };
  2082. };
  2083. simple-audio-card,dai-link@2 { /* I2S - HDMI */
  2084. reg = <2>;
  2085. format = "i2s";
  2086. cpu {
  2087. sound-dai = <&light_i2s 1>;
  2088. };
  2089. codec {
  2090. sound-dai = <&dummy_codec 2>;
  2091. };
  2092. };
  2093. };
  2094. &light_i2s {
  2095. status = "okay";
  2096. };
  2097. &i2s0 {
  2098. status = "okay";
  2099. };
  2100. &i2s1 {
  2101. status = "okay";
  2102. };
  2103. &i2s3 {
  2104. status = "okay";
  2105. };
  2106. &cpus {
  2107. c910_0: cpu@0 {
  2108. operating-points = <
  2109. /* kHz uV */
  2110. 300000 650000
  2111. 800000 700000
  2112. 1500000 800000
  2113. >;
  2114. light,dvddm-operating-points = <
  2115. /* kHz uV */
  2116. 300000 800000
  2117. 800000 800000
  2118. 1500000 800000
  2119. >;
  2120. };
  2121. c910_1: cpu@1 {
  2122. operating-points = <
  2123. /* kHz uV */
  2124. 300000 650000
  2125. 800000 700000
  2126. 1500000 800000
  2127. >;
  2128. light,dvddm-operating-points = <
  2129. /* kHz uV */
  2130. 300000 800000
  2131. 800000 800000
  2132. 1500000 800000
  2133. >;
  2134. };
  2135. c910_2: cpu@2 {
  2136. operating-points = <
  2137. /* kHz uV */
  2138. 300000 650000
  2139. 800000 700000
  2140. 1500000 800000
  2141. >;
  2142. light,dvddm-operating-points = <
  2143. /* kHz uV */
  2144. 300000 800000
  2145. 800000 800000
  2146. 1500000 800000
  2147. >;
  2148. };
  2149. c910_3: cpu@3 {
  2150. operating-points = <
  2151. /* kHz uV */
  2152. 300000 650000
  2153. 800000 700000
  2154. 1500000 800000
  2155. >;
  2156. light,dvddm-operating-points = <
  2157. /* kHz uV */
  2158. 300000 800000
  2159. 800000 800000
  2160. 1500000 800000
  2161. >;
  2162. };
  2163. };