light-a-product.dts 23 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2021 Alibaba Group Holding Limited.
  4. */
  5. /dts-v1/;
  6. #include "light.dtsi"
  7. / {
  8. model = "T-HEAD Light val board";
  9. compatible = "thead,light-val", "thead,light";
  10. chosen {
  11. bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000";
  12. stdout-path = "serial0:115200n8";
  13. };
  14. leds {
  15. compatible = "gpio-leds";
  16. led0 {
  17. label = "SYS_STATUS";
  18. //gpios = <&gpio1_porta 15 0>; /* GPIO_ACTIVE_HIGH: 0 */
  19. default-state = "off";
  20. };
  21. };
  22. lcd0_backlight: pwm-backlight@0 {
  23. compatible = "pwm-backlight";
  24. pwms = <&pwm 0 5000000>;
  25. brightness-levels = <0 4 8 16 32 64 128 255>;
  26. default-brightness-level = <7>;
  27. };
  28. lcd1_backlight: pwm-backlight@1 {
  29. compatible = "pwm-backlight";
  30. pwms = <&pwm 1 5000000>;
  31. brightness-levels = <0 4 8 16 32 64 128 255>;
  32. default-brightness-level = <7>;
  33. };
  34. light_iopmp: iopmp {
  35. compatible = "thead,light-iopmp";
  36. /* config#1: multiple valid regions */
  37. iopmp_emmc: IOPMP_EMMC {
  38. regions = <0x000000 0x100000>,
  39. <0x100000 0x200000>;
  40. attr = <0xFFFFFFFF>;
  41. dummy_slave= <0x800000>;
  42. };
  43. /* config#2: iopmp bypass */
  44. iopmp_sdio0: IOPMP_SDIO0 {
  45. bypass_en;
  46. };
  47. /* config#3: iopmp default region set */
  48. iopmp_sdio1: IOPMP_SDIO1 {
  49. attr = <0xFFFFFFFF>;
  50. is_default_region;
  51. };
  52. iopmp_usb0: IOPMP_USB0 {
  53. attr = <0xFFFFFFFF>;
  54. is_default_region;
  55. };
  56. iopmp_ao: IOPMP_AO {
  57. is_default_region;
  58. };
  59. iopmp_aud: IOPMP_AUD {
  60. is_default_region;
  61. };
  62. iopmp_chip_dbg: IOPMP_CHIP_DBG {
  63. is_default_region;
  64. };
  65. iopmp_eip120i: IOPMP_EIP120I {
  66. is_default_region;
  67. };
  68. iopmp_eip120ii: IOPMP_EIP120II {
  69. is_default_region;
  70. };
  71. iopmp_eip120iii: IOPMP_EIP120III {
  72. is_default_region;
  73. };
  74. iopmp_isp0: IOPMP_ISP0 {
  75. is_default_region;
  76. };
  77. iopmp_isp1: IOPMP_ISP1 {
  78. is_default_region;
  79. };
  80. iopmp_dw200: IOPMP_DW200 {
  81. is_default_region;
  82. };
  83. iopmp_vipre: IOPMP_VIPRE {
  84. is_default_region;
  85. };
  86. iopmp_venc: IOPMP_VENC {
  87. is_default_region;
  88. };
  89. iopmp_vdec: IOPMP_VDEC {
  90. is_default_region;
  91. };
  92. iopmp_g2d: IOPMP_G2D {
  93. is_default_region;
  94. };
  95. iopmp_fce: IOPMP_FCE {
  96. is_default_region;
  97. };
  98. iopmp_npu: IOPMP_NPU {
  99. is_default_region;
  100. };
  101. iopmp0_dpu: IOPMP0_DPU {
  102. bypass_en;
  103. };
  104. iopmp1_dpu: IOPMP1_DPU {
  105. bypass_en;
  106. };
  107. iopmp_gpu: IOPMP_GPU {
  108. is_default_region;
  109. };
  110. iopmp_gmac1: IOPMP_GMAC1 {
  111. is_default_region;
  112. };
  113. iopmp_gmac2: IOPMP_GMAC2 {
  114. is_default_region;
  115. };
  116. iopmp_dmac: IOPMP_DMAC {
  117. is_default_region;
  118. };
  119. iopmp_tee_dmac: IOPMP_TEE_DMAC {
  120. is_default_region;
  121. };
  122. iopmp_dsp0: IOPMP_DSP0 {
  123. is_default_region;
  124. };
  125. iopmp_dsp1: IOPMP_DSP1 {
  126. is_default_region;
  127. };
  128. };
  129. mbox_910t_client1: mbox_910t_client1 {
  130. compatible = "thead,light-mbox-client";
  131. mbox-names = "902";
  132. mboxes = <&mbox_910t 1 0>;
  133. status = "disabled";
  134. };
  135. mbox_910t_client2: mbox_910t_client2 {
  136. compatible = "thead,light-mbox-client";
  137. mbox-names = "906";
  138. mboxes = <&mbox_910t 2 0>;
  139. status = "disabled";
  140. };
  141. lightsound: lightsound@1 {
  142. compatible = "simple-audio-card";
  143. simple-audio-card,name = "Light-Sound-Card";
  144. #address-cells = <1>;
  145. #size-cells = <0>;
  146. status = "disabled";
  147. };
  148. dummy_codec: dummy_codec {
  149. #sound-dai-cells = <1>;
  150. compatible = "linux,bt-sco";
  151. status = "okay";
  152. };
  153. reg_vref_1v8: regulator-adc-verf {
  154. compatible = "regulator-fixed";
  155. regulator-name = "vref-1v8";
  156. regulator-min-microvolt = <1800000>;
  157. regulator-max-microvolt = <1800000>;
  158. status = "okay";
  159. };
  160. reg_tp_pwr_en: regulator-pwr-en {
  161. compatible = "regulator-fixed";
  162. regulator-name = "PWR_EN";
  163. regulator-min-microvolt = <2800000>;
  164. regulator-max-microvolt = <2800000>;
  165. gpio = <&pcal6408ahk_a 3 1>;
  166. enable-active-high;
  167. regulator-always-on;
  168. };
  169. reg_tp1_pwr_en: regulator-tp1-pwr-en {
  170. compatible = "regulator-fixed";
  171. regulator-name = "PWR_EN";
  172. regulator-min-microvolt = <2800000>;
  173. regulator-max-microvolt = <2800000>;
  174. gpio = <&pcal6408ahk_a 6 1>;
  175. enable-active-high;
  176. regulator-always-on;
  177. };
  178. wcn_wifi: wireless-wlan {
  179. compatible = "wlan-platdata";
  180. clock-names = "clk_wifi";
  181. ref-clock-frequency = <24000000>;
  182. keep_wifi_power_on;
  183. pinctrl-names = "default";
  184. wifi_chip_type = "rtl8723ds";
  185. WIFI,poweren_gpio = <&gpio2_porta 26 0>;
  186. WIFI,reset_n = <&gpio2_porta 28 0>;
  187. status = "disabled";
  188. };
  189. wcn_bt: wireless-bluetooth {
  190. compatible = "bluetooth-platdata";
  191. pinctrl-names = "default", "rts_gpio";
  192. BT,power_gpio = <&gpio2_porta 29 0>;
  193. status = "disabled";
  194. };
  195. aon {
  196. compatible = "thead,light-aon";
  197. mbox-names = "aon";
  198. mboxes = <&mbox_910t 1 0>;
  199. status = "okay";
  200. pd: light-aon-pd {
  201. compatible = "thead,light-aon-pd";
  202. #power-domain-cells = <1>;
  203. };
  204. soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
  205. compatible = "regulator-fixed";
  206. regulator-name = "soc_avdd28_scan_en";
  207. regulator-min-microvolt = <2800000>;
  208. regulator-max-microvolt = <2800000>;
  209. gpio = <&ao_gpio_porta 14 1>;
  210. enable-active-high;
  211. regulator-always-on;
  212. };
  213. soc_dovdd18_scan_reg: soc_dovdd18_scan {
  214. compatible = "regulator-fixed";
  215. regulator-name = "soc_dovdd18_scan";
  216. regulator-min-microvolt = <1800000>;
  217. regulator-max-microvolt = <1800000>;
  218. gpio = <&gpio0_porta 10 1>;
  219. enable-active-high;
  220. regulator-always-on;
  221. };
  222. soc_dvdd12_scan_reg: soc_dvdd12_scan {
  223. compatible = "regulator-fixed";
  224. regulator-name = "soc_dvdd12_scan";
  225. regulator-min-microvolt = <1200000>;
  226. regulator-max-microvolt = <1200000>;
  227. gpio = <&gpio0_porta 11 1>;
  228. enable-active-high;
  229. regulator-always-on;
  230. };
  231. soc_vext_2v8_reg: soc_vext_2v8 {
  232. compatible = "regulator-fixed";
  233. regulator-name = "soc_vext_2v8";
  234. regulator-min-microvolt = <2800000>;
  235. regulator-max-microvolt = <2800000>;
  236. gpio = <&gpio1_porta 7 1>;
  237. enable-active-high;
  238. regulator-always-on;
  239. };
  240. soc_avdd28_rgb_reg: soc_avdd28_rgb {
  241. compatible = "regulator-fixed";
  242. regulator-name = "soc_avdd28_rgb";
  243. regulator-min-microvolt = <2800000>;
  244. regulator-max-microvolt = <2800000>;
  245. gpio = <&gpio1_porta 24 1>;
  246. enable-active-high;
  247. regulator-always-on;
  248. };
  249. soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
  250. compatible = "regulator-fixed";
  251. regulator-name = "soc_dovdd18_rgb";
  252. regulator-min-microvolt = <1800000>;
  253. regulator-max-microvolt = <1800000>;
  254. gpio = <&gpio1_porta 22 1>;
  255. enable-active-high;
  256. regulator-always-on;
  257. };
  258. soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
  259. compatible = "regulator-fixed";
  260. regulator-name = "soc_dvdd12_rgb";
  261. regulator-min-microvolt = <1500000>;
  262. regulator-max-microvolt = <1500000>;
  263. gpio = <&gpio1_porta 25 1>;
  264. enable-active-high;
  265. regulator-always-on;
  266. };
  267. soc_avdd25_ir_reg: soc_avdd25_ir {
  268. compatible = "regulator-fixed";
  269. regulator-name = "soc_avdd25_ir";
  270. regulator-min-microvolt = <2500000>;
  271. regulator-max-microvolt = <2500000>;
  272. gpio = <&gpio1_porta 21 1>;
  273. enable-active-high;
  274. regulator-always-on;
  275. };
  276. soc_dovdd18_ir_reg: soc_dovdd18_ir {
  277. compatible = "regulator-fixed";
  278. regulator-name = "soc_dovdd18_ir";
  279. regulator-min-microvolt = <1800000>;
  280. regulator-max-microvolt = <1800000>;
  281. gpio = <&gpio1_porta 22 1>;
  282. enable-active-high;
  283. regulator-always-on;
  284. };
  285. soc_dvdd12_ir_reg: soc_dvdd12_ir {
  286. compatible = "regulator-fixed";
  287. regulator-name = "soc_dvdd12_ir";
  288. regulator-min-microvolt = <1200000>;
  289. regulator-max-microvolt = <1200000>;
  290. gpio = <&gpio1_porta 23 1>;
  291. enable-active-high;
  292. regulator-always-on;
  293. };
  294. aon_reg_ricoh: light-ricoh-reg {
  295. compatible = "thead,light-ricoh-pmic";
  296. status = "okay";
  297. dvdd_cpu_reg: appcpu_dvdd {
  298. regulator-name = "appcpu_dvdd";
  299. regulator-min-microvolt = <600000>;
  300. regulator-max-microvolt = <1500000>;
  301. regulator-boot-on;
  302. regulator-always-on;
  303. };
  304. dvddm_cpu_reg: appcpu_dvddm {
  305. regulator-name = "appcpu_dvddm";
  306. regulator-min-microvolt = <600000>;
  307. regulator-max-microvolt = <1500000>;
  308. regulator-boot-on;
  309. regulator-always-on;
  310. };
  311. soc_dvdd18_aon_reg: soc_dvdd18_aon {
  312. regulator-name = "soc_dvdd18_aon";
  313. regulator-boot-on;
  314. regulator-always-on;
  315. };
  316. soc_avdd33_usb3_reg: soc_avdd33_usb3 {
  317. regulator-name = "soc_avdd33_usb3";
  318. regulator-boot-on;
  319. regulator-always-on;
  320. };
  321. soc_dvdd08_aon_reg: soc_dvdd08_aon {
  322. regulator-name = "soc_dvdd08_aon";
  323. regulator-boot-on;
  324. regulator-always-on;
  325. };
  326. soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
  327. regulator-name = "soc_dvdd08_ddr";
  328. regulator-boot-on;
  329. regulator-always-on;
  330. };
  331. soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
  332. regulator-name = "soc_vdd_ddr_1v8";
  333. regulator-boot-on;
  334. regulator-always-on;
  335. };
  336. soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
  337. regulator-name = "soc_vdd_ddr_1v1";
  338. regulator-boot-on;
  339. regulator-always-on;
  340. };
  341. soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
  342. regulator-name = "soc_vdd_ddr_0v6";
  343. regulator-boot-on;
  344. regulator-always-on;
  345. };
  346. soc_dvdd18_ap_reg: soc_dvdd18_ap {
  347. regulator-name = "soc_dvdd18_ap";
  348. regulator-boot-on;
  349. regulator-always-on;
  350. };
  351. soc_dvdd08_ap_reg: soc_dvdd08_ap {
  352. regulator-name = "soc_dvdd08_ap";
  353. regulator-boot-on;
  354. regulator-always-on;
  355. };
  356. soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
  357. regulator-name = "soc_avdd08_mipi_hdmi";
  358. regulator-boot-on;
  359. regulator-always-on;
  360. };
  361. soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
  362. regulator-name = "soc_avdd18_mipi_hdmi";
  363. regulator-boot-on;
  364. regulator-always-on;
  365. };
  366. soc_vdd33_emmc_reg: soc_dvdd33_emmc {
  367. regulator-name = "soc_dvdd33_emmc";
  368. regulator-boot-on;
  369. regulator-always-on;
  370. };
  371. soc_vdd18_emmc_reg: soc_dvdd18_emmc {
  372. regulator-name = "soc_dvdd18_emmc";
  373. regulator-boot-on;
  374. regulator-always-on;
  375. };
  376. };
  377. c910_cpufreq {
  378. compatible = "thead,light-mpw-cpufreq";
  379. status = "okay";
  380. };
  381. test: light-aon-test {
  382. compatible = "thead,light-aon-test";
  383. };
  384. };
  385. };
  386. &cmamem {
  387. alloc-ranges = <0 0xe4000000 0 0x14000000>; // [0xE400_0000 ~ 0xF800_0000]
  388. };
  389. &resmem {
  390. #address-cells = <2>;
  391. #size-cells = <2>;
  392. ranges;
  393. tee_mem: memory@1a000000 {
  394. reg = <0x0 0x1a000000 0 0x4000000>;
  395. no-map;
  396. };
  397. dsp0_mem: memory@20000000 { /**0x2000_0000~0x2040_0000 4M**/
  398. reg = <0x0 0x20000000 0x0 0x00280000 /* DSP FW code&data section 2.5M*/
  399. 0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/
  400. 0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */
  401. 0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/
  402. no-map;
  403. };
  404. dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/
  405. reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */
  406. 0x0 0x20680000 0x0 0x00001000 /* DSP communication area */
  407. 0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/
  408. 0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */
  409. no-map;
  410. };
  411. vi_mem: framebuffer@0f800000 {
  412. reg = <0x0 0x0F800000 0x0 0x05400000 /* vi_mem_pool_region[0] 84 MB (default) */
  413. 0x0 0x14C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */
  414. 0x0 0x16900000 0x0 0x03200000>; /* vi_mem_pool_region[2] 50 MB */
  415. no-map;
  416. };
  417. facelib_mem: memory@22000000 {
  418. reg = <0x0 0x22000000 0x0 0x10000000>;
  419. no-map;
  420. };
  421. };
  422. &adc {
  423. vref-supply = <&reg_vref_1v8>;
  424. status = "okay";
  425. };
  426. &i2c0 {
  427. clock-frequency = <400000>;
  428. status = "okay";
  429. eeprom@50 {
  430. compatible = "atmel,24c32";
  431. reg = <0x50>;
  432. pagesize = <32>;
  433. };
  434. codec: wm8960@1a {
  435. #sound-dai-cells = <0>;
  436. compatible = "wlf,wm8960";
  437. reg = <0x1a>;
  438. wlf,shared-lrclk;
  439. wlf,hp-cfg = <3 2 3>;
  440. wlf,gpio-cfg = <1 3>;
  441. };
  442. touch@5d {
  443. #gpio-cells = <2>;
  444. compatible = "goodix,gt911";
  445. reg = <0x5d>;
  446. interrupt-parent = <&gpio1_porta>;
  447. interrupts = <8 0>;
  448. irq-gpios = <&gpio1_porta 8 0>;
  449. reset-gpios = <&gpio1_porta 7 0>;
  450. AVDD28-supply = <&reg_tp_pwr_en>;
  451. touchscreen-size-x = <720>;
  452. touchscreen-size-y = <1280>;
  453. };
  454. };
  455. &i2c1 {
  456. clock-frequency = <400000>;
  457. status = "okay";
  458. touch1@5d {
  459. #gpio-cells = <2>;
  460. compatible = "goodix,gt911";
  461. reg = <0x5d>;
  462. interrupt-parent = <&gpio1_porta>;
  463. interrupts = <12 0>;
  464. irq-gpios = <&gpio1_porta 12 0>;
  465. reset-gpios = <&gpio1_porta 11 0>;
  466. AVDD28-supply = <&reg_tp1_pwr_en>;
  467. touchscreen-size-x = <720>;
  468. touchscreen-size-y = <1280>;
  469. };
  470. };
  471. &spi0 {
  472. num-cs = <1>;
  473. cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0
  474. rx-sample-delay-ns = <10>;
  475. status = "disabled";
  476. spi_norflash@0 {
  477. #address-cells = <1>;
  478. #size-cells = <1>;
  479. compatible = "winbond,w25q64jwm", "jedec,spi-nor";
  480. reg = <0>;
  481. spi-max-frequency = <50000000>;
  482. w25q,fast-read;
  483. };
  484. spidev@1 {
  485. compatible = "spidev";
  486. #address-cells = <0x1>;
  487. #size-cells = <0x1>;
  488. reg = <0x1>;
  489. spi-max-frequency = <50000000>;
  490. };
  491. };
  492. &uart0 {
  493. clock-frequency = <100000000>;
  494. };
  495. &qspi0 {
  496. num-cs = <1>;
  497. cs-gpios = <&gpio2_porta 3 0>;
  498. rx-sample-dly = <4>;
  499. status = "disabled";
  500. spi-flash@0 {
  501. #address-cells = <1>;
  502. #size-cells = <1>;
  503. compatible = "spi-nand";
  504. spi-max-frequency = <100000000>;
  505. spi-tx-bus-width = <4>;
  506. spi-rx-bus-width = <4>;
  507. reg = <0>;
  508. partition@0 {
  509. label = "ubi1";
  510. reg = <0x00000000 0x08000000>;
  511. };
  512. };
  513. };
  514. &qspi1 {
  515. num-cs = <1>;
  516. cs-gpios = <&gpio0_porta 1 0>;
  517. status = "disabled";
  518. spi-flash@0 {
  519. #address-cells = <1>;
  520. #size-cells = <1>;
  521. compatible = "spi-nand";
  522. spi-max-frequency = <66000000>;
  523. spi-tx-bus-width = <4>;
  524. spi-rx-bus-width = <4>;
  525. reg = <0>;
  526. partition@0 {
  527. label = "ubi2";
  528. reg = <0x00000000 0x08000000>;
  529. };
  530. };
  531. };
  532. &gmac0 {
  533. phy-mode = "rgmii-id";
  534. rx-clk-delay = <0x00>; /* for RGMII */
  535. tx-clk-delay = <0x00>; /* for RGMII */
  536. phy-handle = <&phy_88E1111_0>;
  537. status = "okay";
  538. mdio0 {
  539. #address-cells = <1>;
  540. #size-cells = <0>;
  541. compatible = "snps,dwmac-mdio";
  542. phy_88E1111_0: ethernet-phy@0 {
  543. reg = <0x1>;
  544. };
  545. phy_88E1111_1: ethernet-phy@1 {
  546. reg = <0x2>;
  547. };
  548. };
  549. };
  550. &gmac1 {
  551. phy-mode = "rgmii-id";
  552. rx-clk-delay = <0x00>; /* for RGMII */
  553. tx-clk-delay = <0x00>; /* for RGMII */
  554. phy-handle = <&phy_88E1111_1>;
  555. status = "okay";
  556. };
  557. &emmc {
  558. max-frequency = <198000000>;
  559. non-removable;
  560. mmc-hs400-1_8v;
  561. io_fixed_1v8;
  562. is_emmc;
  563. no-sdio;
  564. no-sd;
  565. pull_up;
  566. bus-width = <8>;
  567. status = "okay";
  568. };
  569. &sdhci0 {
  570. max-frequency = <198000000>;
  571. bus-width = <4>;
  572. pull_up;
  573. wprtn_ignore;
  574. status = "okay";
  575. };
  576. &sdhci1 {
  577. max-frequency = <100000000>;
  578. bus-width = <4>;
  579. pull_up;
  580. no-sd;
  581. no-mmc;
  582. non-removable;
  583. io_fixed_1v8;
  584. post-power-on-delay-ms = <50>;
  585. wprtn_ignore;
  586. cap-sd-highspeed;
  587. keep-power-in-suspend;
  588. wakeup-source;
  589. status = "disabled";
  590. };
  591. &padctrl0_apsys { /* right-pinctrl */
  592. light-evb-padctrl0 {
  593. /*
  594. * Pin Configuration Node:
  595. * Format: <pin_id mux_node config>
  596. */
  597. pinctrl_uart0: uart0grp {
  598. thead,pins = <
  599. FM_UART0_TXD 0x0 0x72
  600. FM_UART0_RXD 0x0 0x72
  601. >;
  602. };
  603. pinctrl_spi0: spi0grp {
  604. thead,pins = <
  605. FM_SPI_CSN 0x3 0x20a
  606. FM_SPI_SCLK 0x0 0x20a
  607. FM_SPI_MISO 0x0 0x23a
  608. FM_SPI_MOSI 0x0 0x23a
  609. >;
  610. };
  611. pinctrl_qspi0: qspi0grp {
  612. thead,pins = <
  613. FM_QSPI0_SCLK 0x0 0x20f
  614. FM_QSPI0_CSN0 0x3 0x20f
  615. FM_QSPI0_CSN1 0x0 0x20f
  616. FM_QSPI0_D0_MOSI 0x0 0x23f
  617. FM_QSPI0_D1_MISO 0x0 0x23f
  618. FM_QSPI0_D2_WP 0x0 0x23f
  619. FM_QSPI0_D3_HOLD 0x0 0x23f
  620. >;
  621. };
  622. pinctrl_audio_i2s0: i2s0grp {
  623. thead,pins = <
  624. FM_QSPI0_SCLK 0x2 0x208
  625. FM_QSPI0_CSN0 0x2 0x238
  626. FM_QSPI0_CSN1 0x2 0x208
  627. FM_QSPI0_D0_MOSI 0x2 0x238
  628. FM_QSPI0_D1_MISO 0x2 0x238
  629. FM_QSPI0_D2_WP 0x2 0x238
  630. FM_QSPI0_D3_HOLD 0x2 0x238
  631. >;
  632. };
  633. pinctrl_pwm: pwmgrp {
  634. thead,pins = <
  635. FM_GPIO3_2 0x1 0x208 /* pwm0 */
  636. FM_GPIO3_3 0x1 0x208 /* pwm1 */
  637. >;
  638. };
  639. };
  640. };
  641. &padctrl1_apsys { /* left-pinctrl */
  642. light-evb-padctrl1 {
  643. /*
  644. * Pin Configuration Node:
  645. * Format: <pin_id mux_node config>
  646. */
  647. pinctrl_uart3: uart3grp {
  648. thead,pins = <
  649. FM_UART3_TXD 0x0 0x72
  650. FM_UART3_RXD 0x0 0x72
  651. >;
  652. };
  653. pinctrl_uart4: uart4grp {
  654. thead,pins = <
  655. FM_UART4_TXD 0x0 0x72
  656. FM_UART4_RXD 0x0 0x72
  657. FM_UART4_CTSN 0x0 0x72
  658. FM_UART4_RTSN 0x0 0x72
  659. >;
  660. };
  661. pinctrl_qspi1: qspi1grp {
  662. thead,pins = <
  663. FM_QSPI1_SCLK 0x0 0x20a
  664. FM_QSPI1_CSN0 0x3 0x20a
  665. FM_QSPI1_D0_MOSI 0x0 0x23a
  666. FM_QSPI1_D1_MISO 0x0 0x23a
  667. FM_QSPI1_D2_WP 0x0 0x23a
  668. FM_QSPI1_D3_HOLD 0x0 0x23a
  669. >;
  670. };
  671. pinctrl_iso7816: iso7816grp {
  672. thead,pins = <
  673. FM_QSPI1_SCLK 0x1 0x208
  674. FM_QSPI1_D0_MOSI 0x1 0x238
  675. FM_QSPI1_D1_MISO 0x1 0x238
  676. FM_QSPI1_D2_WP 0x1 0x238
  677. FM_QSPI1_D3_HOLD 0x1 0x238
  678. >;
  679. };
  680. };
  681. };
  682. &padctrl_aosys {
  683. light-aon-padctrl {
  684. /*
  685. * Pin Configuration Node:
  686. * Format: <pin_id mux_node config>
  687. */
  688. pinctrl_audiopa1: audiopa1_grp {
  689. thead,pins = <
  690. FM_AUDIO_PA1 0x3 0x72
  691. >;
  692. };
  693. pinctrl_audiopa2: audiopa2_grp {
  694. thead,pins = <
  695. FM_AUDIO_PA2 0x0 0x72
  696. >;
  697. };
  698. };
  699. };
  700. &i2c2 {
  701. clock-frequency = <400000>;
  702. status = "okay";
  703. eeprom@50 {
  704. compatible = "atmel,24c32";
  705. reg = <0x50>;
  706. pagesize = <32>;
  707. };
  708. };
  709. &i2c3 {
  710. clock-frequency = <400000>;
  711. status = "okay";
  712. eeprom@50 {
  713. compatible = "atmel,24c32";
  714. reg = <0x50>;
  715. pagesize = <32>;
  716. };
  717. };
  718. &i2c4 {
  719. clock-frequency = <400000>;
  720. status = "okay";
  721. eeprom@50 {
  722. compatible = "atmel,24c32";
  723. reg = <0x50>;
  724. pagesize = <32>;
  725. };
  726. pcal6408ahk_a: gpio@20 {
  727. compatible = "nxp,pcal9554b";
  728. reg = <0x20>;
  729. gpio-controller;
  730. #gpio-cells = <2>;
  731. };
  732. };
  733. &isp0 {
  734. status = "okay";
  735. };
  736. &isp1 {
  737. status = "okay";
  738. };
  739. &isp_ry0 {
  740. status = "okay";
  741. };
  742. &dewarp {
  743. status = "okay";
  744. };
  745. &dec400_isp0 {
  746. status = "okay";
  747. };
  748. &dec400_isp1 {
  749. status = "okay";
  750. };
  751. &dec400_isp2 {
  752. status = "okay";
  753. };
  754. &bm_visys {
  755. status = "okay";
  756. };
  757. &bm_csi0 {
  758. status = "okay";
  759. };
  760. &bm_csi1 {
  761. status = "okay";
  762. };
  763. &bm_csi2 {
  764. status = "okay";
  765. };
  766. &vi_pre {
  767. //vi_pre_irq_en = <1>;
  768. status = "okay";
  769. };
  770. &xtensa_dsp {
  771. status = "okay";
  772. };
  773. &xtensa_dsp {
  774. status = "okay";
  775. };
  776. &xtensa_dsp0 {
  777. status = "okay";
  778. memory-region = <&dsp0_mem>;
  779. };
  780. &xtensa_dsp1{
  781. status = "okay";
  782. memory-region = <&dsp1_mem>;
  783. };
  784. &vvcam_flash_led0{
  785. //flood_lignt_name = "aw36413";
  786. //projection_lignt_name = "aw36515";
  787. flash_led_name = "aw36413_aw36515";
  788. floodlight_i2c_bus = /bits/ 8 <2>;
  789. projection_i2c_bus = /bits/ 8 <2>;
  790. flash_led_touch_pin = <&gpio1_porta 29 0>; //flash led touch pin
  791. status = "okay";
  792. };
  793. &vvcam_sensor0 {
  794. sensor_name = "SC2310";
  795. sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB";
  796. sensor_regulator_timing_us = <70 50 20>;
  797. sensor_pdn = <&gpio1_porta 28 0>; //powerdown pin / shutdown pin
  798. sensor_rst = <&gpio1_porta 16 0>;
  799. sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready
  800. DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
  801. DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
  802. AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>;
  803. i2c_reg_width = /bits/ 8 <2>;
  804. i2c_data_width = /bits/ 8 <1>;
  805. i2c_addr = /bits/ 8 <0x30>;
  806. i2c_bus = /bits/ 8 <3>;
  807. status = "okay";
  808. };
  809. &vvcam_sensor1 {
  810. sensor_name = "SC132GS";
  811. sensor_regulators = "DOVDD18_IR", "DVDD12_IR", "AVDD25_IR";
  812. sensor_regulator_timing_us = <70 50 20>;
  813. i2c_addr = /bits/ 8 <0x31>;
  814. sensor_pdn = <&gpio1_porta 14 0>;
  815. sensor_rst = <&gpio1_porta 15 0>;
  816. sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready
  817. DOVDD18_IR-supply = <&soc_dovdd18_ir_reg>;
  818. DVDD12_IR-supply = <&soc_dvdd12_ir_reg>;
  819. AVDD25_IR-supply = <&soc_avdd25_ir_reg>;
  820. i2c_reg_width = /bits/ 8 <2>;
  821. i2c_data_width = /bits/ 8 <1>;
  822. i2c_bus = /bits/ 8 <2>;
  823. status = "okay";
  824. };
  825. &video0{
  826. status = "okay";
  827. piplane0 {
  828. pipline_id = <0>;
  829. status = "okay";
  830. sensor0 {
  831. subdev_name = "vivcam";
  832. idx = <1>; //sc132gs
  833. csi_idx = <2>; //<2>=CSI2X2_A
  834. flash_led_idx = <0>;
  835. path_type = "SENSOR_1080P_RAW10_LINER";
  836. };
  837. dma {
  838. subdev_name = "vipre";
  839. idx = <0>;
  840. path_type = "VIPRE_CSI2_DDR";
  841. };
  842. dsp {
  843. subdev_name = "dsp";
  844. idx = <0>;
  845. path_type = "DSP_PATH_VIPRE_DDR";
  846. };
  847. };
  848. };
  849. &video1{
  850. status = "okay";
  851. piplane0 { // VSE0
  852. pipline_id = <0>;
  853. status = "okay";
  854. sensor0 {
  855. subdev_name = "vivcam";
  856. idx = <1>; //sc132gs
  857. csi_idx = <2>; //<2>=CSI2X2_A
  858. flash_led_idx = <0>;
  859. path_type = "SENSOR_1080P_RAW10_LINER";
  860. };
  861. dma {
  862. subdev_name = "vipre";
  863. idx = <0>;
  864. path_type = "VIPRE_CSI2_ISP0";
  865. };
  866. isp {
  867. subdev_name = "isp";
  868. idx = <0>;
  869. path_type = "ISP_MI_PATH_MP";
  870. };
  871. };
  872. };
  873. &video2{
  874. status = "okay";
  875. piplane0 {
  876. pipline_id = <0>;
  877. status = "okay";
  878. sensor0 {
  879. subdev_name = "vivcam";
  880. idx = <1>; //sc132gs
  881. csi_idx = <2>; //<2>=CSI2X2_A
  882. flash_led_idx = <0>;
  883. path_type = "SENSOR_1080P_RAW10_LINER";
  884. };
  885. dma {
  886. subdev_name = "vipre";
  887. idx = <0>;
  888. path_type = "VIPRE_CSI2_DDR";
  889. };
  890. dsp {
  891. subdev_name = "dsp";
  892. idx = <1>;
  893. path_type = "DSP_PATH_VIPRE_ODD";
  894. };
  895. };
  896. piplane1 {
  897. pipline_id = <1>;
  898. status = "okay";
  899. sensor0 {
  900. subdev_name = "vivcam";
  901. idx = <1>; //sc132gs
  902. csi_idx = <2>; //<2>=CSI2X2_A
  903. flash_led_idx = <0>;
  904. path_type = "SENSOR_1080P_RAW10_LINER";
  905. };
  906. dma {
  907. subdev_name = "vipre";
  908. idx = <0>;
  909. path_type = "VIPRE_CSI2_DDR";
  910. };
  911. dsp {
  912. subdev_name = "dsp";
  913. idx = <1>;
  914. path_type = "DSP_PATH_VIPRE_EVEN";
  915. };
  916. };
  917. };
  918. &trng {
  919. status = "disabled";
  920. };
  921. &eip_28 {
  922. status = "okay";
  923. };
  924. &vdec {
  925. status = "okay";
  926. };
  927. &venc {
  928. status = "okay";
  929. };
  930. &isp_venc_shake {
  931. status = "okay";
  932. };
  933. &vidmem {
  934. status = "okay";
  935. memory-region = <&vi_mem>;
  936. };
  937. &gpu {
  938. status = "okay";
  939. };
  940. &npu {
  941. vha_clk_rate = <1000000000>;
  942. status = "okay";
  943. };
  944. &fce {
  945. memory-region = <&facelib_mem>;
  946. status = "okay";
  947. };