ice.dts 9.2 KB

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  1. /dts-v1/;
  2. / {
  3. model = "T-HEAD c910 ice";
  4. compatible = "thead,c910_ice";
  5. #address-cells = <2>;
  6. #size-cells = <2>;
  7. memory@0 {
  8. device_type = "memory";
  9. /*
  10. * Total memory size: 4GB (0x00000000 0x100000000)
  11. * 0x00200000 - 0x0e0000000: 3407MB for Linux system
  12. * 0xe0000000 - 0x100000000: 512MB for GPU
  13. */
  14. reg = <0x0 0x200000 0x0 0xdfe00000>;
  15. };
  16. cpus {
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. timebase-frequency = <3000000>;
  20. cpu@0 {
  21. device_type = "cpu";
  22. reg = <0>;
  23. status = "okay";
  24. compatible = "riscv";
  25. riscv,isa = "rv64imafdcsu";
  26. mmu-type = "riscv,sv39";
  27. cpu-freq = "1.2Ghz";
  28. cpu-icache = "64KB";
  29. cpu-dcache = "64KB";
  30. cpu-l2cache = "2MB";
  31. cpu-tlb = "1024 4-ways";
  32. cpu-cacheline = "64Bytes";
  33. cpu-vector = "0.7.1";
  34. cpu0_intc: interrupt-controller {
  35. #interrupt-cells = <1>;
  36. compatible = "riscv,cpu-intc";
  37. interrupt-controller;
  38. };
  39. };
  40. cpu@1 {
  41. device_type = "cpu";
  42. reg = <1>;
  43. status = "okay";
  44. compatible = "riscv";
  45. riscv,isa = "rv64imafdcsu";
  46. mmu-type = "riscv,sv39";
  47. cpu-freq = "1.2Ghz";
  48. cpu-icache = "64KB";
  49. cpu-dcache = "64KB";
  50. cpu-l2cache = "2MB";
  51. cpu-tlb = "1024 4-ways";
  52. cpu-cacheline = "64Bytes";
  53. cpu-vector = "0.7.1";
  54. cpu1_intc: interrupt-controller {
  55. #interrupt-cells = <1>;
  56. compatible = "riscv,cpu-intc";
  57. interrupt-controller;
  58. };
  59. };
  60. };
  61. soc {
  62. #address-cells = <2>;
  63. #size-cells = <2>;
  64. compatible = "simple-bus";
  65. ranges;
  66. reset: reset-sample {
  67. compatible = "thead,reset-sample";
  68. plic-delegate = <0x3 0xf01ffffc>;
  69. using-csr-reset;
  70. csr-copy = <
  71. 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc
  72. 0x3b0 0x3b1 0x3b2 0x3b3
  73. 0x3b4 0x3b5 0x3b6 0x3b7
  74. 0x3a0
  75. >;
  76. };
  77. clint0: clint@3f4000000 {
  78. compatible = "riscv,clint0";
  79. interrupts-extended = <
  80. &cpu0_intc 3 &cpu0_intc 7
  81. &cpu1_intc 3 &cpu1_intc 7
  82. >;
  83. reg = <0x3 0xf4000000 0x0 0x04000000>;
  84. clint,has-no-64bit-mmio;
  85. };
  86. intc: interrupt-controller@3f0000000 {
  87. #interrupt-cells = <1>;
  88. compatible = "riscv,plic0";
  89. interrupt-controller;
  90. interrupts-extended = <
  91. &cpu0_intc 0xffffffff &cpu0_intc 9
  92. &cpu1_intc 0xffffffff &cpu1_intc 9
  93. >;
  94. reg = <0x3 0xf0000000 0x0 0x04000000>;
  95. reg-names = "control";
  96. riscv,max-priority = <7>;
  97. riscv,ndev = <80>;
  98. };
  99. dummy_apb: apb-clock {
  100. compatible = "fixed-clock";
  101. clock-frequency = <62500000>;
  102. clock-output-names = "dummy_apb";
  103. #clock-cells = <0>;
  104. };
  105. dummy_ahb: ahb-clock {
  106. compatible = "fixed-clock";
  107. clock-frequency = <250000000>;
  108. clock-output-names = "dummy_ahb";
  109. #clock-cells = <0>;
  110. };
  111. dummy_axi: axi-clock {
  112. compatible = "fixed-clock";
  113. clock-frequency = <500000000>;
  114. clock-output-names = "dummy_axi";
  115. #clock-cells = <0>;
  116. };
  117. dummy_gmac: gmac-clock {
  118. compatible = "fixed-clock";
  119. clock-frequency = <1000000000>;
  120. clock-output-names = "dummy_gmac";
  121. #clock-cells = <0>;
  122. };
  123. dummy_clk_sdio: dummy-clk-sdio {
  124. compatible = "fixed-clock";
  125. clock-frequency = <150000000>;
  126. clock-output-names = "dummy_clk_sdio";
  127. #clock-cells = <0>;
  128. };
  129. usb: dwc3@3fff10000 {
  130. compatible = "snps,dwc3";
  131. reg = <0x3 0xfff10000 0x0 0x10000>;
  132. interrupt-parent = <&intc>;
  133. interrupts = <44>;
  134. clocks = <&dummy_ahb>, <&dummy_ahb>, <&dummy_ahb>;
  135. clock-names = "ref", "bus_early", "suspend";
  136. maximum-speed = "super-speed";
  137. dr_mode = "peripheral";
  138. snps,usb3_lpm_capable;
  139. snps,dis_u3_susphy_quirk;
  140. };
  141. gpio0: gpio@3fff71000 {
  142. compatible = "snps,dw-apb-gpio";
  143. reg = <0x3 0xfff71000 0x0 0x1000>;
  144. #address-cells = <1>;
  145. #size-cells = <0>;
  146. /* GPIO0[0-31] */
  147. gpio0_porta: gpio0-controller@0 {
  148. compatible = "snps,dw-apb-gpio-port";
  149. gpio-controller;
  150. #gpio-cells = <2>;
  151. snps,nr-gpios = <32>;
  152. reg = <0>;
  153. interrupt-controller;
  154. #interrupt-cells = <2>;
  155. interrupt-parent = <&intc>;
  156. interrupts = <27>;
  157. };
  158. /* GPIO0[32-63] */
  159. gpio0_portb: gpio0-controller@1 {
  160. compatible = "snps,dw-apb-gpio-port";
  161. gpio-controller;
  162. #gpio-cells = <2>;
  163. snps,nr-gpios = <32>;
  164. reg = <1>;
  165. };
  166. };
  167. gpio1: gpio@3fff72000 {
  168. compatible = "snps,dw-apb-gpio";
  169. reg = <0x3 0xfff72000 0x0 0x1000>;
  170. #address-cells = <1>;
  171. #size-cells = <0>;
  172. /* GPIO1[0-31] */
  173. gpio1_porta: gpio1-controller@0 {
  174. compatible = "snps,dw-apb-gpio-port";
  175. gpio-controller;
  176. #gpio-cells = <2>;
  177. snps,nr-gpios = <32>;
  178. reg = <0>;
  179. };
  180. /* GPIO1[32-63] */
  181. gpio1_portb: gpio1-controller@1 {
  182. compatible = "snps,dw-apb-gpio-port";
  183. gpio-controller;
  184. #gpio-cells = <2>;
  185. snps,nr-gpios = <32>;
  186. reg = <1>;
  187. };
  188. /* GPIO1[64-95] */
  189. gpio1_portc: gpio1-controller@2 {
  190. compatible = "snps,dw-apb-gpio-port";
  191. gpio-controller;
  192. #gpio-cells = <2>;
  193. snps,nr-gpios = <32>;
  194. reg = <2>;
  195. };
  196. };
  197. gpio-leds {
  198. compatible = "gpio-leds";
  199. led0 { /* GPIO0[11] - UART2_TXD */
  200. label = "led0";
  201. gpios = <&gpio0_porta 11 1>;
  202. default-state = "off";
  203. };
  204. };
  205. gpio-keys {
  206. compatible = "gpio-keys";
  207. /* autorepeat; */
  208. key_0 { /* GPIO0[10] - UART2_RXD */
  209. gpios = <&gpio0_porta 10 1>;
  210. linux,code = <59>;
  211. label = "key_0";
  212. };
  213. };
  214. i2c@3fff74000 {
  215. #address-cells = <1>;
  216. #size-cells = <0>;
  217. compatible = "snps,designware-i2c-ice";
  218. reg = <0x3 0xfff74000 0x0 0x1000>;
  219. interrupts = <21>;
  220. interrupt-parent = <&intc>;
  221. clocks = <&dummy_apb>;
  222. clock-frequency = <400000>;
  223. eeprom@50 {
  224. compatible = "atmel,24c64";
  225. reg = <0x50>;
  226. pagesize = <32>;
  227. };
  228. goodix_ts@14 {
  229. #gpio-cells = <2>;
  230. compatible = "goodix,gt917s";
  231. reg = <0x14>;
  232. interrupt-parent = <&gpio0_porta>;
  233. interrupts = <31 0>;
  234. irq-gpios = <&gpio0_porta 31 0>;
  235. reset-gpios = <&gpio0_porta 30 0>;
  236. touchscreen-size-x = <720>;
  237. touchscreen-size-y = <1280>;
  238. };
  239. };
  240. serial@3fff73000 {
  241. compatible = "snps,dw-apb-uart";
  242. reg = <0x3 0xfff73000 0x0 0x400>;
  243. interrupt-parent = <&intc>;
  244. interrupts = <23>;
  245. clocks = <&dummy_apb>;
  246. clock-names = "baudclk";
  247. reg-shift = <2>;
  248. reg-io-width = <4>;
  249. };
  250. pmu: pmu {
  251. interrupt-parent = <&cpu0_intc>;
  252. interrupts = <17>;
  253. compatible = "riscv,c910_pmu";
  254. };
  255. dmac0: dmac@3fffd0000 {
  256. compatible = "snps,axi-dma-1.01a";
  257. reg = <0x3 0xfffd0000 0x0 0x1000>;
  258. interrupt-parent = <&intc>;
  259. interrupts = <65>;
  260. clocks = <&dummy_axi>, <&dummy_ahb>;
  261. clock-names = "core-clk", "cfgr-clk";
  262. dma-channels = <8>;
  263. snps,block-size = <65536 65536 65536 65536 65536 65536 65536 65536>;
  264. snps,priority = <0 1 2 3 4 5 6 7>;
  265. snps,dma-masters = <1>;
  266. snps,data-width = <4>;
  267. snps,axi-max-burst-len = <16>;
  268. status = "disabled";
  269. };
  270. sdhc0: sdhc0@3fffb0000 {
  271. compatible = "snps,dw-mshc";
  272. reg = <0x3 0xfffb0000 0x0 0x1000>;
  273. interrupt-parent = <&intc>;
  274. interrupts = <37>;
  275. clocks = <&dummy_clk_sdio>, <&dummy_clk_sdio>;
  276. clock-names = "ciu", "biu";
  277. num-slots = <1>;
  278. card-detect-delay = <200>;
  279. cap-mmc-highspeed;
  280. cap-cmd23;
  281. non-removable;
  282. bus-width = <8>;
  283. };
  284. sdhc1: sdhc1@3fffa0000 {
  285. compatible = "snps,dw-mshc";
  286. reg = <0x3 0xfffa0000 0x0 0x1000>;
  287. interrupt-parent = <&intc>;
  288. interrupts = <38>;
  289. clocks = <&dummy_clk_sdio>, <&dummy_clk_sdio>;
  290. clock-names = "ciu", "biu";
  291. num-slots = <1>;
  292. card-detect-delay = <200>;
  293. cap-sd-highspeed;
  294. bus-width = <4>;
  295. };
  296. stmmac_axi_setup: stmmac-axi-config {
  297. snps,wr_osr_lmt = <3>;
  298. snps,rd_osr_lmt = <3>;
  299. snps,blen = <16 8 4 0 0 0 0>;
  300. };
  301. gmac: ethernet@3fffc0000 {
  302. compatible = "thead,dwmac";
  303. reg = < 0x3 0xfffc0000 0x0 0x2000
  304. 0x3 0xfe83025c 0x0 0x4
  305. 0x3 0xfe83031c 0x0 0x4
  306. 0x3 0xfff770c0 0x0 0x1c>;
  307. reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg";
  308. interrupt-parent = <&intc>;
  309. interrupts = <40>;
  310. interrupt-names = "macirq";
  311. clocks = <&dummy_ahb>, <&dummy_gmac>;
  312. clock-names = "stmmaceth", "gmac_pll_clk";
  313. snps,pbl = <32>;
  314. snps,fixed-burst;
  315. snps,axi-config = <&stmmac_axi_setup>;
  316. phy-mode = "rgmii-id";
  317. rx-clk-delay = <0x1f>; /* for RGMII */
  318. tx-clk-delay = <0x1f>; /* for RGMII */
  319. phy-handle = <&eth_phy_0>;
  320. mdio0 {
  321. #address-cells = <1>;
  322. #size-cells = <0>;
  323. compatible = "snps,dwmac-mdio";
  324. eth_phy_0: ethernet-phy@0 {
  325. reg = <0>;
  326. };
  327. };
  328. };
  329. gpu: gpu@3fff27000 {
  330. compatible = "verisilicon,gc8000ul";
  331. reg = <0x3 0xfff27000 0x0 0x1000>;
  332. interrupt-parent = <&intc>;
  333. interrupts = <63>;
  334. contiguous-base = <0x0 0xe0000000>;
  335. contiguous-size = <0x0 0x20000000>;
  336. };
  337. watchdog: watchdog@3fffe3000 {
  338. compatible = "ice,ice-wdt";
  339. reg = <0x3 0xfffe3000 0x0 0x1000>;
  340. interrupts = <20>;
  341. };
  342. dpu: dpu@3fff28000 {
  343. compatible = "verisilicon,dc8000-fb";
  344. reg = <0x3 0xfff28000 0x0 0x8000>;
  345. interrupt-parent = <&intc>;
  346. interrupts = <64>;
  347. };
  348. };
  349. chosen {
  350. /* bootargs = "console=ttyS0,115200 crashkernel=256M-:128M c910_mmu_v1"; */
  351. /* linux,initrd-start = <0x2000000>; */
  352. /* linux,initrd-end = <0x17000000>; */
  353. bootargs = "console=ttyS0,115200 rdinit=/sbin/init root=/dev/mmcblk0p4 rw rootfstype=ext4 blkdevparts=mmcblk0:2M(table),2M(dtb),60M(kernel),-(rootfs) clk_ignore_unused loglevel=7 rootwait crashkernel=256M-:128M c910_mmu_v1";
  354. stdout-path = "serial0@3fff73000:115200";
  355. };
  356. };