pinctl.rst 50 KB

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  1. ===============================
  2. PINCTRL (PIN CONTROL) subsystem
  3. ===============================
  4. This document outlines the pin control subsystem in Linux
  5. This subsystem deals with:
  6. - Enumerating and naming controllable pins
  7. - Multiplexing of pins, pads, fingers (etc) see below for details
  8. - Configuration of pins, pads, fingers (etc), such as software-controlled
  9. biasing and driving mode specific pins, such as pull-up/down, open drain,
  10. load capacitance etc.
  11. Top-level interface
  12. ===================
  13. Definition of PIN CONTROLLER:
  14. - A pin controller is a piece of hardware, usually a set of registers, that
  15. can control PINs. It may be able to multiplex, bias, set load capacitance,
  16. set drive strength, etc. for individual pins or groups of pins.
  17. Definition of PIN:
  18. - PINS are equal to pads, fingers, balls or whatever packaging input or
  19. output line you want to control and these are denoted by unsigned integers
  20. in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
  21. there may be several such number spaces in a system. This pin space may
  22. be sparse - i.e. there may be gaps in the space with numbers where no
  23. pin exists.
  24. When a PIN CONTROLLER is instantiated, it will register a descriptor to the
  25. pin control framework, and this descriptor contains an array of pin descriptors
  26. describing the pins handled by this specific pin controller.
  27. Here is an example of a PGA (Pin Grid Array) chip seen from underneath::
  28. A B C D E F G H
  29. 8 o o o o o o o o
  30. 7 o o o o o o o o
  31. 6 o o o o o o o o
  32. 5 o o o o o o o o
  33. 4 o o o o o o o o
  34. 3 o o o o o o o o
  35. 2 o o o o o o o o
  36. 1 o o o o o o o o
  37. To register a pin controller and name all the pins on this package we can do
  38. this in our driver::
  39. #include <linux/pinctrl/pinctrl.h>
  40. const struct pinctrl_pin_desc foo_pins[] = {
  41. PINCTRL_PIN(0, "A8"),
  42. PINCTRL_PIN(1, "B8"),
  43. PINCTRL_PIN(2, "C8"),
  44. ...
  45. PINCTRL_PIN(61, "F1"),
  46. PINCTRL_PIN(62, "G1"),
  47. PINCTRL_PIN(63, "H1"),
  48. };
  49. static struct pinctrl_desc foo_desc = {
  50. .name = "foo",
  51. .pins = foo_pins,
  52. .npins = ARRAY_SIZE(foo_pins),
  53. .owner = THIS_MODULE,
  54. };
  55. int __init foo_probe(void)
  56. {
  57. int error;
  58. struct pinctrl_dev *pctl;
  59. error = pinctrl_register_and_init(&foo_desc, <PARENT>,
  60. NULL, &pctl);
  61. if (error)
  62. return error;
  63. return pinctrl_enable(pctl);
  64. }
  65. To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and
  66. selected drivers, you need to select them from your machine's Kconfig entry,
  67. since these are so tightly integrated with the machines they are used on.
  68. See for example arch/arm/mach-u300/Kconfig for an example.
  69. Pins usually have fancier names than this. You can find these in the datasheet
  70. for your chip. Notice that the core pinctrl.h file provides a fancy macro
  71. called PINCTRL_PIN() to create the struct entries. As you can see I enumerated
  72. the pins from 0 in the upper left corner to 63 in the lower right corner.
  73. This enumeration was arbitrarily chosen, in practice you need to think
  74. through your numbering system so that it matches the layout of registers
  75. and such things in your driver, or the code may become complicated. You must
  76. also consider matching of offsets to the GPIO ranges that may be handled by
  77. the pin controller.
  78. For a padring with 467 pads, as opposed to actual pins, I used an enumeration
  79. like this, walking around the edge of the chip, which seems to be industry
  80. standard too (all these pads had names, too)::
  81. 0 ..... 104
  82. 466 105
  83. . .
  84. . .
  85. 358 224
  86. 357 .... 225
  87. Pin groups
  88. ==========
  89. Many controllers need to deal with groups of pins, so the pin controller
  90. subsystem has a mechanism for enumerating groups of pins and retrieving the
  91. actual enumerated pins that are part of a certain group.
  92. For example, say that we have a group of pins dealing with an SPI interface
  93. on { 0, 8, 16, 24 }, and a group of pins dealing with an I2C interface on pins
  94. on { 24, 25 }.
  95. These two groups are presented to the pin control subsystem by implementing
  96. some generic pinctrl_ops like this::
  97. #include <linux/pinctrl/pinctrl.h>
  98. struct foo_group {
  99. const char *name;
  100. const unsigned int *pins;
  101. const unsigned num_pins;
  102. };
  103. static const unsigned int spi0_pins[] = { 0, 8, 16, 24 };
  104. static const unsigned int i2c0_pins[] = { 24, 25 };
  105. static const struct foo_group foo_groups[] = {
  106. {
  107. .name = "spi0_grp",
  108. .pins = spi0_pins,
  109. .num_pins = ARRAY_SIZE(spi0_pins),
  110. },
  111. {
  112. .name = "i2c0_grp",
  113. .pins = i2c0_pins,
  114. .num_pins = ARRAY_SIZE(i2c0_pins),
  115. },
  116. };
  117. static int foo_get_groups_count(struct pinctrl_dev *pctldev)
  118. {
  119. return ARRAY_SIZE(foo_groups);
  120. }
  121. static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
  122. unsigned selector)
  123. {
  124. return foo_groups[selector].name;
  125. }
  126. static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
  127. const unsigned **pins,
  128. unsigned *num_pins)
  129. {
  130. *pins = (unsigned *) foo_groups[selector].pins;
  131. *num_pins = foo_groups[selector].num_pins;
  132. return 0;
  133. }
  134. static struct pinctrl_ops foo_pctrl_ops = {
  135. .get_groups_count = foo_get_groups_count,
  136. .get_group_name = foo_get_group_name,
  137. .get_group_pins = foo_get_group_pins,
  138. };
  139. static struct pinctrl_desc foo_desc = {
  140. ...
  141. .pctlops = &foo_pctrl_ops,
  142. };
  143. The pin control subsystem will call the .get_groups_count() function to
  144. determine the total number of legal selectors, then it will call the other functions
  145. to retrieve the name and pins of the group. Maintaining the data structure of
  146. the groups is up to the driver, this is just a simple example - in practice you
  147. may need more entries in your group structure, for example specific register
  148. ranges associated with each group and so on.
  149. Pin configuration
  150. =================
  151. Pins can sometimes be software-configured in various ways, mostly related
  152. to their electronic properties when used as inputs or outputs. For example you
  153. may be able to make an output pin high impedance, or "tristate" meaning it is
  154. effectively disconnected. You may be able to connect an input pin to VDD or GND
  155. using a certain resistor value - pull up and pull down - so that the pin has a
  156. stable value when nothing is driving the rail it is connected to, or when it's
  157. unconnected.
  158. Pin configuration can be programmed by adding configuration entries into the
  159. mapping table; see section "Board/machine configuration" below.
  160. The format and meaning of the configuration parameter, PLATFORM_X_PULL_UP
  161. above, is entirely defined by the pin controller driver.
  162. The pin configuration driver implements callbacks for changing pin
  163. configuration in the pin controller ops like this::
  164. #include <linux/pinctrl/pinctrl.h>
  165. #include <linux/pinctrl/pinconf.h>
  166. #include "platform_x_pindefs.h"
  167. static int foo_pin_config_get(struct pinctrl_dev *pctldev,
  168. unsigned offset,
  169. unsigned long *config)
  170. {
  171. struct my_conftype conf;
  172. ... Find setting for pin @ offset ...
  173. *config = (unsigned long) conf;
  174. }
  175. static int foo_pin_config_set(struct pinctrl_dev *pctldev,
  176. unsigned offset,
  177. unsigned long config)
  178. {
  179. struct my_conftype *conf = (struct my_conftype *) config;
  180. switch (conf) {
  181. case PLATFORM_X_PULL_UP:
  182. ...
  183. }
  184. }
  185. }
  186. static int foo_pin_config_group_get (struct pinctrl_dev *pctldev,
  187. unsigned selector,
  188. unsigned long *config)
  189. {
  190. ...
  191. }
  192. static int foo_pin_config_group_set (struct pinctrl_dev *pctldev,
  193. unsigned selector,
  194. unsigned long config)
  195. {
  196. ...
  197. }
  198. static struct pinconf_ops foo_pconf_ops = {
  199. .pin_config_get = foo_pin_config_get,
  200. .pin_config_set = foo_pin_config_set,
  201. .pin_config_group_get = foo_pin_config_group_get,
  202. .pin_config_group_set = foo_pin_config_group_set,
  203. };
  204. /* Pin config operations are handled by some pin controller */
  205. static struct pinctrl_desc foo_desc = {
  206. ...
  207. .confops = &foo_pconf_ops,
  208. };
  209. Interaction with the GPIO subsystem
  210. ===================================
  211. The GPIO drivers may want to perform operations of various types on the same
  212. physical pins that are also registered as pin controller pins.
  213. First and foremost, the two subsystems can be used as completely orthogonal,
  214. see the section named "pin control requests from drivers" and
  215. "drivers needing both pin control and GPIOs" below for details. But in some
  216. situations a cross-subsystem mapping between pins and GPIOs is needed.
  217. Since the pin controller subsystem has its pinspace local to the pin controller
  218. we need a mapping so that the pin control subsystem can figure out which pin
  219. controller handles control of a certain GPIO pin. Since a single pin controller
  220. may be muxing several GPIO ranges (typically SoCs that have one set of pins,
  221. but internally several GPIO silicon blocks, each modelled as a struct
  222. gpio_chip) any number of GPIO ranges can be added to a pin controller instance
  223. like this::
  224. struct gpio_chip chip_a;
  225. struct gpio_chip chip_b;
  226. static struct pinctrl_gpio_range gpio_range_a = {
  227. .name = "chip a",
  228. .id = 0,
  229. .base = 32,
  230. .pin_base = 32,
  231. .npins = 16,
  232. .gc = &chip_a;
  233. };
  234. static struct pinctrl_gpio_range gpio_range_b = {
  235. .name = "chip b",
  236. .id = 0,
  237. .base = 48,
  238. .pin_base = 64,
  239. .npins = 8,
  240. .gc = &chip_b;
  241. };
  242. {
  243. struct pinctrl_dev *pctl;
  244. ...
  245. pinctrl_add_gpio_range(pctl, &gpio_range_a);
  246. pinctrl_add_gpio_range(pctl, &gpio_range_b);
  247. }
  248. So this complex system has one pin controller handling two different
  249. GPIO chips. "chip a" has 16 pins and "chip b" has 8 pins. The "chip a" and
  250. "chip b" have different .pin_base, which means a start pin number of the
  251. GPIO range.
  252. The GPIO range of "chip a" starts from the GPIO base of 32 and actual
  253. pin range also starts from 32. However "chip b" has different starting
  254. offset for the GPIO range and pin range. The GPIO range of "chip b" starts
  255. from GPIO number 48, while the pin range of "chip b" starts from 64.
  256. We can convert a gpio number to actual pin number using this "pin_base".
  257. They are mapped in the global GPIO pin space at:
  258. chip a:
  259. - GPIO range : [32 .. 47]
  260. - pin range : [32 .. 47]
  261. chip b:
  262. - GPIO range : [48 .. 55]
  263. - pin range : [64 .. 71]
  264. The above examples assume the mapping between the GPIOs and pins is
  265. linear. If the mapping is sparse or haphazard, an array of arbitrary pin
  266. numbers can be encoded in the range like this::
  267. static const unsigned range_pins[] = { 14, 1, 22, 17, 10, 8, 6, 2 };
  268. static struct pinctrl_gpio_range gpio_range = {
  269. .name = "chip",
  270. .id = 0,
  271. .base = 32,
  272. .pins = &range_pins,
  273. .npins = ARRAY_SIZE(range_pins),
  274. .gc = &chip;
  275. };
  276. In this case the pin_base property will be ignored. If the name of a pin
  277. group is known, the pins and npins elements of the above structure can be
  278. initialised using the function pinctrl_get_group_pins(), e.g. for pin
  279. group "foo"::
  280. pinctrl_get_group_pins(pctl, "foo", &gpio_range.pins,
  281. &gpio_range.npins);
  282. When GPIO-specific functions in the pin control subsystem are called, these
  283. ranges will be used to look up the appropriate pin controller by inspecting
  284. and matching the pin to the pin ranges across all controllers. When a
  285. pin controller handling the matching range is found, GPIO-specific functions
  286. will be called on that specific pin controller.
  287. For all functionalities dealing with pin biasing, pin muxing etc, the pin
  288. controller subsystem will look up the corresponding pin number from the passed
  289. in gpio number, and use the range's internals to retrieve a pin number. After
  290. that, the subsystem passes it on to the pin control driver, so the driver
  291. will get a pin number into its handled number range. Further it is also passed
  292. the range ID value, so that the pin controller knows which range it should
  293. deal with.
  294. Calling pinctrl_add_gpio_range from pinctrl driver is DEPRECATED. Please see
  295. section 2.1 of Documentation/devicetree/bindings/gpio/gpio.txt on how to bind
  296. pinctrl and gpio drivers.
  297. PINMUX interfaces
  298. =================
  299. These calls use the pinmux_* naming prefix. No other calls should use that
  300. prefix.
  301. What is pinmuxing?
  302. ==================
  303. PINMUX, also known as padmux, ballmux, alternate functions or mission modes
  304. is a way for chip vendors producing some kind of electrical packages to use
  305. a certain physical pin (ball, pad, finger, etc) for multiple mutually exclusive
  306. functions, depending on the application. By "application" in this context
  307. we usually mean a way of soldering or wiring the package into an electronic
  308. system, even though the framework makes it possible to also change the function
  309. at runtime.
  310. Here is an example of a PGA (Pin Grid Array) chip seen from underneath::
  311. A B C D E F G H
  312. +---+
  313. 8 | o | o o o o o o o
  314. | |
  315. 7 | o | o o o o o o o
  316. | |
  317. 6 | o | o o o o o o o
  318. +---+---+
  319. 5 | o | o | o o o o o o
  320. +---+---+ +---+
  321. 4 o o o o o o | o | o
  322. | |
  323. 3 o o o o o o | o | o
  324. | |
  325. 2 o o o o o o | o | o
  326. +-------+-------+-------+---+---+
  327. 1 | o o | o o | o o | o | o |
  328. +-------+-------+-------+---+---+
  329. This is not tetris. The game to think of is chess. Not all PGA/BGA packages
  330. are chessboard-like, big ones have "holes" in some arrangement according to
  331. different design patterns, but we're using this as a simple example. Of the
  332. pins you see some will be taken by things like a few VCC and GND to feed power
  333. to the chip, and quite a few will be taken by large ports like an external
  334. memory interface. The remaining pins will often be subject to pin multiplexing.
  335. The example 8x8 PGA package above will have pin numbers 0 through 63 assigned
  336. to its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using
  337. pinctrl_register_pins() and a suitable data set as shown earlier.
  338. In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port
  339. (these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as
  340. some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can
  341. be used as an I2C port (these are just two pins: SCL, SDA). Needless to say,
  342. we cannot use the SPI port and I2C port at the same time. However in the inside
  343. of the package the silicon performing the SPI logic can alternatively be routed
  344. out on pins { G4, G3, G2, G1 }.
  345. On the bottom row at { A1, B1, C1, D1, E1, F1, G1, H1 } we have something
  346. special - it's an external MMC bus that can be 2, 4 or 8 bits wide, and it will
  347. consume 2, 4 or 8 pins respectively, so either { A1, B1 } are taken or
  348. { A1, B1, C1, D1 } or all of them. If we use all 8 bits, we cannot use the SPI
  349. port on pins { G4, G3, G2, G1 } of course.
  350. This way the silicon blocks present inside the chip can be multiplexed "muxed"
  351. out on different pin ranges. Often contemporary SoC (systems on chip) will
  352. contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to
  353. different pins by pinmux settings.
  354. Since general-purpose I/O pins (GPIO) are typically always in shortage, it is
  355. common to be able to use almost any pin as a GPIO pin if it is not currently
  356. in use by some other I/O port.
  357. Pinmux conventions
  358. ==================
  359. The purpose of the pinmux functionality in the pin controller subsystem is to
  360. abstract and provide pinmux settings to the devices you choose to instantiate
  361. in your machine configuration. It is inspired by the clk, GPIO and regulator
  362. subsystems, so devices will request their mux setting, but it's also possible
  363. to request a single pin for e.g. GPIO.
  364. Definitions:
  365. - FUNCTIONS can be switched in and out by a driver residing with the pin
  366. control subsystem in the drivers/pinctrl/* directory of the kernel. The
  367. pin control driver knows the possible functions. In the example above you can
  368. identify three pinmux functions, one for spi, one for i2c and one for mmc.
  369. - FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array.
  370. In this case the array could be something like: { spi0, i2c0, mmc0 }
  371. for the three available functions.
  372. - FUNCTIONS have PIN GROUPS as defined on the generic level - so a certain
  373. function is *always* associated with a certain set of pin groups, could
  374. be just a single one, but could also be many. In the example above the
  375. function i2c is associated with the pins { A5, B5 }, enumerated as
  376. { 24, 25 } in the controller pin space.
  377. The Function spi is associated with pin groups { A8, A7, A6, A5 }
  378. and { G4, G3, G2, G1 }, which are enumerated as { 0, 8, 16, 24 } and
  379. { 38, 46, 54, 62 } respectively.
  380. Group names must be unique per pin controller, no two groups on the same
  381. controller may have the same name.
  382. - The combination of a FUNCTION and a PIN GROUP determine a certain function
  383. for a certain set of pins. The knowledge of the functions and pin groups
  384. and their machine-specific particulars are kept inside the pinmux driver,
  385. from the outside only the enumerators are known, and the driver core can
  386. request:
  387. - The name of a function with a certain selector (>= 0)
  388. - A list of groups associated with a certain function
  389. - That a certain group in that list to be activated for a certain function
  390. As already described above, pin groups are in turn self-descriptive, so
  391. the core will retrieve the actual pin range in a certain group from the
  392. driver.
  393. - FUNCTIONS and GROUPS on a certain PIN CONTROLLER are MAPPED to a certain
  394. device by the board file, device tree or similar machine setup configuration
  395. mechanism, similar to how regulators are connected to devices, usually by
  396. name. Defining a pin controller, function and group thus uniquely identify
  397. the set of pins to be used by a certain device. (If only one possible group
  398. of pins is available for the function, no group name need to be supplied -
  399. the core will simply select the first and only group available.)
  400. In the example case we can define that this particular machine shall
  401. use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function
  402. fi2c0 group gi2c0, on the primary pin controller, we get mappings
  403. like these::
  404. {
  405. {"map-spi0", spi0, pinctrl0, fspi0, gspi0},
  406. {"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0}
  407. }
  408. Every map must be assigned a state name, pin controller, device and
  409. function. The group is not compulsory - if it is omitted the first group
  410. presented by the driver as applicable for the function will be selected,
  411. which is useful for simple cases.
  412. It is possible to map several groups to the same combination of device,
  413. pin controller and function. This is for cases where a certain function on
  414. a certain pin controller may use different sets of pins in different
  415. configurations.
  416. - PINS for a certain FUNCTION using a certain PIN GROUP on a certain
  417. PIN CONTROLLER are provided on a first-come first-serve basis, so if some
  418. other device mux setting or GPIO pin request has already taken your physical
  419. pin, you will be denied the use of it. To get (activate) a new setting, the
  420. old one has to be put (deactivated) first.
  421. Sometimes the documentation and hardware registers will be oriented around
  422. pads (or "fingers") rather than pins - these are the soldering surfaces on the
  423. silicon inside the package, and may or may not match the actual number of
  424. pins/balls underneath the capsule. Pick some enumeration that makes sense to
  425. you. Define enumerators only for the pins you can control if that makes sense.
  426. Assumptions:
  427. We assume that the number of possible function maps to pin groups is limited by
  428. the hardware. I.e. we assume that there is no system where any function can be
  429. mapped to any pin, like in a phone exchange. So the available pin groups for
  430. a certain function will be limited to a few choices (say up to eight or so),
  431. not hundreds or any amount of choices. This is the characteristic we have found
  432. by inspecting available pinmux hardware, and a necessary assumption since we
  433. expect pinmux drivers to present *all* possible function vs pin group mappings
  434. to the subsystem.
  435. Pinmux drivers
  436. ==============
  437. The pinmux core takes care of preventing conflicts on pins and calling
  438. the pin controller driver to execute different settings.
  439. It is the responsibility of the pinmux driver to impose further restrictions
  440. (say for example infer electronic limitations due to load, etc.) to determine
  441. whether or not the requested function can actually be allowed, and in case it
  442. is possible to perform the requested mux setting, poke the hardware so that
  443. this happens.
  444. Pinmux drivers are required to supply a few callback functions, some are
  445. optional. Usually the set_mux() function is implemented, writing values into
  446. some certain registers to activate a certain mux setting for a certain pin.
  447. A simple driver for the above example will work by setting bits 0, 1, 2, 3 or 4
  448. into some register named MUX to select a certain function with a certain
  449. group of pins would work something like this::
  450. #include <linux/pinctrl/pinctrl.h>
  451. #include <linux/pinctrl/pinmux.h>
  452. struct foo_group {
  453. const char *name;
  454. const unsigned int *pins;
  455. const unsigned num_pins;
  456. };
  457. static const unsigned spi0_0_pins[] = { 0, 8, 16, 24 };
  458. static const unsigned spi0_1_pins[] = { 38, 46, 54, 62 };
  459. static const unsigned i2c0_pins[] = { 24, 25 };
  460. static const unsigned mmc0_1_pins[] = { 56, 57 };
  461. static const unsigned mmc0_2_pins[] = { 58, 59 };
  462. static const unsigned mmc0_3_pins[] = { 60, 61, 62, 63 };
  463. static const struct foo_group foo_groups[] = {
  464. {
  465. .name = "spi0_0_grp",
  466. .pins = spi0_0_pins,
  467. .num_pins = ARRAY_SIZE(spi0_0_pins),
  468. },
  469. {
  470. .name = "spi0_1_grp",
  471. .pins = spi0_1_pins,
  472. .num_pins = ARRAY_SIZE(spi0_1_pins),
  473. },
  474. {
  475. .name = "i2c0_grp",
  476. .pins = i2c0_pins,
  477. .num_pins = ARRAY_SIZE(i2c0_pins),
  478. },
  479. {
  480. .name = "mmc0_1_grp",
  481. .pins = mmc0_1_pins,
  482. .num_pins = ARRAY_SIZE(mmc0_1_pins),
  483. },
  484. {
  485. .name = "mmc0_2_grp",
  486. .pins = mmc0_2_pins,
  487. .num_pins = ARRAY_SIZE(mmc0_2_pins),
  488. },
  489. {
  490. .name = "mmc0_3_grp",
  491. .pins = mmc0_3_pins,
  492. .num_pins = ARRAY_SIZE(mmc0_3_pins),
  493. },
  494. };
  495. static int foo_get_groups_count(struct pinctrl_dev *pctldev)
  496. {
  497. return ARRAY_SIZE(foo_groups);
  498. }
  499. static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
  500. unsigned selector)
  501. {
  502. return foo_groups[selector].name;
  503. }
  504. static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
  505. const unsigned ** pins,
  506. unsigned * num_pins)
  507. {
  508. *pins = (unsigned *) foo_groups[selector].pins;
  509. *num_pins = foo_groups[selector].num_pins;
  510. return 0;
  511. }
  512. static struct pinctrl_ops foo_pctrl_ops = {
  513. .get_groups_count = foo_get_groups_count,
  514. .get_group_name = foo_get_group_name,
  515. .get_group_pins = foo_get_group_pins,
  516. };
  517. struct foo_pmx_func {
  518. const char *name;
  519. const char * const *groups;
  520. const unsigned num_groups;
  521. };
  522. static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
  523. static const char * const i2c0_groups[] = { "i2c0_grp" };
  524. static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp",
  525. "mmc0_3_grp" };
  526. static const struct foo_pmx_func foo_functions[] = {
  527. {
  528. .name = "spi0",
  529. .groups = spi0_groups,
  530. .num_groups = ARRAY_SIZE(spi0_groups),
  531. },
  532. {
  533. .name = "i2c0",
  534. .groups = i2c0_groups,
  535. .num_groups = ARRAY_SIZE(i2c0_groups),
  536. },
  537. {
  538. .name = "mmc0",
  539. .groups = mmc0_groups,
  540. .num_groups = ARRAY_SIZE(mmc0_groups),
  541. },
  542. };
  543. static int foo_get_functions_count(struct pinctrl_dev *pctldev)
  544. {
  545. return ARRAY_SIZE(foo_functions);
  546. }
  547. static const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
  548. {
  549. return foo_functions[selector].name;
  550. }
  551. static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
  552. const char * const **groups,
  553. unsigned * const num_groups)
  554. {
  555. *groups = foo_functions[selector].groups;
  556. *num_groups = foo_functions[selector].num_groups;
  557. return 0;
  558. }
  559. static int foo_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
  560. unsigned group)
  561. {
  562. u8 regbit = (1 << selector + group);
  563. writeb((readb(MUX)|regbit), MUX);
  564. return 0;
  565. }
  566. static struct pinmux_ops foo_pmxops = {
  567. .get_functions_count = foo_get_functions_count,
  568. .get_function_name = foo_get_fname,
  569. .get_function_groups = foo_get_groups,
  570. .set_mux = foo_set_mux,
  571. .strict = true,
  572. };
  573. /* Pinmux operations are handled by some pin controller */
  574. static struct pinctrl_desc foo_desc = {
  575. ...
  576. .pctlops = &foo_pctrl_ops,
  577. .pmxops = &foo_pmxops,
  578. };
  579. In the example activating muxing 0 and 1 at the same time setting bits
  580. 0 and 1, uses one pin in common so they would collide.
  581. The beauty of the pinmux subsystem is that since it keeps track of all
  582. pins and who is using them, it will already have denied an impossible
  583. request like that, so the driver does not need to worry about such
  584. things - when it gets a selector passed in, the pinmux subsystem makes
  585. sure no other device or GPIO assignment is already using the selected
  586. pins. Thus bits 0 and 1 in the control register will never be set at the
  587. same time.
  588. All the above functions are mandatory to implement for a pinmux driver.
  589. Pin control interaction with the GPIO subsystem
  590. ===============================================
  591. Note that the following implies that the use case is to use a certain pin
  592. from the Linux kernel using the API in <linux/gpio.h> with gpio_request()
  593. and similar functions. There are cases where you may be using something
  594. that your datasheet calls "GPIO mode", but actually is just an electrical
  595. configuration for a certain device. See the section below named
  596. "GPIO mode pitfalls" for more details on this scenario.
  597. The public pinmux API contains two functions named pinctrl_gpio_request()
  598. and pinctrl_gpio_free(). These two functions shall *ONLY* be called from
  599. gpiolib-based drivers as part of their gpio_request() and
  600. gpio_free() semantics. Likewise the pinctrl_gpio_direction_[input|output]
  601. shall only be called from within respective gpio_direction_[input|output]
  602. gpiolib implementation.
  603. NOTE that platforms and individual drivers shall *NOT* request GPIO pins to be
  604. controlled e.g. muxed in. Instead, implement a proper gpiolib driver and have
  605. that driver request proper muxing and other control for its pins.
  606. The function list could become long, especially if you can convert every
  607. individual pin into a GPIO pin independent of any other pins, and then try
  608. the approach to define every pin as a function.
  609. In this case, the function array would become 64 entries for each GPIO
  610. setting and then the device functions.
  611. For this reason there are two functions a pin control driver can implement
  612. to enable only GPIO on an individual pin: .gpio_request_enable() and
  613. .gpio_disable_free().
  614. This function will pass in the affected GPIO range identified by the pin
  615. controller core, so you know which GPIO pins are being affected by the request
  616. operation.
  617. If your driver needs to have an indication from the framework of whether the
  618. GPIO pin shall be used for input or output you can implement the
  619. .gpio_set_direction() function. As described this shall be called from the
  620. gpiolib driver and the affected GPIO range, pin offset and desired direction
  621. will be passed along to this function.
  622. Alternatively to using these special functions, it is fully allowed to use
  623. named functions for each GPIO pin, the pinctrl_gpio_request() will attempt to
  624. obtain the function "gpioN" where "N" is the global GPIO pin number if no
  625. special GPIO-handler is registered.
  626. GPIO mode pitfalls
  627. ==================
  628. Due to the naming conventions used by hardware engineers, where "GPIO"
  629. is taken to mean different things than what the kernel does, the developer
  630. may be confused by a datasheet talking about a pin being possible to set
  631. into "GPIO mode". It appears that what hardware engineers mean with
  632. "GPIO mode" is not necessarily the use case that is implied in the kernel
  633. interface <linux/gpio.h>: a pin that you grab from kernel code and then
  634. either listen for input or drive high/low to assert/deassert some
  635. external line.
  636. Rather hardware engineers think that "GPIO mode" means that you can
  637. software-control a few electrical properties of the pin that you would
  638. not be able to control if the pin was in some other mode, such as muxed in
  639. for a device.
  640. The GPIO portions of a pin and its relation to a certain pin controller
  641. configuration and muxing logic can be constructed in several ways. Here
  642. are two examples::
  643. (A)
  644. pin config
  645. logic regs
  646. | +- SPI
  647. Physical pins --- pad --- pinmux -+- I2C
  648. | +- mmc
  649. | +- GPIO
  650. pin
  651. multiplex
  652. logic regs
  653. Here some electrical properties of the pin can be configured no matter
  654. whether the pin is used for GPIO or not. If you multiplex a GPIO onto a
  655. pin, you can also drive it high/low from "GPIO" registers.
  656. Alternatively, the pin can be controlled by a certain peripheral, while
  657. still applying desired pin config properties. GPIO functionality is thus
  658. orthogonal to any other device using the pin.
  659. In this arrangement the registers for the GPIO portions of the pin controller,
  660. or the registers for the GPIO hardware module are likely to reside in a
  661. separate memory range only intended for GPIO driving, and the register
  662. range dealing with pin config and pin multiplexing get placed into a
  663. different memory range and a separate section of the data sheet.
  664. A flag "strict" in struct pinmux_ops is available to check and deny
  665. simultaneous access to the same pin from GPIO and pin multiplexing
  666. consumers on hardware of this type. The pinctrl driver should set this flag
  667. accordingly.
  668. ::
  669. (B)
  670. pin config
  671. logic regs
  672. | +- SPI
  673. Physical pins --- pad --- pinmux -+- I2C
  674. | | +- mmc
  675. | |
  676. GPIO pin
  677. multiplex
  678. logic regs
  679. In this arrangement, the GPIO functionality can always be enabled, such that
  680. e.g. a GPIO input can be used to "spy" on the SPI/I2C/MMC signal while it is
  681. pulsed out. It is likely possible to disrupt the traffic on the pin by doing
  682. wrong things on the GPIO block, as it is never really disconnected. It is
  683. possible that the GPIO, pin config and pin multiplex registers are placed into
  684. the same memory range and the same section of the data sheet, although that
  685. need not be the case.
  686. In some pin controllers, although the physical pins are designed in the same
  687. way as (B), the GPIO function still can't be enabled at the same time as the
  688. peripheral functions. So again the "strict" flag should be set, denying
  689. simultaneous activation by GPIO and other muxed in devices.
  690. From a kernel point of view, however, these are different aspects of the
  691. hardware and shall be put into different subsystems:
  692. - Registers (or fields within registers) that control electrical
  693. properties of the pin such as biasing and drive strength should be
  694. exposed through the pinctrl subsystem, as "pin configuration" settings.
  695. - Registers (or fields within registers) that control muxing of signals
  696. from various other HW blocks (e.g. I2C, MMC, or GPIO) onto pins should
  697. be exposed through the pinctrl subsystem, as mux functions.
  698. - Registers (or fields within registers) that control GPIO functionality
  699. such as setting a GPIO's output value, reading a GPIO's input value, or
  700. setting GPIO pin direction should be exposed through the GPIO subsystem,
  701. and if they also support interrupt capabilities, through the irqchip
  702. abstraction.
  703. Depending on the exact HW register design, some functions exposed by the
  704. GPIO subsystem may call into the pinctrl subsystem in order to
  705. co-ordinate register settings across HW modules. In particular, this may
  706. be needed for HW with separate GPIO and pin controller HW modules, where
  707. e.g. GPIO direction is determined by a register in the pin controller HW
  708. module rather than the GPIO HW module.
  709. Electrical properties of the pin such as biasing and drive strength
  710. may be placed at some pin-specific register in all cases or as part
  711. of the GPIO register in case (B) especially. This doesn't mean that such
  712. properties necessarily pertain to what the Linux kernel calls "GPIO".
  713. Example: a pin is usually muxed in to be used as a UART TX line. But during
  714. system sleep, we need to put this pin into "GPIO mode" and ground it.
  715. If you make a 1-to-1 map to the GPIO subsystem for this pin, you may start
  716. to think that you need to come up with something really complex, that the
  717. pin shall be used for UART TX and GPIO at the same time, that you will grab
  718. a pin control handle and set it to a certain state to enable UART TX to be
  719. muxed in, then twist it over to GPIO mode and use gpio_direction_output()
  720. to drive it low during sleep, then mux it over to UART TX again when you
  721. wake up and maybe even gpio_request/gpio_free as part of this cycle. This
  722. all gets very complicated.
  723. The solution is to not think that what the datasheet calls "GPIO mode"
  724. has to be handled by the <linux/gpio.h> interface. Instead view this as
  725. a certain pin config setting. Look in e.g. <linux/pinctrl/pinconf-generic.h>
  726. and you find this in the documentation:
  727. PIN_CONFIG_OUTPUT:
  728. this will configure the pin in output, use argument
  729. 1 to indicate high level, argument 0 to indicate low level.
  730. So it is perfectly possible to push a pin into "GPIO mode" and drive the
  731. line low as part of the usual pin control map. So for example your UART
  732. driver may look like this::
  733. #include <linux/pinctrl/consumer.h>
  734. struct pinctrl *pinctrl;
  735. struct pinctrl_state *pins_default;
  736. struct pinctrl_state *pins_sleep;
  737. pins_default = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_DEFAULT);
  738. pins_sleep = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_SLEEP);
  739. /* Normal mode */
  740. retval = pinctrl_select_state(pinctrl, pins_default);
  741. /* Sleep mode */
  742. retval = pinctrl_select_state(pinctrl, pins_sleep);
  743. And your machine configuration may look like this:
  744. --------------------------------------------------
  745. ::
  746. static unsigned long uart_default_mode[] = {
  747. PIN_CONF_PACKED(PIN_CONFIG_DRIVE_PUSH_PULL, 0),
  748. };
  749. static unsigned long uart_sleep_mode[] = {
  750. PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0),
  751. };
  752. static struct pinctrl_map pinmap[] __initdata = {
  753. PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
  754. "u0_group", "u0"),
  755. PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
  756. "UART_TX_PIN", uart_default_mode),
  757. PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
  758. "u0_group", "gpio-mode"),
  759. PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
  760. "UART_TX_PIN", uart_sleep_mode),
  761. };
  762. foo_init(void) {
  763. pinctrl_register_mappings(pinmap, ARRAY_SIZE(pinmap));
  764. }
  765. Here the pins we want to control are in the "u0_group" and there is some
  766. function called "u0" that can be enabled on this group of pins, and then
  767. everything is UART business as usual. But there is also some function
  768. named "gpio-mode" that can be mapped onto the same pins to move them into
  769. GPIO mode.
  770. This will give the desired effect without any bogus interaction with the
  771. GPIO subsystem. It is just an electrical configuration used by that device
  772. when going to sleep, it might imply that the pin is set into something the
  773. datasheet calls "GPIO mode", but that is not the point: it is still used
  774. by that UART device to control the pins that pertain to that very UART
  775. driver, putting them into modes needed by the UART. GPIO in the Linux
  776. kernel sense are just some 1-bit line, and is a different use case.
  777. How the registers are poked to attain the push or pull, and output low
  778. configuration and the muxing of the "u0" or "gpio-mode" group onto these
  779. pins is a question for the driver.
  780. Some datasheets will be more helpful and refer to the "GPIO mode" as
  781. "low power mode" rather than anything to do with GPIO. This often means
  782. the same thing electrically speaking, but in this latter case the
  783. software engineers will usually quickly identify that this is some
  784. specific muxing or configuration rather than anything related to the GPIO
  785. API.
  786. Board/machine configuration
  787. ===========================
  788. Boards and machines define how a certain complete running system is put
  789. together, including how GPIOs and devices are muxed, how regulators are
  790. constrained and how the clock tree looks. Of course pinmux settings are also
  791. part of this.
  792. A pin controller configuration for a machine looks pretty much like a simple
  793. regulator configuration, so for the example array above we want to enable i2c
  794. and spi on the second function mapping::
  795. #include <linux/pinctrl/machine.h>
  796. static const struct pinctrl_map mapping[] __initconst = {
  797. {
  798. .dev_name = "foo-spi.0",
  799. .name = PINCTRL_STATE_DEFAULT,
  800. .type = PIN_MAP_TYPE_MUX_GROUP,
  801. .ctrl_dev_name = "pinctrl-foo",
  802. .data.mux.function = "spi0",
  803. },
  804. {
  805. .dev_name = "foo-i2c.0",
  806. .name = PINCTRL_STATE_DEFAULT,
  807. .type = PIN_MAP_TYPE_MUX_GROUP,
  808. .ctrl_dev_name = "pinctrl-foo",
  809. .data.mux.function = "i2c0",
  810. },
  811. {
  812. .dev_name = "foo-mmc.0",
  813. .name = PINCTRL_STATE_DEFAULT,
  814. .type = PIN_MAP_TYPE_MUX_GROUP,
  815. .ctrl_dev_name = "pinctrl-foo",
  816. .data.mux.function = "mmc0",
  817. },
  818. };
  819. The dev_name here matches to the unique device name that can be used to look
  820. up the device struct (just like with clockdev or regulators). The function name
  821. must match a function provided by the pinmux driver handling this pin range.
  822. As you can see we may have several pin controllers on the system and thus
  823. we need to specify which one of them contains the functions we wish to map.
  824. You register this pinmux mapping to the pinmux subsystem by simply::
  825. ret = pinctrl_register_mappings(mapping, ARRAY_SIZE(mapping));
  826. Since the above construct is pretty common there is a helper macro to make
  827. it even more compact which assumes you want to use pinctrl-foo and position
  828. 0 for mapping, for example::
  829. static struct pinctrl_map mapping[] __initdata = {
  830. PIN_MAP_MUX_GROUP("foo-i2c.o", PINCTRL_STATE_DEFAULT,
  831. "pinctrl-foo", NULL, "i2c0"),
  832. };
  833. The mapping table may also contain pin configuration entries. It's common for
  834. each pin/group to have a number of configuration entries that affect it, so
  835. the table entries for configuration reference an array of config parameters
  836. and values. An example using the convenience macros is shown below::
  837. static unsigned long i2c_grp_configs[] = {
  838. FOO_PIN_DRIVEN,
  839. FOO_PIN_PULLUP,
  840. };
  841. static unsigned long i2c_pin_configs[] = {
  842. FOO_OPEN_COLLECTOR,
  843. FOO_SLEW_RATE_SLOW,
  844. };
  845. static struct pinctrl_map mapping[] __initdata = {
  846. PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT,
  847. "pinctrl-foo", "i2c0", "i2c0"),
  848. PIN_MAP_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT,
  849. "pinctrl-foo", "i2c0", i2c_grp_configs),
  850. PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT,
  851. "pinctrl-foo", "i2c0scl", i2c_pin_configs),
  852. PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT,
  853. "pinctrl-foo", "i2c0sda", i2c_pin_configs),
  854. };
  855. Finally, some devices expect the mapping table to contain certain specific
  856. named states. When running on hardware that doesn't need any pin controller
  857. configuration, the mapping table must still contain those named states, in
  858. order to explicitly indicate that the states were provided and intended to
  859. be empty. Table entry macro PIN_MAP_DUMMY_STATE serves the purpose of defining
  860. a named state without causing any pin controller to be programmed::
  861. static struct pinctrl_map mapping[] __initdata = {
  862. PIN_MAP_DUMMY_STATE("foo-i2c.0", PINCTRL_STATE_DEFAULT),
  863. };
  864. Complex mappings
  865. ================
  866. As it is possible to map a function to different groups of pins an optional
  867. .group can be specified like this::
  868. ...
  869. {
  870. .dev_name = "foo-spi.0",
  871. .name = "spi0-pos-A",
  872. .type = PIN_MAP_TYPE_MUX_GROUP,
  873. .ctrl_dev_name = "pinctrl-foo",
  874. .function = "spi0",
  875. .group = "spi0_0_grp",
  876. },
  877. {
  878. .dev_name = "foo-spi.0",
  879. .name = "spi0-pos-B",
  880. .type = PIN_MAP_TYPE_MUX_GROUP,
  881. .ctrl_dev_name = "pinctrl-foo",
  882. .function = "spi0",
  883. .group = "spi0_1_grp",
  884. },
  885. ...
  886. This example mapping is used to switch between two positions for spi0 at
  887. runtime, as described further below under the heading "Runtime pinmuxing".
  888. Further it is possible for one named state to affect the muxing of several
  889. groups of pins, say for example in the mmc0 example above, where you can
  890. additively expand the mmc0 bus from 2 to 4 to 8 pins. If we want to use all
  891. three groups for a total of 2+2+4 = 8 pins (for an 8-bit MMC bus as is the
  892. case), we define a mapping like this::
  893. ...
  894. {
  895. .dev_name = "foo-mmc.0",
  896. .name = "2bit"
  897. .type = PIN_MAP_TYPE_MUX_GROUP,
  898. .ctrl_dev_name = "pinctrl-foo",
  899. .function = "mmc0",
  900. .group = "mmc0_1_grp",
  901. },
  902. {
  903. .dev_name = "foo-mmc.0",
  904. .name = "4bit"
  905. .type = PIN_MAP_TYPE_MUX_GROUP,
  906. .ctrl_dev_name = "pinctrl-foo",
  907. .function = "mmc0",
  908. .group = "mmc0_1_grp",
  909. },
  910. {
  911. .dev_name = "foo-mmc.0",
  912. .name = "4bit"
  913. .type = PIN_MAP_TYPE_MUX_GROUP,
  914. .ctrl_dev_name = "pinctrl-foo",
  915. .function = "mmc0",
  916. .group = "mmc0_2_grp",
  917. },
  918. {
  919. .dev_name = "foo-mmc.0",
  920. .name = "8bit"
  921. .type = PIN_MAP_TYPE_MUX_GROUP,
  922. .ctrl_dev_name = "pinctrl-foo",
  923. .function = "mmc0",
  924. .group = "mmc0_1_grp",
  925. },
  926. {
  927. .dev_name = "foo-mmc.0",
  928. .name = "8bit"
  929. .type = PIN_MAP_TYPE_MUX_GROUP,
  930. .ctrl_dev_name = "pinctrl-foo",
  931. .function = "mmc0",
  932. .group = "mmc0_2_grp",
  933. },
  934. {
  935. .dev_name = "foo-mmc.0",
  936. .name = "8bit"
  937. .type = PIN_MAP_TYPE_MUX_GROUP,
  938. .ctrl_dev_name = "pinctrl-foo",
  939. .function = "mmc0",
  940. .group = "mmc0_3_grp",
  941. },
  942. ...
  943. The result of grabbing this mapping from the device with something like
  944. this (see next paragraph)::
  945. p = devm_pinctrl_get(dev);
  946. s = pinctrl_lookup_state(p, "8bit");
  947. ret = pinctrl_select_state(p, s);
  948. or more simply::
  949. p = devm_pinctrl_get_select(dev, "8bit");
  950. Will be that you activate all the three bottom records in the mapping at
  951. once. Since they share the same name, pin controller device, function and
  952. device, and since we allow multiple groups to match to a single device, they
  953. all get selected, and they all get enabled and disable simultaneously by the
  954. pinmux core.
  955. Pin control requests from drivers
  956. =================================
  957. When a device driver is about to probe the device core will automatically
  958. attempt to issue pinctrl_get_select_default() on these devices.
  959. This way driver writers do not need to add any of the boilerplate code
  960. of the type found below. However when doing fine-grained state selection
  961. and not using the "default" state, you may have to do some device driver
  962. handling of the pinctrl handles and states.
  963. So if you just want to put the pins for a certain device into the default
  964. state and be done with it, there is nothing you need to do besides
  965. providing the proper mapping table. The device core will take care of
  966. the rest.
  967. Generally it is discouraged to let individual drivers get and enable pin
  968. control. So if possible, handle the pin control in platform code or some other
  969. place where you have access to all the affected struct device * pointers. In
  970. some cases where a driver needs to e.g. switch between different mux mappings
  971. at runtime this is not possible.
  972. A typical case is if a driver needs to switch bias of pins from normal
  973. operation and going to sleep, moving from the PINCTRL_STATE_DEFAULT to
  974. PINCTRL_STATE_SLEEP at runtime, re-biasing or even re-muxing pins to save
  975. current in sleep mode.
  976. A driver may request a certain control state to be activated, usually just the
  977. default state like this::
  978. #include <linux/pinctrl/consumer.h>
  979. struct foo_state {
  980. struct pinctrl *p;
  981. struct pinctrl_state *s;
  982. ...
  983. };
  984. foo_probe()
  985. {
  986. /* Allocate a state holder named "foo" etc */
  987. struct foo_state *foo = ...;
  988. foo->p = devm_pinctrl_get(&device);
  989. if (IS_ERR(foo->p)) {
  990. /* FIXME: clean up "foo" here */
  991. return PTR_ERR(foo->p);
  992. }
  993. foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
  994. if (IS_ERR(foo->s)) {
  995. /* FIXME: clean up "foo" here */
  996. return PTR_ERR(s);
  997. }
  998. ret = pinctrl_select_state(foo->s);
  999. if (ret < 0) {
  1000. /* FIXME: clean up "foo" here */
  1001. return ret;
  1002. }
  1003. }
  1004. This get/lookup/select/put sequence can just as well be handled by bus drivers
  1005. if you don't want each and every driver to handle it and you know the
  1006. arrangement on your bus.
  1007. The semantics of the pinctrl APIs are:
  1008. - pinctrl_get() is called in process context to obtain a handle to all pinctrl
  1009. information for a given client device. It will allocate a struct from the
  1010. kernel memory to hold the pinmux state. All mapping table parsing or similar
  1011. slow operations take place within this API.
  1012. - devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put()
  1013. to be called automatically on the retrieved pointer when the associated
  1014. device is removed. It is recommended to use this function over plain
  1015. pinctrl_get().
  1016. - pinctrl_lookup_state() is called in process context to obtain a handle to a
  1017. specific state for a client device. This operation may be slow, too.
  1018. - pinctrl_select_state() programs pin controller hardware according to the
  1019. definition of the state as given by the mapping table. In theory, this is a
  1020. fast-path operation, since it only involved blasting some register settings
  1021. into hardware. However, note that some pin controllers may have their
  1022. registers on a slow/IRQ-based bus, so client devices should not assume they
  1023. can call pinctrl_select_state() from non-blocking contexts.
  1024. - pinctrl_put() frees all information associated with a pinctrl handle.
  1025. - devm_pinctrl_put() is a variant of pinctrl_put() that may be used to
  1026. explicitly destroy a pinctrl object returned by devm_pinctrl_get().
  1027. However, use of this function will be rare, due to the automatic cleanup
  1028. that will occur even without calling it.
  1029. pinctrl_get() must be paired with a plain pinctrl_put().
  1030. pinctrl_get() may not be paired with devm_pinctrl_put().
  1031. devm_pinctrl_get() can optionally be paired with devm_pinctrl_put().
  1032. devm_pinctrl_get() may not be paired with plain pinctrl_put().
  1033. Usually the pin control core handled the get/put pair and call out to the
  1034. device drivers bookkeeping operations, like checking available functions and
  1035. the associated pins, whereas select_state pass on to the pin controller
  1036. driver which takes care of activating and/or deactivating the mux setting by
  1037. quickly poking some registers.
  1038. The pins are allocated for your device when you issue the devm_pinctrl_get()
  1039. call, after this you should be able to see this in the debugfs listing of all
  1040. pins.
  1041. NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the
  1042. requested pinctrl handles, for example if the pinctrl driver has not yet
  1043. registered. Thus make sure that the error path in your driver gracefully
  1044. cleans up and is ready to retry the probing later in the startup process.
  1045. Drivers needing both pin control and GPIOs
  1046. ==========================================
  1047. Again, it is discouraged to let drivers lookup and select pin control states
  1048. themselves, but again sometimes this is unavoidable.
  1049. So say that your driver is fetching its resources like this::
  1050. #include <linux/pinctrl/consumer.h>
  1051. #include <linux/gpio.h>
  1052. struct pinctrl *pinctrl;
  1053. int gpio;
  1054. pinctrl = devm_pinctrl_get_select_default(&dev);
  1055. gpio = devm_gpio_request(&dev, 14, "foo");
  1056. Here we first request a certain pin state and then request GPIO 14 to be
  1057. used. If you're using the subsystems orthogonally like this, you should
  1058. nominally always get your pinctrl handle and select the desired pinctrl
  1059. state BEFORE requesting the GPIO. This is a semantic convention to avoid
  1060. situations that can be electrically unpleasant, you will certainly want to
  1061. mux in and bias pins in a certain way before the GPIO subsystems starts to
  1062. deal with them.
  1063. The above can be hidden: using the device core, the pinctrl core may be
  1064. setting up the config and muxing for the pins right before the device is
  1065. probing, nevertheless orthogonal to the GPIO subsystem.
  1066. But there are also situations where it makes sense for the GPIO subsystem
  1067. to communicate directly with the pinctrl subsystem, using the latter as a
  1068. back-end. This is when the GPIO driver may call out to the functions
  1069. described in the section "Pin control interaction with the GPIO subsystem"
  1070. above. This only involves per-pin multiplexing, and will be completely
  1071. hidden behind the gpio_*() function namespace. In this case, the driver
  1072. need not interact with the pin control subsystem at all.
  1073. If a pin control driver and a GPIO driver is dealing with the same pins
  1074. and the use cases involve multiplexing, you MUST implement the pin controller
  1075. as a back-end for the GPIO driver like this, unless your hardware design
  1076. is such that the GPIO controller can override the pin controller's
  1077. multiplexing state through hardware without the need to interact with the
  1078. pin control system.
  1079. System pin control hogging
  1080. ==========================
  1081. Pin control map entries can be hogged by the core when the pin controller
  1082. is registered. This means that the core will attempt to call pinctrl_get(),
  1083. lookup_state() and select_state() on it immediately after the pin control
  1084. device has been registered.
  1085. This occurs for mapping table entries where the client device name is equal
  1086. to the pin controller device name, and the state name is PINCTRL_STATE_DEFAULT::
  1087. {
  1088. .dev_name = "pinctrl-foo",
  1089. .name = PINCTRL_STATE_DEFAULT,
  1090. .type = PIN_MAP_TYPE_MUX_GROUP,
  1091. .ctrl_dev_name = "pinctrl-foo",
  1092. .function = "power_func",
  1093. },
  1094. Since it may be common to request the core to hog a few always-applicable
  1095. mux settings on the primary pin controller, there is a convenience macro for
  1096. this::
  1097. PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-foo", NULL /* group */,
  1098. "power_func")
  1099. This gives the exact same result as the above construction.
  1100. Runtime pinmuxing
  1101. =================
  1102. It is possible to mux a certain function in and out at runtime, say to move
  1103. an SPI port from one set of pins to another set of pins. Say for example for
  1104. spi0 in the example above, we expose two different groups of pins for the same
  1105. function, but with different named in the mapping as described under
  1106. "Advanced mapping" above. So that for an SPI device, we have two states named
  1107. "pos-A" and "pos-B".
  1108. This snippet first initializes a state object for both groups (in foo_probe()),
  1109. then muxes the function in the pins defined by group A, and finally muxes it in
  1110. on the pins defined by group B::
  1111. #include <linux/pinctrl/consumer.h>
  1112. struct pinctrl *p;
  1113. struct pinctrl_state *s1, *s2;
  1114. foo_probe()
  1115. {
  1116. /* Setup */
  1117. p = devm_pinctrl_get(&device);
  1118. if (IS_ERR(p))
  1119. ...
  1120. s1 = pinctrl_lookup_state(foo->p, "pos-A");
  1121. if (IS_ERR(s1))
  1122. ...
  1123. s2 = pinctrl_lookup_state(foo->p, "pos-B");
  1124. if (IS_ERR(s2))
  1125. ...
  1126. }
  1127. foo_switch()
  1128. {
  1129. /* Enable on position A */
  1130. ret = pinctrl_select_state(s1);
  1131. if (ret < 0)
  1132. ...
  1133. ...
  1134. /* Enable on position B */
  1135. ret = pinctrl_select_state(s2);
  1136. if (ret < 0)
  1137. ...
  1138. ...
  1139. }
  1140. The above has to be done from process context. The reservation of the pins
  1141. will be done when the state is activated, so in effect one specific pin
  1142. can be used by different functions at different times on a running system.