sve.rst 20 KB

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  1. ===================================================
  2. Scalable Vector Extension support for AArch64 Linux
  3. ===================================================
  4. Author: Dave Martin <Dave.Martin@arm.com>
  5. Date: 4 August 2017
  6. This document outlines briefly the interface provided to userspace by Linux in
  7. order to support use of the ARM Scalable Vector Extension (SVE).
  8. This is an outline of the most important features and issues only and not
  9. intended to be exhaustive.
  10. This document does not aim to describe the SVE architecture or programmer's
  11. model. To aid understanding, a minimal description of relevant programmer's
  12. model features for SVE is included in Appendix A.
  13. 1. General
  14. -----------
  15. * SVE registers Z0..Z31, P0..P15 and FFR and the current vector length VL, are
  16. tracked per-thread.
  17. * The presence of SVE is reported to userspace via HWCAP_SVE in the aux vector
  18. AT_HWCAP entry. Presence of this flag implies the presence of the SVE
  19. instructions and registers, and the Linux-specific system interfaces
  20. described in this document. SVE is reported in /proc/cpuinfo as "sve".
  21. * Support for the execution of SVE instructions in userspace can also be
  22. detected by reading the CPU ID register ID_AA64PFR0_EL1 using an MRS
  23. instruction, and checking that the value of the SVE field is nonzero. [3]
  24. It does not guarantee the presence of the system interfaces described in the
  25. following sections: software that needs to verify that those interfaces are
  26. present must check for HWCAP_SVE instead.
  27. * On hardware that supports the SVE2 extensions, HWCAP2_SVE2 will also
  28. be reported in the AT_HWCAP2 aux vector entry. In addition to this,
  29. optional extensions to SVE2 may be reported by the presence of:
  30. HWCAP2_SVE2
  31. HWCAP2_SVEAES
  32. HWCAP2_SVEPMULL
  33. HWCAP2_SVEBITPERM
  34. HWCAP2_SVESHA3
  35. HWCAP2_SVESM4
  36. This list may be extended over time as the SVE architecture evolves.
  37. These extensions are also reported via the CPU ID register ID_AA64ZFR0_EL1,
  38. which userspace can read using an MRS instruction. See elf_hwcaps.txt and
  39. cpu-feature-registers.txt for details.
  40. * Debuggers should restrict themselves to interacting with the target via the
  41. NT_ARM_SVE regset. The recommended way of detecting support for this regset
  42. is to connect to a target process first and then attempt a
  43. ptrace(PTRACE_GETREGSET, pid, NT_ARM_SVE, &iov).
  44. * Whenever SVE scalable register values (Zn, Pn, FFR) are exchanged in memory
  45. between userspace and the kernel, the register value is encoded in memory in
  46. an endianness-invariant layout, with bits [(8 * i + 7) : (8 * i)] encoded at
  47. byte offset i from the start of the memory representation. This affects for
  48. example the signal frame (struct sve_context) and ptrace interface
  49. (struct user_sve_header) and associated data.
  50. Beware that on big-endian systems this results in a different byte order than
  51. for the FPSIMD V-registers, which are stored as single host-endian 128-bit
  52. values, with bits [(127 - 8 * i) : (120 - 8 * i)] of the register encoded at
  53. byte offset i. (struct fpsimd_context, struct user_fpsimd_state).
  54. 2. Vector length terminology
  55. -----------------------------
  56. The size of an SVE vector (Z) register is referred to as the "vector length".
  57. To avoid confusion about the units used to express vector length, the kernel
  58. adopts the following conventions:
  59. * Vector length (VL) = size of a Z-register in bytes
  60. * Vector quadwords (VQ) = size of a Z-register in units of 128 bits
  61. (So, VL = 16 * VQ.)
  62. The VQ convention is used where the underlying granularity is important, such
  63. as in data structure definitions. In most other situations, the VL convention
  64. is used. This is consistent with the meaning of the "VL" pseudo-register in
  65. the SVE instruction set architecture.
  66. 3. System call behaviour
  67. -------------------------
  68. * On syscall, V0..V31 are preserved (as without SVE). Thus, bits [127:0] of
  69. Z0..Z31 are preserved. All other bits of Z0..Z31, and all of P0..P15 and FFR
  70. become unspecified on return from a syscall.
  71. * The SVE registers are not used to pass arguments to or receive results from
  72. any syscall.
  73. * In practice the affected registers/bits will be preserved or will be replaced
  74. with zeros on return from a syscall, but userspace should not make
  75. assumptions about this. The kernel behaviour may vary on a case-by-case
  76. basis.
  77. * All other SVE state of a thread, including the currently configured vector
  78. length, the state of the PR_SVE_VL_INHERIT flag, and the deferred vector
  79. length (if any), is preserved across all syscalls, subject to the specific
  80. exceptions for execve() described in section 6.
  81. In particular, on return from a fork() or clone(), the parent and new child
  82. process or thread share identical SVE configuration, matching that of the
  83. parent before the call.
  84. 4. Signal handling
  85. -------------------
  86. * A new signal frame record sve_context encodes the SVE registers on signal
  87. delivery. [1]
  88. * This record is supplementary to fpsimd_context. The FPSR and FPCR registers
  89. are only present in fpsimd_context. For convenience, the content of V0..V31
  90. is duplicated between sve_context and fpsimd_context.
  91. * The signal frame record for SVE always contains basic metadata, in particular
  92. the thread's vector length (in sve_context.vl).
  93. * The SVE registers may or may not be included in the record, depending on
  94. whether the registers are live for the thread. The registers are present if
  95. and only if:
  96. sve_context.head.size >= SVE_SIG_CONTEXT_SIZE(sve_vq_from_vl(sve_context.vl)).
  97. * If the registers are present, the remainder of the record has a vl-dependent
  98. size and layout. Macros SVE_SIG_* are defined [1] to facilitate access to
  99. the members.
  100. * Each scalable register (Zn, Pn, FFR) is stored in an endianness-invariant
  101. layout, with bits [(8 * i + 7) : (8 * i)] stored at byte offset i from the
  102. start of the register's representation in memory.
  103. * If the SVE context is too big to fit in sigcontext.__reserved[], then extra
  104. space is allocated on the stack, an extra_context record is written in
  105. __reserved[] referencing this space. sve_context is then written in the
  106. extra space. Refer to [1] for further details about this mechanism.
  107. 5. Signal return
  108. -----------------
  109. When returning from a signal handler:
  110. * If there is no sve_context record in the signal frame, or if the record is
  111. present but contains no register data as desribed in the previous section,
  112. then the SVE registers/bits become non-live and take unspecified values.
  113. * If sve_context is present in the signal frame and contains full register
  114. data, the SVE registers become live and are populated with the specified
  115. data. However, for backward compatibility reasons, bits [127:0] of Z0..Z31
  116. are always restored from the corresponding members of fpsimd_context.vregs[]
  117. and not from sve_context. The remaining bits are restored from sve_context.
  118. * Inclusion of fpsimd_context in the signal frame remains mandatory,
  119. irrespective of whether sve_context is present or not.
  120. * The vector length cannot be changed via signal return. If sve_context.vl in
  121. the signal frame does not match the current vector length, the signal return
  122. attempt is treated as illegal, resulting in a forced SIGSEGV.
  123. 6. prctl extensions
  124. --------------------
  125. Some new prctl() calls are added to allow programs to manage the SVE vector
  126. length:
  127. prctl(PR_SVE_SET_VL, unsigned long arg)
  128. Sets the vector length of the calling thread and related flags, where
  129. arg == vl | flags. Other threads of the calling process are unaffected.
  130. vl is the desired vector length, where sve_vl_valid(vl) must be true.
  131. flags:
  132. PR_SVE_VL_INHERIT
  133. Inherit the current vector length across execve(). Otherwise, the
  134. vector length is reset to the system default at execve(). (See
  135. Section 9.)
  136. PR_SVE_SET_VL_ONEXEC
  137. Defer the requested vector length change until the next execve()
  138. performed by this thread.
  139. The effect is equivalent to implicit exceution of the following
  140. call immediately after the next execve() (if any) by the thread:
  141. prctl(PR_SVE_SET_VL, arg & ~PR_SVE_SET_VL_ONEXEC)
  142. This allows launching of a new program with a different vector
  143. length, while avoiding runtime side effects in the caller.
  144. Without PR_SVE_SET_VL_ONEXEC, the requested change takes effect
  145. immediately.
  146. Return value: a nonnegative on success, or a negative value on error:
  147. EINVAL: SVE not supported, invalid vector length requested, or
  148. invalid flags.
  149. On success:
  150. * Either the calling thread's vector length or the deferred vector length
  151. to be applied at the next execve() by the thread (dependent on whether
  152. PR_SVE_SET_VL_ONEXEC is present in arg), is set to the largest value
  153. supported by the system that is less than or equal to vl. If vl ==
  154. SVE_VL_MAX, the value set will be the largest value supported by the
  155. system.
  156. * Any previously outstanding deferred vector length change in the calling
  157. thread is cancelled.
  158. * The returned value describes the resulting configuration, encoded as for
  159. PR_SVE_GET_VL. The vector length reported in this value is the new
  160. current vector length for this thread if PR_SVE_SET_VL_ONEXEC was not
  161. present in arg; otherwise, the reported vector length is the deferred
  162. vector length that will be applied at the next execve() by the calling
  163. thread.
  164. * Changing the vector length causes all of P0..P15, FFR and all bits of
  165. Z0..Z31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become
  166. unspecified. Calling PR_SVE_SET_VL with vl equal to the thread's current
  167. vector length, or calling PR_SVE_SET_VL with the PR_SVE_SET_VL_ONEXEC
  168. flag, does not constitute a change to the vector length for this purpose.
  169. prctl(PR_SVE_GET_VL)
  170. Gets the vector length of the calling thread.
  171. The following flag may be OR-ed into the result:
  172. PR_SVE_VL_INHERIT
  173. Vector length will be inherited across execve().
  174. There is no way to determine whether there is an outstanding deferred
  175. vector length change (which would only normally be the case between a
  176. fork() or vfork() and the corresponding execve() in typical use).
  177. To extract the vector length from the result, and it with
  178. PR_SVE_VL_LEN_MASK.
  179. Return value: a nonnegative value on success, or a negative value on error:
  180. EINVAL: SVE not supported.
  181. 7. ptrace extensions
  182. ---------------------
  183. * A new regset NT_ARM_SVE is defined for use with PTRACE_GETREGSET and
  184. PTRACE_SETREGSET.
  185. Refer to [2] for definitions.
  186. The regset data starts with struct user_sve_header, containing:
  187. size
  188. Size of the complete regset, in bytes.
  189. This depends on vl and possibly on other things in the future.
  190. If a call to PTRACE_GETREGSET requests less data than the value of
  191. size, the caller can allocate a larger buffer and retry in order to
  192. read the complete regset.
  193. max_size
  194. Maximum size in bytes that the regset can grow to for the target
  195. thread. The regset won't grow bigger than this even if the target
  196. thread changes its vector length etc.
  197. vl
  198. Target thread's current vector length, in bytes.
  199. max_vl
  200. Maximum possible vector length for the target thread.
  201. flags
  202. either
  203. SVE_PT_REGS_FPSIMD
  204. SVE registers are not live (GETREGSET) or are to be made
  205. non-live (SETREGSET).
  206. The payload is of type struct user_fpsimd_state, with the same
  207. meaning as for NT_PRFPREG, starting at offset
  208. SVE_PT_FPSIMD_OFFSET from the start of user_sve_header.
  209. Extra data might be appended in the future: the size of the
  210. payload should be obtained using SVE_PT_FPSIMD_SIZE(vq, flags).
  211. vq should be obtained using sve_vq_from_vl(vl).
  212. or
  213. SVE_PT_REGS_SVE
  214. SVE registers are live (GETREGSET) or are to be made live
  215. (SETREGSET).
  216. The payload contains the SVE register data, starting at offset
  217. SVE_PT_SVE_OFFSET from the start of user_sve_header, and with
  218. size SVE_PT_SVE_SIZE(vq, flags);
  219. ... OR-ed with zero or more of the following flags, which have the same
  220. meaning and behaviour as the corresponding PR_SET_VL_* flags:
  221. SVE_PT_VL_INHERIT
  222. SVE_PT_VL_ONEXEC (SETREGSET only).
  223. * The effects of changing the vector length and/or flags are equivalent to
  224. those documented for PR_SVE_SET_VL.
  225. The caller must make a further GETREGSET call if it needs to know what VL is
  226. actually set by SETREGSET, unless is it known in advance that the requested
  227. VL is supported.
  228. * In the SVE_PT_REGS_SVE case, the size and layout of the payload depends on
  229. the header fields. The SVE_PT_SVE_*() macros are provided to facilitate
  230. access to the members.
  231. * In either case, for SETREGSET it is permissible to omit the payload, in which
  232. case only the vector length and flags are changed (along with any
  233. consequences of those changes).
  234. * For SETREGSET, if an SVE_PT_REGS_SVE payload is present and the
  235. requested VL is not supported, the effect will be the same as if the
  236. payload were omitted, except that an EIO error is reported. No
  237. attempt is made to translate the payload data to the correct layout
  238. for the vector length actually set. The thread's FPSIMD state is
  239. preserved, but the remaining bits of the SVE registers become
  240. unspecified. It is up to the caller to translate the payload layout
  241. for the actual VL and retry.
  242. * The effect of writing a partial, incomplete payload is unspecified.
  243. 8. ELF coredump extensions
  244. ---------------------------
  245. * A NT_ARM_SVE note will be added to each coredump for each thread of the
  246. dumped process. The contents will be equivalent to the data that would have
  247. been read if a PTRACE_GETREGSET of NT_ARM_SVE were executed for each thread
  248. when the coredump was generated.
  249. 9. System runtime configuration
  250. --------------------------------
  251. * To mitigate the ABI impact of expansion of the signal frame, a policy
  252. mechanism is provided for administrators, distro maintainers and developers
  253. to set the default vector length for userspace processes:
  254. /proc/sys/abi/sve_default_vector_length
  255. Writing the text representation of an integer to this file sets the system
  256. default vector length to the specified value, unless the value is greater
  257. than the maximum vector length supported by the system in which case the
  258. default vector length is set to that maximum.
  259. The result can be determined by reopening the file and reading its
  260. contents.
  261. At boot, the default vector length is initially set to 64 or the maximum
  262. supported vector length, whichever is smaller. This determines the initial
  263. vector length of the init process (PID 1).
  264. Reading this file returns the current system default vector length.
  265. * At every execve() call, the new vector length of the new process is set to
  266. the system default vector length, unless
  267. * PR_SVE_VL_INHERIT (or equivalently SVE_PT_VL_INHERIT) is set for the
  268. calling thread, or
  269. * a deferred vector length change is pending, established via the
  270. PR_SVE_SET_VL_ONEXEC flag (or SVE_PT_VL_ONEXEC).
  271. * Modifying the system default vector length does not affect the vector length
  272. of any existing process or thread that does not make an execve() call.
  273. Appendix A. SVE programmer's model (informative)
  274. =================================================
  275. This section provides a minimal description of the additions made by SVE to the
  276. ARMv8-A programmer's model that are relevant to this document.
  277. Note: This section is for information only and not intended to be complete or
  278. to replace any architectural specification.
  279. A.1. Registers
  280. ---------------
  281. In A64 state, SVE adds the following:
  282. * 32 8VL-bit vector registers Z0..Z31
  283. For each Zn, Zn bits [127:0] alias the ARMv8-A vector register Vn.
  284. A register write using a Vn register name zeros all bits of the corresponding
  285. Zn except for bits [127:0].
  286. * 16 VL-bit predicate registers P0..P15
  287. * 1 VL-bit special-purpose predicate register FFR (the "first-fault register")
  288. * a VL "pseudo-register" that determines the size of each vector register
  289. The SVE instruction set architecture provides no way to write VL directly.
  290. Instead, it can be modified only by EL1 and above, by writing appropriate
  291. system registers.
  292. * The value of VL can be configured at runtime by EL1 and above:
  293. 16 <= VL <= VLmax, where VL must be a multiple of 16.
  294. * The maximum vector length is determined by the hardware:
  295. 16 <= VLmax <= 256.
  296. (The SVE architecture specifies 256, but permits future architecture
  297. revisions to raise this limit.)
  298. * FPSR and FPCR are retained from ARMv8-A, and interact with SVE floating-point
  299. operations in a similar way to the way in which they interact with ARMv8
  300. floating-point operations::
  301. 8VL-1 128 0 bit index
  302. +---- //// -----------------+
  303. Z0 | : V0 |
  304. : :
  305. Z7 | : V7 |
  306. Z8 | : * V8 |
  307. : : :
  308. Z15 | : *V15 |
  309. Z16 | : V16 |
  310. : :
  311. Z31 | : V31 |
  312. +---- //// -----------------+
  313. 31 0
  314. VL-1 0 +-------+
  315. +---- //// --+ FPSR | |
  316. P0 | | +-------+
  317. : | | *FPCR | |
  318. P15 | | +-------+
  319. +---- //// --+
  320. FFR | | +-----+
  321. +---- //// --+ VL | |
  322. +-----+
  323. (*) callee-save:
  324. This only applies to bits [63:0] of Z-/V-registers.
  325. FPCR contains callee-save and caller-save bits. See [4] for details.
  326. A.2. Procedure call standard
  327. -----------------------------
  328. The ARMv8-A base procedure call standard is extended as follows with respect to
  329. the additional SVE register state:
  330. * All SVE register bits that are not shared with FP/SIMD are caller-save.
  331. * Z8 bits [63:0] .. Z15 bits [63:0] are callee-save.
  332. This follows from the way these bits are mapped to V8..V15, which are caller-
  333. save in the base procedure call standard.
  334. Appendix B. ARMv8-A FP/SIMD programmer's model
  335. ===============================================
  336. Note: This section is for information only and not intended to be complete or
  337. to replace any architectural specification.
  338. Refer to [4] for more information.
  339. ARMv8-A defines the following floating-point / SIMD register state:
  340. * 32 128-bit vector registers V0..V31
  341. * 2 32-bit status/control registers FPSR, FPCR
  342. ::
  343. 127 0 bit index
  344. +---------------+
  345. V0 | |
  346. : : :
  347. V7 | |
  348. * V8 | |
  349. : : : :
  350. *V15 | |
  351. V16 | |
  352. : : :
  353. V31 | |
  354. +---------------+
  355. 31 0
  356. +-------+
  357. FPSR | |
  358. +-------+
  359. *FPCR | |
  360. +-------+
  361. (*) callee-save:
  362. This only applies to bits [63:0] of V-registers.
  363. FPCR contains a mixture of callee-save and caller-save bits.
  364. References
  365. ==========
  366. [1] arch/arm64/include/uapi/asm/sigcontext.h
  367. AArch64 Linux signal ABI definitions
  368. [2] arch/arm64/include/uapi/asm/ptrace.h
  369. AArch64 Linux ptrace ABI definitions
  370. [3] Documentation/arm64/cpu-feature-registers.rst
  371. [4] ARM IHI0055C
  372. http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055c/IHI0055C_beta_aapcs64.pdf
  373. http://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.abi/index.html
  374. Procedure Call Standard for the ARM 64-bit Architecture (AArch64)