light-i2s.h 24 KB

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  1. #ifndef _LIGHT_I2S_H
  2. #define _LIGHT_I2S_H
  3. #include <linux/io.h>
  4. #include <linux/module.h>
  5. #include <linux/workqueue.h>
  6. #include <linux/scatterlist.h>
  7. #include <linux/sh_dma.h>
  8. #include <linux/slab.h>
  9. #include <linux/module.h>
  10. #include <linux/workqueue.h>
  11. #include <sound/soc.h>
  12. #include <sound/pcm_params.h>
  13. #include <sound/pcm.h>
  14. #include <sound/core.h>
  15. #include <sound/initval.h>
  16. #include <sound/dmaengine_pcm.h>
  17. #include "light-pcm.h"
  18. #include <linux/spinlock.h>
  19. #define I2S_IISEN 0x000 /* IIS Enable Register */
  20. #define I2S_FUNCMODE 0x004 /* IIS function mode */
  21. #define I2S_IISCNF_IN 0x008 /* IIS interface configuration in (on RX side) */
  22. #define I2S_FSSTA 0x00c /* IIS ATX audio input control/state register */
  23. #define I2S_IISCNF_OUT 0x010 /* IIS interface configuration in (on TX side) */
  24. #define I2S_FADTLR 0x014 /* IIS Fs auto detected Threshold level register */
  25. #define I2S_SCCR 0x018 /* Sample compress control register */
  26. #define I2S_TXFTLR 0x01c /* Transmit FIFO Threshold Level */
  27. #define I2S_RXFTLR 0x020 /* Receive FIFO Threshold Level */
  28. #define I2S_TXFLR 0x024 /* Transmit FIFO Level Register */
  29. #define I2S_RXFLR 0x028 /* Receive FIFO Level Register */
  30. #define I2S_SR 0x02c /* Status Register */
  31. #define I2S_IMR 0x030 /* Interrupt Mask Register */
  32. #define I2S_ISR 0x034 /* Interrupt Status Register */
  33. #define I2S_RISR 0x038 /* Raw Interrupt Status Register */
  34. #define I2S_ICR 0x03c /* FIFO Interrupt Clear Register */
  35. #define I2S_DMACR 0x040 /* DMA Control Register */
  36. #define I2S_DMATDLR 0x044 /* DMA Transmit Data Level */
  37. #define I2S_DMARDLR 0x048 /* DMA Receive Data Level */
  38. #define I2S_DR 0x04C /* Data Register */
  39. #define I2S_DIV0_LEVEL 0x050 /* Divide i2s_clkgen source clock, get mclk_o */
  40. #define I2S_DIV3_LEVEL 0x054 /* Divide i2s_clkgen source clock, get reference clock */
  41. #define RESERVED 0x058 /* RESERVED */
  42. #define RESERVED1 0x05C /* RESERVED */
  43. #define I2S_DR1 0x060 /* CH1_Data Register */
  44. #define I2S_DR2 0x064 /* CH2_Data Register */
  45. #define I2S_DR3 0x068 /* CH3_Data Register */
  46. #define I2S_DR4 0x06C /* CH4_Data Register */
  47. #define CPR_PERI_DIV_SEL_REG 0x004 /*audio sys i2s clock div Register*/
  48. #define CPR_PERI_CLK_SEL_REG 0x008 /*audio sys i2s clock selection Register*/
  49. /* IISEN , offset: 0x00 */
  50. #define IISEN_I2SEN_POS (0U)
  51. #define IISEN_I2SEN_MSK (0x1U << IISEN_I2SEN_POS)
  52. #define IISEN_I2SEN IISEN_I2SEN_MSK
  53. /* FUNCMODE, offset: 0x04 */
  54. #define FUNCMODE_TMODE_Pos (0U)
  55. #define FUNCMODE_TMODE_Msk (0x1U << FUNCMODE_TMODE_Pos)
  56. #define FUNCMODE_TMODE FUNCMODE_TMODE_Msk
  57. #define FUNCMODE_TMODE_WEN_Pos (1U)
  58. #define FUNCMODE_TMODE_WEN_Msk (0x1U << FUNCMODE_TMODE_WEN_Pos)
  59. #define FUNCMODE_TMODE_WEN FUNCMODE_TMODE_WEN_Msk
  60. #define FUNCMODE_RMODE_Pos (4U)
  61. #define FUNCMODE_RMODE_Msk (0x1U << FUNCMODE_RMODE_Pos)
  62. #define FUNCMODE_RMODE FUNCMODE_RMODE_Msk
  63. #define FUNCMODE_RMODE_WEN_Pos (5U)
  64. #define FUNCMODE_RMODE_WEN_Msk (0x1U << FUNCMODE_RMODE_WEN_Pos)
  65. #define FUNCMODE_RMODE_WEN FUNCMODE_RMODE_WEN_Msk
  66. #define FUNCMODE_CH0_ENABLE_Pos (8U)
  67. #define FUNCMODE_CH0_ENABLE_Msk (0x1U << FUNCMODE_CH0_ENABLE_Pos)
  68. #define FUNCMODE_CH0_ENABLE FUNCMODE_CH0_ENABLE_Msk
  69. #define FUNCMODE_CH1_ENABLE_Pos (9U)
  70. #define FUNCMODE_CH1_ENABLE_Msk (0x1U << FUNCMODE_CH1_ENABLE_Pos)
  71. #define FUNCMODE_CH1_ENABLE FUNCMODE_CH1_ENABLE_Msk
  72. #define FUNCMODE_CH2_ENABLE_Pos (10U)
  73. #define FUNCMODE_CH2_ENABLE_Msk (0x1U << FUNCMODE_CH2_ENABLE_Pos)
  74. #define FUNCMODE_CH2_ENABLE FUNCMODE_CH2_ENABLE_Msk
  75. #define FUNCMODE_CH3_ENABLE_Pos (11U)
  76. #define FUNCMODE_CH3_ENABLE_Msk (0x1U << FUNCMODE_CH3_ENABLE_Pos)
  77. #define FUNCMODE_CH3_ENABLE FUNCMODE_CH3_ENABLE_Msk
  78. #define FUNCMODE_CH4_ENABLE_Pos (12U)
  79. #define FUNCMODE_CH4_ENABLE_Msk (0x1U << FUNCMODE_CH4_ENABLE_Pos)
  80. #define FUNCMODE_CH4_ENABLE FUNCMODE_CH4_ENABLE_Msk
  81. /* IISCNFIN, offset: 0x08 */
  82. #define CNFIN_RSAFS_Pos (0U)
  83. #define CNFIN_RSAFS_Msk (0x3U << CNFIN_RSAFS_Pos)
  84. #define CNFIN_RSAFS_I2S (0x0U << CNFIN_RSAFS_Pos)
  85. #define CNFIN_RSAFS_RIGHT_JUSTIFIED (0x1U << CNFIN_RSAFS_Pos)
  86. #define CNFIN_RSAFS_LEFT_JUSTIFIED (0x2U << CNFIN_RSAFS_Pos)
  87. #define CNFIN_RSAFS_PCM (0x3U << CNFIN_RSAFS_Pos)
  88. #define CNFIN_RALOLRC_Pos (2U)
  89. #define CNFIN_RALOLRC_Msk (0x1U << CNFIN_RALOLRC_Pos)
  90. #define CNFIN_RALOLRC_HIGHFORLEFT CNFIN_RALOLRC_Msk
  91. #define CNFIN_RVOICEEN_Pos (4U)
  92. #define CNFIN_RVOICEEN_Msk (0x1U << CNFIN_RVOICEEN_Pos)
  93. #define CNFIN_RVOICEEN_MONO CNFIN_RVOICEEN_Msk
  94. #define CNFIN_RX_CH_SEL_Pos (5U)
  95. #define CNFIN_RX_CH_SEL_Msk (0x1U << CNFIN_RX_CH_SEL_Pos)
  96. #define CNFIN_RX_CH_SEL_LEFT CNFIN_RX_CH_SEL_Msk
  97. #define CNFIN_I2S_RXMODE_Pos (8U)
  98. #define CNFIN_I2S_RXMODE_Msk (0x1U << CNFIN_I2S_RXMODE_Pos)
  99. #define CNFIN_I2S_RXMODE_MASTER_MODE CNFIN_I2S_RXMODE_Msk
  100. #define CNFIN_I2S_RX_CLK_SEL_Pos (9U)
  101. #define CNFIN_I2S_RX_CLK_SEL_Msk (0x1U << CNFIN_I2S_RX_CLK_SEL_Pos)
  102. #define CNFIN_I2S_RX_CLK_SEL_MCLK CNFIN_I2S_RX_CLK_SEL_Msk
  103. #define CNFIN_I2S_RDELAY_Pos (12U)
  104. #define CNFIN_I2S_RDELAY_Msk (0x3U << CNFIN_I2S_RDELAY_Pos)
  105. #define CNFIN_I2S_RDELAY_NO_DELAY (0x0U << CNFIN_I2S_RDELAY_Pos)
  106. #define CNFIN_I2S_RDELAY_1_DELAY (0x1U << CNFIN_I2S_RDELAY_Pos)
  107. #define CNFIN_I2S_RDELAY_2_DELAY (0x2U << CNFIN_I2S_RDELAY_Pos)
  108. #define CNFIN_I2S_RDELAY_3_DELAY (0x3U << CNFIN_I2S_RDELAY_Pos)
  109. /* FSSTA , offset: 0x0C */
  110. #define FSSTA_AIRAD_Pos (0U)
  111. #define FSSTA_AIRAD_Msk (0x1U << FSSTA_AIRAD_Pos)
  112. #define FSSTA_AIRAD FSSTA_AIRAD_Msk
  113. #define FSSTA_AFR_Pos (4U)
  114. #define FSSTA_AFR_Msk (0x3U << FSSTA_AFR_Pos)
  115. #define FSSTA_AFR_88_2KSPS (0x0U << FSSTA_AFR_Pos)
  116. #define FSSTA_AFR_96KSPS (0x1U << FSSTA_AFR_Pos)
  117. #define FSSTA_AFR_64KSPS (0x2U << FSSTA_AFR_Pos)
  118. #define FSSTA_AFR_192KSPS (0x3U << FSSTA_AFR_Pos)
  119. #define FSSTA_ARS_Pos (6U)
  120. #define FSSTA_ARS_Msk (0x3U << FSSTA_ARS_Pos)
  121. #define FSSTA_ARS_1 (0x0U << FSSTA_ARS_Pos)
  122. #define FSSTA_ARS_0_5 (0x1U << FSSTA_ARS_Pos)
  123. #define FSSTA_ARS_0_25 (0x2U << FSSTA_ARS_Pos)
  124. #define FSSTA_ARS_0_125 (0x3U << FSSTA_ARS_Pos)
  125. #define FSSTA_DATAWTH_Pos (8U)
  126. #define FSSTA_DATAWTH_Msk (0xFU << FSSTA_DATAWTH_Pos)
  127. #define FSSTA_SCLK_SEL_Pos (12U)
  128. #define FSSTA_SCLK_SEL_Msk (0x3U << FSSTA_SCLK_SEL_Pos)
  129. #define FSSTA_SCLK_SEL_32 (0x0U << FSSTA_SCLK_SEL_Pos)
  130. #define FSSTA_SCLK_SEL_48 (0x1U << FSSTA_SCLK_SEL_Pos)
  131. #define FSSTA_SCLK_SEL_64 (0x2U << FSSTA_SCLK_SEL_Pos)
  132. #define FSSTA_SCLK_SEL_16 (0x3U << FSSTA_SCLK_SEL_Pos)
  133. #define FSSTA_MCLK_SEL_Pos (16U)
  134. #define FSSTA_MCLK_SEL_Msk (0x1U << FSSTA_MCLK_SEL_Pos)
  135. #define FSSTA_MCLK_SEL_384 FSSTA_MCLK_SEL_Msk
  136. /* IISCNFOUT, offset: 0x10 */
  137. #define IISCNFOUT_TSAFS_POS (0U)
  138. #define IISCNFOUT_TSAFS_MSK (0x3U << IISCNFOUT_TSAFS_POS)
  139. #define IISCNFOUT_TSAFS_I2S (0x0U << IISCNFOUT_TSAFS_POS)
  140. #define IISCNFOUT_TSAFS_RIGHT_JUSTIFIED (0x1U << IISCNFOUT_TSAFS_POS)
  141. #define IISCNFOUT_TSAFS_LEFT_JUSTIFIED (0x2U << IISCNFOUT_TSAFS_POS)
  142. #define IISCNFOUT_TSAFS_PCM (0x3U << IISCNFOUT_TSAFS_POS)
  143. #define IISCNFOUT_TALOLRC_Pos (2U)
  144. #define IISCNFOUT_TALOLRC_Msk (0x1U << IISCNFOUT_TALOLRC_Pos)
  145. #define IISCNFOUT_TALOLRC_HIGHFORLEFT IISCNFOUT_TALOLRC_Msk
  146. #define IISCNFOUT_TX_VOICE_EN_Pos (3U)
  147. #define IISCNFOUT_TX_VOICE_EN_Msk (0x1U << IISCNFOUT_TX_VOICE_EN_Pos)
  148. #define IISCNFOUT_TX_VOICE_EN_MONO IISCNFOUT_TX_VOICE_EN_Msk
  149. #define IISCNFOUT_I2S_TXMODE_Pos (4U)
  150. #define IISCNFOUT_I2S_TXMODE_Msk (0x1U << IISCNFOUT_I2S_TXMODE_Pos)
  151. #define IISCNFOUT_I2S_TXMODE_SLAVE IISCNFOUT_I2S_TXMODE_Msk
  152. #define IISCNFOUT_TX_CLK_SEL_Pos (5U)
  153. #define IISCNFOUT_TX_CLK_SEL_Msk (0x1U << IISCNFOUT_TX_CLK_SEL_Pos)
  154. #define IISCNFOUT_TX_CLK_SEL_MCLK IISCNFOUT_TX_CLK_SEL_Msk
  155. /* FADTLR, offset: 0x14 */
  156. #define FADTLR_96FTR_Pos (0U)
  157. #define FADTLR_96FTR_Msk (0x3FU << FADTLR_96FTR_Pos)
  158. #define FADTLR_88FTR_Pos (8U)
  159. #define FADTLR_88FTR_Msk (0x3FU << FADTLR_88FTR_Pos)
  160. #define FADTLR_64FTR_Pos (16U)
  161. #define FADTLR_64FTR_Msk (0x3FU << FADTLR_64FTR_Pos)
  162. #define FADTLR_192FTR_Pos (24U)
  163. #define FADTLR_192FTR_Msk (0x3FU << FADTLR_192FTR_Pos)
  164. /* SCCR, offset: 0x18 */
  165. #define SCCR_RVCCR_Pos (0U)
  166. #define SCCR_RVCCR_Msk (0x1FU << SCCR_RVCCR_Pos)
  167. #define SCCR_SSRCR_Pos (5U)
  168. #define SCCR_SSRCR_Msk (0x3U << SCCR_SSRCR_Pos)
  169. #define SCCR_SSRCR_NO_COMPRESS (0x0U << SCCR_SSRCR_Pos)
  170. #define SCCR_SSRCR_ONE_COMPRESS (0x1U << SCCR_SSRCR_Pos)
  171. #define SCCR_SSRCR_THREE_COMPRESS (0x2U << SCCR_SSRCR_Pos)
  172. #define SCCR_TVCCR_Pos (8U)
  173. #define SCCR_TVCCR_Msk (0x3U << SCCR_TVCCR_Pos)
  174. #define SCCR_TVCCR_NO_COMPRESS (0x0U << SCCR_TVCCR_Pos)
  175. #define SCCR_TVCCR_ONE_COMPRESS (0x1U << SCCR_TVCCR_Pos)
  176. #define SCCR_TVCCR_THREE_COMPRESS (0x2U << SCCR_TVCCR_Pos)
  177. /* TXFTLR, offset: 0x1C */
  178. #define TXFTLR_TFT_Pos (0U)
  179. #define TXFTLR_TFT_Msk (0xFU << TXFTLR_TFT_Pos)
  180. /* RXFTLR, offset: 0x20 */
  181. #define RXFTLR_RFT_Pos (0U)
  182. #define RXFTLR_RFT_Msk (0xFU << RXFTLR_RFT_Pos)
  183. /* TXFLR, offset: 0x24 */
  184. #define TXFLR_TXTFL_Pos (0U)
  185. /* RXFLR, offset: 0x28 */
  186. #define RXFLR_RXTFL_Pos (0U)
  187. /* SR, offset: 0x2C */
  188. #define SR_RXBUSY_Pos (0U)
  189. #define SR_RXBUSY_Msk (0x1U << SR_RXBUSY_Pos)
  190. #define SR_RXBUSY_STATUS SR_RXBUSY_Msk
  191. #define SR_TXBUSY_Pos (1U)
  192. #define SR_TXBUSY_Msk (0x1U << SR_TXBUSY_Pos)
  193. #define SR_TXBUSY_STATUS SR_TXBUSY_Msk
  194. #define SR_TFNF_Pos (2U)
  195. #define SR_TFNF_Msk (0x1U << SR_TFNF_Pos)
  196. #define SR_TFNF_TX_FIFO_NOT_FULL SR_TFNF_Msk
  197. #define SR_TFE_Pos (3U)
  198. #define SR_TFE_Msk (0x1U << SR_TFE_Pos)
  199. #define SR_TFE_TX_FIFO_EMPTY SR_TFE_Msk
  200. #define SR_RFNE_Pos (4U)
  201. #define SR_RFNE_Msk (0x1U << SR_RFNE_Pos)
  202. #define SR_RFNE_RX_FIFO_NOT_EMPTY SR_RFNE_Msk
  203. #define SR_RFF_Pos (5U)
  204. #define SR_RFF_Msk (0x1U << SR_RFF_Pos)
  205. #define SR_RFF_RX_FIFO_FULL SR_RFF_Msk
  206. /* IMR, offset: 0x30 */
  207. #define IMR_WADEM_Pos (0U)
  208. #define IMR_WADEM_Msk (0x1U << IMR_WADEM_Pos)
  209. #define IMR_WADEM_INTR_MSK IMR_WADEM_Msk
  210. #define IMR_TXUIRM_Pos (1U)
  211. #define IMR_TXUIRM_Msk (0x1U << IMR_TXUIRM_Pos)
  212. #define IMR_TXUIRM_INTR_MSK IMR_TXUIRM_Msk
  213. #define IMR_TXOIM_Pos (2U)
  214. #define IMR_TXOIM_Msk (0x1U << IMR_TXOIM_Pos)
  215. #define IMR_TXOIM_INTR_MSK IMR_TXOIM_Msk
  216. #define IMR_RXUIM_Pos (3U)
  217. #define IMR_RXUIM_Msk (0x1U << IMR_RXUIM_Pos)
  218. #define IMR_RXUIM_INTR_MSK IMR_RXUIM_Msk
  219. #define IMR_RXOIM_Pos (4U)
  220. #define IMR_RXOIM_Msk (0x1U << IMR_RXOIM_Pos)
  221. #define IMR_RXOIM_INTR_MSK IMR_RXOIM_Msk
  222. #define IMR_TXEIM_Pos (5U)
  223. #define IMR_TXEIM_Msk (0x1U << IMR_TXEIM_Pos)
  224. #define IMR_TXEIM_INTR_MSK IMR_TXEIM_Msk
  225. #define IMR_RXFIM_Pos (6U)
  226. #define IMR_RXFIM_Msk (0x1U << IMR_RXFIM_Pos)
  227. #define IMR_RXFIM_INTR_MSK IMR_RXFIM_Msk
  228. #define IMR_IRBFCM_Pos (7U)
  229. #define IMR_IRBFCM_Msk (0x1U << IMR_IRBFCM_Pos)
  230. #define IMR_IRBFCM_INTR_MSK IMR_IRBFCM_Msk
  231. #define IMR_ITBFCM_Pos (8U)
  232. #define IMR_ITBFCM_Msk (0x1U << IMR_ITBFCM_Pos)
  233. #define IMR_ITBFCM_INTR_MSK IMR_ITBFCM_Msk
  234. #define IMR_IFSCM_Pos (9U)
  235. #define IMR_IFSCM_Msk (0x1U << IMR_IFSCM_Pos)
  236. #define IMR_IFSCM_INTR_MSK IMR_IFSCM_Msk
  237. /* ISR, offset: 0x34 */
  238. #define ISR_WADES_Pos (0U)
  239. #define ISR_WADES_Msk (0x1U << ISR_WADES_Pos)
  240. #define ISR_WADES_STATUS ISR_WADES_Msk
  241. #define ISR_TXUIRS_Pos (1U)
  242. #define ISR_TXUIRS_Msk (0x1U << ISR_TXUIRS_Pos)
  243. #define ISR_TXUIRS_STATUS ISR_TXUIRS_Msk
  244. #define ISR_TXOIS_Pos (2U)
  245. #define ISR_TXOIS_Msk (0x1U << ISR_TXOIS_Pos)
  246. #define ISR_TXOIS_STATUS ISR_TXOIS_Msk
  247. #define ISR_RXUIS_Pos (3U)
  248. #define ISR_RXUIS_Msk (0x1U << ISR_RXUIS_Pos)
  249. #define ISR_RXUIS_STATUS ISR_RXUIS_Msk
  250. #define ISR_RXOIS_Pos (4U)
  251. #define ISR_RXOIS_Msk (0x1U << ISR_RXOIS_Pos)
  252. #define ISR_RXOIS_STATUS ISR_RXOIS_Msk
  253. #define ISR_TXEIS_Pos (5U)
  254. #define ISR_TXEIS_Msk (0x1U << ISR_TXEIS_Pos)
  255. #define ISR_TXEIS_STATUS ISR_TXEIS_Msk
  256. #define ISR_RXFIS_Pos (6U)
  257. #define ISR_RXFIS_Msk (0x1U << ISR_RXFIS_Pos)
  258. #define ISR_RXFIS_STATUS ISR_RXFIS_Msk
  259. #define ISR_IRBFCS_Pos (7U)
  260. #define ISR_IRBFCS_Msk (0x1U << ISR_IRBFCS_Pos)
  261. #define ISR_IRBFCS_STATUS ISR_IRBFCS_Msk
  262. #define ISR_ITBFCS_Pos (8U)
  263. #define ISR_ITBFCS_Msk (0x1U << ISR_ITBFCS_Pos)
  264. #define ISR_ITBFCS_STATUS ISR_ITBFCS_Msk
  265. #define ISR_IFSCS_Pos (9U)
  266. #define ISR_IFSCS_Msk (0x1U << ISR_IFSCS_Pos)
  267. #define ISR_IFSCS_STATUS ISR_IFSCS_Msk
  268. /* RISR, offset: 0x38 */
  269. #define RISR_RWADES_Pos (0U)
  270. #define RISR_RWADES_Msk (0x1U << RISR_RWADES_Pos)
  271. #define RISR_RWADES_RAW RISR_RWADES_Msk
  272. #define RISR_TXUIR_Pos (1U)
  273. #define RISR_TXUIR_Msk (0x1U << RISR_TXUIR_Pos)
  274. #define RISR_TXUIR_RAW RISR_TXUIR_Msk
  275. #define RISR_TXOIR_Pos (2U)
  276. #define RISR_TXOIR_Msk (0x1U << RISR_TXOIR_Pos)
  277. #define RISR_TXOIR_RAW RISR_TXOIR_Msk
  278. #define RISR_RXUIR_Pos (3U)
  279. #define RISR_RXUIR_Msk (0x1U << RISR_RXUIR_Pos)
  280. #define RISR_RXUIR_RAW RISR_RXUIR_Msk
  281. #define RISR_RXOIR_Pos (4U)
  282. #define RISR_RXOIR_Msk (0x1U << RISR_RXOIR_Pos)
  283. #define RISR_RXOIR_RAW RISR_RXOIR_Msk
  284. #define RISR_TXEIR_Pos (5U)
  285. #define RISR_TXEIR_Msk (0x1U << RISR_TXEIR_Pos)
  286. #define RISR_TXEIR_RAW RISR_TXEIR_Msk
  287. #define RISR_RXFIR_Pos (6U)
  288. #define RISR_RXFIR_Msk (0x1U << RISR_RXFIR_Pos)
  289. #define RISR_RXFIR_RAW RISR_RXFIR_Msk
  290. #define RISR_RIRBFCS_Pos (7U)
  291. #define RISR_RIRBFCS_Msk (0x1U << RISR_RIRBFCS_Pos)
  292. #define RISR_RIRBFCS_RAW RISR_RIRBFCS_Msk
  293. #define RISR_RITBFCS_Pos (8U)
  294. #define RISR_RITBFCS_Msk (0x1U << RISR_RITBFCS_Pos)
  295. #define RISR_RITBFCS_RAW RISR_RITBFCS_Msk
  296. #define RISR_RIFSCS_Pos (9U)
  297. #define RISR_RIFSCS_Msk (0x1U << RISR_RIFSCS_Pos)
  298. #define RISR_RIFSCS_RAW RISR_RIFSCS_Msk
  299. /* ICR, offset: 0x3C */
  300. #define ICR_CWADEC_Pos (0U)
  301. #define ICR_CWADEC_Msk (0x1U << ICR_CWADEC_Pos)
  302. #define ICR_CWADEC_CLEAR ICR_CWADEC_Msk
  303. #define ICR_TXUIC_Pos (1U)
  304. #define ICR_TXUIC_Msk (0x1U << ICR_TXUIC_Pos)
  305. #define ICR_TXUIC_CLEAR ICR_TXUIC_Msk
  306. #define ICR_TXOIC_Pos (2U)
  307. #define ICR_TXOIC_Msk (0x1U << ICR_TXOIC_Pos)
  308. #define ICR_TXOIC_CLEAR ICR_TXOIC_Msk
  309. #define ICR_RXUIC_Pos (3U)
  310. #define ICR_RXUIC_Msk (0x1U << ICR_RXUIC_Pos)
  311. #define ICR_RXUIC_CLEAR ICR_RXUIC_Msk
  312. #define ICR_RXOIC_Pos (4U)
  313. #define ICR_RXOIC_Msk (0x1U << ICR_RXOIC_Pos)
  314. #define ICR_RXOIC_CLEAR ICR_RXOIC_Msk
  315. #define ICR_TXEIC_Pos (5U)
  316. #define ICR_TXEIC_Msk (0x1U << ICR_TXEIC_Pos)
  317. #define ICR_TXEIC_CLEAR ICR_TXEIC_Msk
  318. #define ICR_RXFIC_Pos (6U)
  319. #define ICR_RXFIC_Msk (0x1U << ICR_RXFIC_Pos)
  320. #define ICR_RXFIC_CLEAR ICR_RXFIC_Msk
  321. #define ICR_CRIRBFC_Pos (7U)
  322. #define ICR_CRIRBFC_Msk (0x1U << ICR_CRIRBFC_Pos)
  323. #define ICR_CRIRBFC_CLEAR ICR_CRIRBFC_Msk
  324. #define ICR_CRITBFC_Pos (8U)
  325. #define ICR_CRITBFC_Msk (0x1U << ICR_CRITBFC_Pos)
  326. #define ICR_CRITBFC_CLEAR ICR_CRITBFC_Msk
  327. #define ICR_CRIFSC_Pos (9U)
  328. #define ICR_CRIFSC_Msk (0x1U << ICR_CRIFSC_Pos)
  329. #define ICR_CRIFSC_CLEAR ICR_CRIFSC_Msk
  330. /* DMACR, offset: 0x40 */
  331. #define DMACR_RDMAE_POS (0U)
  332. #define DMACR_RDMAE_MSK (0x1U << DMACR_RDMAE_POS)
  333. #define DMACR_RDMAE_EN DMACR_RDMAE_MSK
  334. #define DMACR_TDMAE_POS (1U)
  335. #define DMACR_TDMAE_MSK (0x1U << DMACR_TDMAE_POS)
  336. #define DMACR_TDMAE_EN DMACR_TDMAE_MSK
  337. /* DMATDLR, offset: 0x44 */
  338. #define DMATDLR_DMATDL_Pos (0U)
  339. #define DMATDLR_DMATDL_Msk (0x1FU << DMATDLR_DMATDL_Pos)
  340. /* DMARDLR, offset: 0x48 */
  341. #define DMARDLR_DMATDL_Pos (0U)
  342. #define DMARDLR_DMATDL_Msk (0x1FU << DMARDLR_DMATDL_Pos)
  343. /* DR, offset: 0x4C */
  344. #define DR_DR_Pos (0U)
  345. /* DIV0LEVEL, offset: 0x50 */
  346. #define DIV0LEVEL_DIV0_Pos (0U)
  347. #define DIV0LEVEL_DIV0_Msk (0XFFU << DIV0LEVEL_DIV0_Pos)
  348. /* DIV3LEVEL, offset: 0x54 */
  349. #define DIV3LEVEL_DIV3_Pos (0U)
  350. #define DIV0LEVEL_DIV3_Msk (0XFFU << DIV3LEVEL_DIV3_Pos)
  351. #define I2S_DATA_WIDTH_8BIT (0xFU << FSSTA_DATAWTH_Pos)
  352. #define I2S_DATA_8BIT_WIDTH_32BIT (0xEU << FSSTA_DATAWTH_Pos)
  353. #define I2S_DATA_WIDTH_16BIT (0U << FSSTA_DATAWTH_Pos)
  354. #define I2S_DATA_16BIT_WIDTH_32BIT (0x2U << FSSTA_DATAWTH_Pos)
  355. #define I2S_DATA_WIDTH_24BIT (0x5U << FSSTA_DATAWTH_Pos)
  356. #define I2S_DATA_24BIT_WIDTH_32BIT (0x7U << FSSTA_DATAWTH_Pos)
  357. #define I2S_DATA_WIDTH_32BIT (0xAU << FSSTA_DATAWTH_Pos)
  358. #define I2S_DATA_WIDTH_32BIT_OUPUT (0x8U << FSSTA_DATAWTH_Pos)
  359. #define TXFIFO_IRQ_TH (0x8U)
  360. #define RXFIFO_IRQ_TH (0x20U)
  361. #define I2S_MAX_FIFO (0x20U)
  362. /* AUDIO SYS DIV SEL REG, offset: 0x4 */
  363. #define CPR_AUDIO_DIV1_SEL_POS (12U)
  364. #define CPR_AUDIO_DIV1_SEL_MSK (0x1FU << CPR_AUDIO_DIV1_SEL_POS)
  365. #define CPR_AUDIO_DIV1_SEL(X) (X << CPR_AUDIO_DIV1_SEL_POS)
  366. /* AUDIO SYS CLK SEL REG, offset: 0x8 */
  367. #define CPR_I2S0_SRC_SEL_POS (0U)
  368. #define CPR_I2S0_SRC_SEL_MSK (0x3U << CPR_I2S0_SRC_SEL_POS)
  369. #define CPR_I2S0_SRC_SEL(X) (X << CPR_I2S0_SRC_SEL_POS)
  370. #define CPR_I2S0_SRC_SEL_24M (0x1U << AUDIOSYS_I2S0_SRC_SEL_POS)
  371. #define CPR_I2S0_SRC_SEL_AUDIO_DIVCLK1 (0x2U << AUDIOSYS_I2S0_SRC_SEL_POS)
  372. #define CPR_I2S1_SRC_SEL_POS (4U)
  373. #define CPR_I2S1_SRC_SEL_MSK (0x3U << CPR_I2S1_SRC_SEL_POS)
  374. #define CPR_I2S1_SRC_SEL(X) (X << CPR_I2S1_SRC_SEL_POS)
  375. #define CPR_I2S1_SRC_SEL_24M (0x1U << AUDIOSYS_I2S1_SRC_SEL_POS)
  376. #define CPR_I2S1_SRC_SEL_AUDIO_DIVCLK1 (0x2U << AUDIOSYS_I2S1_SRC_SEL_POS)
  377. #define CPR_I2S2_SRC_SEL_POS (8U)
  378. #define CPR_I2S2_SRC_SEL_MSK (0x3U << CPR_I2S2_SRC_SEL_POS)
  379. #define CPR_I2S2_SRC_SEL(X) (X << CPR_I2S2_SRC_SEL_POS)
  380. #define CPR_I2S2_SRC_SEL_24M (0x1U << AUDIOSYS_I2S2_SRC_SEL_POS)
  381. #define CPR_I2S2_SRC_SEL_AUDIO_DIVCLK1 (0x2U << AUDIOSYS_I2S2_SRC_SEL_POS)
  382. struct light_i2s_priv {
  383. void __iomem *base;
  384. phys_addr_t phys;
  385. void __iomem *regs;
  386. struct regmap *regmap;
  387. struct regmap *audio_pin_regmap;
  388. struct regmap *audio_cpr_regmap;
  389. struct clk *clk;
  390. struct snd_dmaengine_dai_dma_data dma_params_tx;
  391. struct snd_dmaengine_dai_dma_data dma_params_rx;
  392. u32 fmt;
  393. unsigned int dai_fmt;
  394. u32 dma_maxburst;
  395. unsigned int cfg_off;
  396. struct device *dev;
  397. char name[16];
  398. int chan_num:16;
  399. unsigned int clk_master:1;
  400. };
  401. #endif /* _LIGHT_I2S_H */