dwc3-pci.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /**
  3. * dwc3-pci.c - PCI Specific glue layer
  4. *
  5. * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
  6. *
  7. * Authors: Felipe Balbi <balbi@ti.com>,
  8. * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/slab.h>
  13. #include <linux/pci.h>
  14. #include <linux/workqueue.h>
  15. #include <linux/pm_runtime.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/gpio/consumer.h>
  18. #include <linux/gpio/machine.h>
  19. #include <linux/acpi.h>
  20. #include <linux/delay.h>
  21. #define PCI_DEVICE_ID_INTEL_BYT 0x0f37
  22. #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e
  23. #define PCI_DEVICE_ID_INTEL_BSW 0x22b7
  24. #define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30
  25. #define PCI_DEVICE_ID_INTEL_SPTH 0xa130
  26. #define PCI_DEVICE_ID_INTEL_BXT 0x0aaa
  27. #define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa
  28. #define PCI_DEVICE_ID_INTEL_APL 0x5aaa
  29. #define PCI_DEVICE_ID_INTEL_KBP 0xa2b0
  30. #define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee
  31. #define PCI_DEVICE_ID_INTEL_CMLH 0x06ee
  32. #define PCI_DEVICE_ID_INTEL_GLK 0x31aa
  33. #define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee
  34. #define PCI_DEVICE_ID_INTEL_CNPH 0xa36e
  35. #define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0
  36. #define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee
  37. #define PCI_DEVICE_ID_INTEL_EHLLP 0x4b7e
  38. #define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee
  39. #define PCI_DEVICE_ID_INTEL_TGPH 0x43ee
  40. #define PCI_DEVICE_ID_INTEL_JSP 0x4dee
  41. #define PCI_DEVICE_ID_INTEL_ADLP 0x51ee
  42. #define PCI_DEVICE_ID_INTEL_ADLS 0x7ae1
  43. #define PCI_DEVICE_ID_INTEL_TGL 0x9a15
  44. #define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
  45. #define PCI_INTEL_BXT_FUNC_PMU_PWR 4
  46. #define PCI_INTEL_BXT_STATE_D0 0
  47. #define PCI_INTEL_BXT_STATE_D3 3
  48. #define GP_RWBAR 1
  49. #define GP_RWREG1 0xa0
  50. #define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17)
  51. /**
  52. * struct dwc3_pci - Driver private structure
  53. * @dwc3: child dwc3 platform_device
  54. * @pci: our link to PCI bus
  55. * @guid: _DSM GUID
  56. * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
  57. * @wakeup_work: work for asynchronous resume
  58. */
  59. struct dwc3_pci {
  60. struct platform_device *dwc3;
  61. struct pci_dev *pci;
  62. guid_t guid;
  63. unsigned int has_dsm_for_pm:1;
  64. struct work_struct wakeup_work;
  65. };
  66. static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
  67. static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
  68. static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
  69. { "reset-gpios", &reset_gpios, 1 },
  70. { "cs-gpios", &cs_gpios, 1 },
  71. { },
  72. };
  73. static struct gpiod_lookup_table platform_bytcr_gpios = {
  74. .dev_id = "0000:00:16.0",
  75. .table = {
  76. GPIO_LOOKUP("INT33FC:00", 54, "cs", GPIO_ACTIVE_HIGH),
  77. GPIO_LOOKUP("INT33FC:02", 14, "reset", GPIO_ACTIVE_HIGH),
  78. {}
  79. },
  80. };
  81. static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci)
  82. {
  83. void __iomem *reg;
  84. u32 value;
  85. reg = pcim_iomap(pci, GP_RWBAR, 0);
  86. if (!reg)
  87. return -ENOMEM;
  88. value = readl(reg + GP_RWREG1);
  89. if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE))
  90. goto unmap; /* ULPI refclk already enabled */
  91. value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE;
  92. writel(value, reg + GP_RWREG1);
  93. /* This comes from the Intel Android x86 tree w/o any explanation */
  94. msleep(100);
  95. unmap:
  96. pcim_iounmap(pci, reg);
  97. return 0;
  98. }
  99. static const struct property_entry dwc3_pci_intel_properties[] = {
  100. PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
  101. PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
  102. {}
  103. };
  104. static const struct property_entry dwc3_pci_mrfld_properties[] = {
  105. PROPERTY_ENTRY_STRING("dr_mode", "otg"),
  106. PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"),
  107. PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
  108. PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
  109. PROPERTY_ENTRY_BOOL("snps,usb2-gadget-lpm-disable"),
  110. PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
  111. {}
  112. };
  113. static const struct property_entry dwc3_pci_amd_properties[] = {
  114. PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
  115. PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
  116. PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
  117. PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
  118. PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
  119. PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
  120. PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
  121. PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
  122. PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
  123. PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
  124. PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
  125. /* FIXME these quirks should be removed when AMD NL tapes out */
  126. PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
  127. PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
  128. PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
  129. PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
  130. {}
  131. };
  132. static const struct software_node dwc3_pci_intel_swnode = {
  133. .properties = dwc3_pci_intel_properties,
  134. };
  135. static const struct software_node dwc3_pci_intel_mrfld_swnode = {
  136. .properties = dwc3_pci_mrfld_properties,
  137. };
  138. static const struct software_node dwc3_pci_amd_swnode = {
  139. .properties = dwc3_pci_amd_properties,
  140. };
  141. static int dwc3_pci_quirks(struct dwc3_pci *dwc)
  142. {
  143. struct pci_dev *pdev = dwc->pci;
  144. if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
  145. if (pdev->device == PCI_DEVICE_ID_INTEL_BXT ||
  146. pdev->device == PCI_DEVICE_ID_INTEL_BXT_M ||
  147. pdev->device == PCI_DEVICE_ID_INTEL_EHLLP) {
  148. guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid);
  149. dwc->has_dsm_for_pm = true;
  150. }
  151. if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
  152. struct gpio_desc *gpio;
  153. int ret;
  154. /* On BYT the FW does not always enable the refclock */
  155. ret = dwc3_byt_enable_ulpi_refclock(pdev);
  156. if (ret)
  157. return ret;
  158. ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
  159. acpi_dwc3_byt_gpios);
  160. if (ret)
  161. dev_dbg(&pdev->dev, "failed to add mapping table\n");
  162. /*
  163. * A lot of BYT devices lack ACPI resource entries for
  164. * the GPIOs, add a fallback mapping to the reference
  165. * design GPIOs which all boards seem to use.
  166. */
  167. gpiod_add_lookup_table(&platform_bytcr_gpios);
  168. /*
  169. * These GPIOs will turn on the USB2 PHY. Note that we have to
  170. * put the gpio descriptors again here because the phy driver
  171. * might want to grab them, too.
  172. */
  173. gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
  174. if (IS_ERR(gpio))
  175. return PTR_ERR(gpio);
  176. gpiod_set_value_cansleep(gpio, 1);
  177. gpiod_put(gpio);
  178. gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
  179. if (IS_ERR(gpio))
  180. return PTR_ERR(gpio);
  181. if (gpio) {
  182. gpiod_set_value_cansleep(gpio, 1);
  183. gpiod_put(gpio);
  184. usleep_range(10000, 11000);
  185. }
  186. }
  187. }
  188. return 0;
  189. }
  190. #ifdef CONFIG_PM
  191. static void dwc3_pci_resume_work(struct work_struct *work)
  192. {
  193. struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work);
  194. struct platform_device *dwc3 = dwc->dwc3;
  195. int ret;
  196. ret = pm_runtime_get_sync(&dwc3->dev);
  197. if (ret) {
  198. pm_runtime_put_sync_autosuspend(&dwc3->dev);
  199. return;
  200. }
  201. pm_runtime_mark_last_busy(&dwc3->dev);
  202. pm_runtime_put_sync_autosuspend(&dwc3->dev);
  203. }
  204. #endif
  205. static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
  206. {
  207. struct dwc3_pci *dwc;
  208. struct resource res[2];
  209. int ret;
  210. struct device *dev = &pci->dev;
  211. ret = pcim_enable_device(pci);
  212. if (ret) {
  213. dev_err(dev, "failed to enable pci device\n");
  214. return -ENODEV;
  215. }
  216. pci_set_master(pci);
  217. dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
  218. if (!dwc)
  219. return -ENOMEM;
  220. dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
  221. if (!dwc->dwc3)
  222. return -ENOMEM;
  223. memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
  224. res[0].start = pci_resource_start(pci, 0);
  225. res[0].end = pci_resource_end(pci, 0);
  226. res[0].name = "dwc_usb3";
  227. res[0].flags = IORESOURCE_MEM;
  228. res[1].start = pci->irq;
  229. res[1].name = "dwc_usb3";
  230. res[1].flags = IORESOURCE_IRQ;
  231. ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
  232. if (ret) {
  233. dev_err(dev, "couldn't add resources to dwc3 device\n");
  234. goto err;
  235. }
  236. dwc->pci = pci;
  237. dwc->dwc3->dev.parent = dev;
  238. ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));
  239. ret = device_add_software_node(&dwc->dwc3->dev, (void *)id->driver_data);
  240. if (ret < 0)
  241. goto err;
  242. ret = dwc3_pci_quirks(dwc);
  243. if (ret)
  244. goto err;
  245. ret = platform_device_add(dwc->dwc3);
  246. if (ret) {
  247. dev_err(dev, "failed to register dwc3 device\n");
  248. goto err;
  249. }
  250. device_init_wakeup(dev, true);
  251. pci_set_drvdata(pci, dwc);
  252. pm_runtime_put(dev);
  253. #ifdef CONFIG_PM
  254. INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work);
  255. #endif
  256. return 0;
  257. err:
  258. device_remove_software_node(&dwc->dwc3->dev);
  259. platform_device_put(dwc->dwc3);
  260. return ret;
  261. }
  262. static void dwc3_pci_remove(struct pci_dev *pci)
  263. {
  264. struct dwc3_pci *dwc = pci_get_drvdata(pci);
  265. struct pci_dev *pdev = dwc->pci;
  266. if (pdev->device == PCI_DEVICE_ID_INTEL_BYT)
  267. gpiod_remove_lookup_table(&platform_bytcr_gpios);
  268. #ifdef CONFIG_PM
  269. cancel_work_sync(&dwc->wakeup_work);
  270. #endif
  271. device_init_wakeup(&pci->dev, false);
  272. pm_runtime_get(&pci->dev);
  273. device_remove_software_node(&dwc->dwc3->dev);
  274. platform_device_unregister(dwc->dwc3);
  275. }
  276. static const struct pci_device_id dwc3_pci_id_table[] = {
  277. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW),
  278. (kernel_ulong_t) &dwc3_pci_intel_swnode, },
  279. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT),
  280. (kernel_ulong_t) &dwc3_pci_intel_swnode, },
  281. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD),
  282. (kernel_ulong_t) &dwc3_pci_intel_mrfld_swnode, },
  283. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP),
  284. (kernel_ulong_t) &dwc3_pci_intel_swnode, },
  285. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH),
  286. (kernel_ulong_t) &dwc3_pci_intel_swnode, },
  287. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP),
  288. (kernel_ulong_t) &dwc3_pci_intel_swnode, },
  289. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH),
  290. (kernel_ulong_t) &dwc3_pci_intel_swnode, },
  291. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT),
  292. (kernel_ulong_t) &dwc3_pci_intel_swnode, },
  293. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M),
  294. (kernel_ulong_t) &dwc3_pci_intel_swnode, },
  295. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL),
  296. (kernel_ulong_t) &dwc3_pci_intel_swnode, },
  297. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP),
  298. (kernel_ulong_t) &dwc3_pci_intel_swnode, },
  299. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK),
  300. (kernel_ulong_t) &dwc3_pci_intel_swnode, },
  301. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP),
  302. (kernel_ulong_t) &dwc3_pci_intel_swnode, },
  303. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH),
  304. (kernel_ulong_t) &dwc3_pci_intel_swnode, },
  305. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPV),
  306. (kernel_ulong_t) &dwc3_pci_intel_swnode, },
  307. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP),
  308. (kernel_ulong_t) &dwc3_pci_intel_swnode, },
  309. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_EHLLP),
  310. (kernel_ulong_t) &dwc3_pci_intel_swnode },
  311. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP),
  312. (kernel_ulong_t) &dwc3_pci_intel_swnode, },
  313. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPH),
  314. (kernel_ulong_t) &dwc3_pci_intel_swnode, },
  315. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_JSP),
  316. (kernel_ulong_t) &dwc3_pci_intel_swnode, },
  317. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLP),
  318. (kernel_ulong_t) &dwc3_pci_intel_swnode, },
  319. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLS),
  320. (kernel_ulong_t) &dwc3_pci_intel_swnode, },
  321. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL),
  322. (kernel_ulong_t) &dwc3_pci_intel_swnode, },
  323. { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB),
  324. (kernel_ulong_t) &dwc3_pci_amd_swnode, },
  325. { } /* Terminating Entry */
  326. };
  327. MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
  328. #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP)
  329. static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
  330. {
  331. union acpi_object *obj;
  332. union acpi_object tmp;
  333. union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
  334. if (!dwc->has_dsm_for_pm)
  335. return 0;
  336. tmp.type = ACPI_TYPE_INTEGER;
  337. tmp.integer.value = param;
  338. obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid,
  339. 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
  340. if (!obj) {
  341. dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
  342. return -EIO;
  343. }
  344. ACPI_FREE(obj);
  345. return 0;
  346. }
  347. #endif /* CONFIG_PM || CONFIG_PM_SLEEP */
  348. #ifdef CONFIG_PM
  349. static int dwc3_pci_runtime_suspend(struct device *dev)
  350. {
  351. struct dwc3_pci *dwc = dev_get_drvdata(dev);
  352. if (device_can_wakeup(dev))
  353. return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
  354. return -EBUSY;
  355. }
  356. static int dwc3_pci_runtime_resume(struct device *dev)
  357. {
  358. struct dwc3_pci *dwc = dev_get_drvdata(dev);
  359. int ret;
  360. ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
  361. if (ret)
  362. return ret;
  363. queue_work(pm_wq, &dwc->wakeup_work);
  364. return 0;
  365. }
  366. #endif /* CONFIG_PM */
  367. #ifdef CONFIG_PM_SLEEP
  368. static int dwc3_pci_suspend(struct device *dev)
  369. {
  370. struct dwc3_pci *dwc = dev_get_drvdata(dev);
  371. return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
  372. }
  373. static int dwc3_pci_resume(struct device *dev)
  374. {
  375. struct dwc3_pci *dwc = dev_get_drvdata(dev);
  376. return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
  377. }
  378. #endif /* CONFIG_PM_SLEEP */
  379. static const struct dev_pm_ops dwc3_pci_dev_pm_ops = {
  380. SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
  381. SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
  382. NULL)
  383. };
  384. static struct pci_driver dwc3_pci_driver = {
  385. .name = "dwc3-pci",
  386. .id_table = dwc3_pci_id_table,
  387. .probe = dwc3_pci_probe,
  388. .remove = dwc3_pci_remove,
  389. .driver = {
  390. .pm = &dwc3_pci_dev_pm_ops,
  391. }
  392. };
  393. MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
  394. MODULE_LICENSE("GPL v2");
  395. MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
  396. module_pci_driver(dwc3_pci_driver);