drd.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * drd.c - DesignWare USB3 DRD Controller Dual-role support
  4. *
  5. * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com
  6. *
  7. * Authors: Roger Quadros <rogerq@ti.com>
  8. */
  9. #include <linux/extcon.h>
  10. #include <linux/of_graph.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/property.h>
  13. #include "debug.h"
  14. #include "core.h"
  15. #include "gadget.h"
  16. static void dwc3_otg_disable_events(struct dwc3 *dwc, u32 disable_mask)
  17. {
  18. u32 reg = dwc3_readl(dwc->regs, DWC3_OEVTEN);
  19. reg &= ~(disable_mask);
  20. dwc3_writel(dwc->regs, DWC3_OEVTEN, reg);
  21. }
  22. static void dwc3_otg_enable_events(struct dwc3 *dwc, u32 enable_mask)
  23. {
  24. u32 reg = dwc3_readl(dwc->regs, DWC3_OEVTEN);
  25. reg |= (enable_mask);
  26. dwc3_writel(dwc->regs, DWC3_OEVTEN, reg);
  27. }
  28. static void dwc3_otg_clear_events(struct dwc3 *dwc)
  29. {
  30. u32 reg = dwc3_readl(dwc->regs, DWC3_OEVT);
  31. dwc3_writel(dwc->regs, DWC3_OEVTEN, reg);
  32. }
  33. #define DWC3_OTG_ALL_EVENTS (DWC3_OEVTEN_XHCIRUNSTPSETEN | \
  34. DWC3_OEVTEN_DEVRUNSTPSETEN | DWC3_OEVTEN_HIBENTRYEN | \
  35. DWC3_OEVTEN_CONIDSTSCHNGEN | DWC3_OEVTEN_HRRCONFNOTIFEN | \
  36. DWC3_OEVTEN_HRRINITNOTIFEN | DWC3_OEVTEN_ADEVIDLEEN | \
  37. DWC3_OEVTEN_ADEVBHOSTENDEN | DWC3_OEVTEN_ADEVHOSTEN | \
  38. DWC3_OEVTEN_ADEVHNPCHNGEN | DWC3_OEVTEN_ADEVSRPDETEN | \
  39. DWC3_OEVTEN_ADEVSESSENDDETEN | DWC3_OEVTEN_BDEVBHOSTENDEN | \
  40. DWC3_OEVTEN_BDEVHNPCHNGEN | DWC3_OEVTEN_BDEVSESSVLDDETEN | \
  41. DWC3_OEVTEN_BDEVVBUSCHNGEN)
  42. static irqreturn_t dwc3_otg_thread_irq(int irq, void *_dwc)
  43. {
  44. struct dwc3 *dwc = _dwc;
  45. spin_lock(&dwc->lock);
  46. if (dwc->otg_restart_host) {
  47. dwc3_otg_host_init(dwc);
  48. dwc->otg_restart_host = false;
  49. }
  50. spin_unlock(&dwc->lock);
  51. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
  52. return IRQ_HANDLED;
  53. }
  54. static irqreturn_t dwc3_otg_irq(int irq, void *_dwc)
  55. {
  56. u32 reg;
  57. struct dwc3 *dwc = _dwc;
  58. irqreturn_t ret = IRQ_NONE;
  59. reg = dwc3_readl(dwc->regs, DWC3_OEVT);
  60. if (reg) {
  61. /* ignore non OTG events, we can't disable them in OEVTEN */
  62. if (!(reg & DWC3_OTG_ALL_EVENTS)) {
  63. dwc3_writel(dwc->regs, DWC3_OEVT, reg);
  64. return IRQ_NONE;
  65. }
  66. if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST &&
  67. !(reg & DWC3_OEVT_DEVICEMODE))
  68. dwc->otg_restart_host = true;
  69. dwc3_writel(dwc->regs, DWC3_OEVT, reg);
  70. ret = IRQ_WAKE_THREAD;
  71. }
  72. return ret;
  73. }
  74. static void dwc3_otgregs_init(struct dwc3 *dwc)
  75. {
  76. u32 reg;
  77. /*
  78. * Prevent host/device reset from resetting OTG core.
  79. * If we don't do this then xhci_reset (USBCMD.HCRST) will reset
  80. * the signal outputs sent to the PHY, the OTG FSM logic of the
  81. * core and also the resets to the VBUS filters inside the core.
  82. */
  83. reg = dwc3_readl(dwc->regs, DWC3_OCFG);
  84. reg |= DWC3_OCFG_SFTRSTMASK;
  85. dwc3_writel(dwc->regs, DWC3_OCFG, reg);
  86. /* Disable hibernation for simplicity */
  87. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  88. reg &= ~DWC3_GCTL_GBLHIBERNATIONEN;
  89. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  90. /*
  91. * Initialize OTG registers as per
  92. * Figure 11-4 OTG Driver Overall Programming Flow
  93. */
  94. /* OCFG.SRPCap = 0, OCFG.HNPCap = 0 */
  95. reg = dwc3_readl(dwc->regs, DWC3_OCFG);
  96. reg &= ~(DWC3_OCFG_SRPCAP | DWC3_OCFG_HNPCAP);
  97. dwc3_writel(dwc->regs, DWC3_OCFG, reg);
  98. /* OEVT = FFFF */
  99. dwc3_otg_clear_events(dwc);
  100. /* OEVTEN = 0 */
  101. dwc3_otg_disable_events(dwc, DWC3_OTG_ALL_EVENTS);
  102. /* OEVTEN.ConIDStsChngEn = 1. Instead we enable all events */
  103. dwc3_otg_enable_events(dwc, DWC3_OTG_ALL_EVENTS);
  104. /*
  105. * OCTL.PeriMode = 1, OCTL.DevSetHNPEn = 0, OCTL.HstSetHNPEn = 0,
  106. * OCTL.HNPReq = 0
  107. */
  108. reg = dwc3_readl(dwc->regs, DWC3_OCTL);
  109. reg |= DWC3_OCTL_PERIMODE;
  110. reg &= ~(DWC3_OCTL_DEVSETHNPEN | DWC3_OCTL_HSTSETHNPEN |
  111. DWC3_OCTL_HNPREQ);
  112. dwc3_writel(dwc->regs, DWC3_OCTL, reg);
  113. }
  114. static int dwc3_otg_get_irq(struct dwc3 *dwc)
  115. {
  116. struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
  117. int irq;
  118. irq = platform_get_irq_byname_optional(dwc3_pdev, "otg");
  119. if (irq > 0)
  120. goto out;
  121. if (irq == -EPROBE_DEFER)
  122. goto out;
  123. irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3");
  124. if (irq > 0)
  125. goto out;
  126. if (irq == -EPROBE_DEFER)
  127. goto out;
  128. irq = platform_get_irq(dwc3_pdev, 0);
  129. if (irq > 0)
  130. goto out;
  131. if (!irq)
  132. irq = -EINVAL;
  133. out:
  134. return irq;
  135. }
  136. void dwc3_otg_init(struct dwc3 *dwc)
  137. {
  138. u32 reg;
  139. /*
  140. * As per Figure 11-4 OTG Driver Overall Programming Flow,
  141. * block "Initialize GCTL for OTG operation".
  142. */
  143. /* GCTL.PrtCapDir=2'b11 */
  144. dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_OTG);
  145. /* GUSB2PHYCFG0.SusPHY=0 */
  146. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  147. reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
  148. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  149. /* Initialize OTG registers */
  150. dwc3_otgregs_init(dwc);
  151. }
  152. void dwc3_otg_exit(struct dwc3 *dwc)
  153. {
  154. /* disable all OTG IRQs */
  155. dwc3_otg_disable_events(dwc, DWC3_OTG_ALL_EVENTS);
  156. /* clear all events */
  157. dwc3_otg_clear_events(dwc);
  158. }
  159. /* should be called before Host controller driver is started */
  160. void dwc3_otg_host_init(struct dwc3 *dwc)
  161. {
  162. u32 reg;
  163. /* As per Figure 11-10 A-Device Flow Diagram */
  164. /* OCFG.HNPCap = 0, OCFG.SRPCap = 0. Already 0 */
  165. /*
  166. * OCTL.PeriMode=0, OCTL.TermSelDLPulse = 0,
  167. * OCTL.DevSetHNPEn = 0, OCTL.HstSetHNPEn = 0
  168. */
  169. reg = dwc3_readl(dwc->regs, DWC3_OCTL);
  170. reg &= ~(DWC3_OCTL_PERIMODE | DWC3_OCTL_TERMSELIDPULSE |
  171. DWC3_OCTL_DEVSETHNPEN | DWC3_OCTL_HSTSETHNPEN);
  172. dwc3_writel(dwc->regs, DWC3_OCTL, reg);
  173. /*
  174. * OCFG.DisPrtPwrCutoff = 0/1
  175. */
  176. reg = dwc3_readl(dwc->regs, DWC3_OCFG);
  177. reg &= ~DWC3_OCFG_DISPWRCUTTOFF;
  178. dwc3_writel(dwc->regs, DWC3_OCFG, reg);
  179. /*
  180. * OCFG.SRPCap = 1, OCFG.HNPCap = GHWPARAMS6.HNP_CAP
  181. * We don't want SRP/HNP for simple dual-role so leave
  182. * these disabled.
  183. */
  184. /*
  185. * OEVTEN.OTGADevHostEvntEn = 1
  186. * OEVTEN.OTGADevSessEndDetEvntEn = 1
  187. * We don't want HNP/role-swap so leave these disabled.
  188. */
  189. /* GUSB2PHYCFG.ULPIAutoRes = 1/0, GUSB2PHYCFG.SusPHY = 1 */
  190. if (!dwc->dis_u2_susphy_quirk) {
  191. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  192. reg |= DWC3_GUSB2PHYCFG_SUSPHY;
  193. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  194. }
  195. /* Set Port Power to enable VBUS: OCTL.PrtPwrCtl = 1 */
  196. reg = dwc3_readl(dwc->regs, DWC3_OCTL);
  197. reg |= DWC3_OCTL_PRTPWRCTL;
  198. dwc3_writel(dwc->regs, DWC3_OCTL, reg);
  199. }
  200. /* should be called after Host controller driver is stopped */
  201. static void dwc3_otg_host_exit(struct dwc3 *dwc)
  202. {
  203. u32 reg;
  204. /*
  205. * Exit from A-device flow as per
  206. * Figure 11-4 OTG Driver Overall Programming Flow
  207. */
  208. /*
  209. * OEVTEN.OTGADevBHostEndEvntEn=0, OEVTEN.OTGADevHNPChngEvntEn=0
  210. * OEVTEN.OTGADevSessEndDetEvntEn=0,
  211. * OEVTEN.OTGADevHostEvntEn = 0
  212. * But we don't disable any OTG events
  213. */
  214. /* OCTL.HstSetHNPEn = 0, OCTL.PrtPwrCtl=0 */
  215. reg = dwc3_readl(dwc->regs, DWC3_OCTL);
  216. reg &= ~(DWC3_OCTL_HSTSETHNPEN | DWC3_OCTL_PRTPWRCTL);
  217. dwc3_writel(dwc->regs, DWC3_OCTL, reg);
  218. }
  219. /* should be called before the gadget controller driver is started */
  220. static void dwc3_otg_device_init(struct dwc3 *dwc)
  221. {
  222. u32 reg;
  223. /* As per Figure 11-20 B-Device Flow Diagram */
  224. /*
  225. * OCFG.HNPCap = GHWPARAMS6.HNP_CAP, OCFG.SRPCap = 1
  226. * but we keep them 0 for simple dual-role operation.
  227. */
  228. reg = dwc3_readl(dwc->regs, DWC3_OCFG);
  229. /* OCFG.OTGSftRstMsk = 0/1 */
  230. reg |= DWC3_OCFG_SFTRSTMASK;
  231. dwc3_writel(dwc->regs, DWC3_OCFG, reg);
  232. /*
  233. * OCTL.PeriMode = 1
  234. * OCTL.TermSelDLPulse = 0/1, OCTL.HNPReq = 0
  235. * OCTL.DevSetHNPEn = 0, OCTL.HstSetHNPEn = 0
  236. */
  237. reg = dwc3_readl(dwc->regs, DWC3_OCTL);
  238. reg |= DWC3_OCTL_PERIMODE;
  239. reg &= ~(DWC3_OCTL_TERMSELIDPULSE | DWC3_OCTL_HNPREQ |
  240. DWC3_OCTL_DEVSETHNPEN | DWC3_OCTL_HSTSETHNPEN);
  241. dwc3_writel(dwc->regs, DWC3_OCTL, reg);
  242. /* OEVTEN.OTGBDevSesVldDetEvntEn = 1 */
  243. dwc3_otg_enable_events(dwc, DWC3_OEVTEN_BDEVSESSVLDDETEN);
  244. /* GUSB2PHYCFG.ULPIAutoRes = 0, GUSB2PHYCFG0.SusPHY = 1 */
  245. if (!dwc->dis_u2_susphy_quirk) {
  246. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  247. reg |= DWC3_GUSB2PHYCFG_SUSPHY;
  248. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  249. }
  250. /* GCTL.GblHibernationEn = 0. Already 0. */
  251. }
  252. /* should be called after the gadget controller driver is stopped */
  253. static void dwc3_otg_device_exit(struct dwc3 *dwc)
  254. {
  255. u32 reg;
  256. /*
  257. * Exit from B-device flow as per
  258. * Figure 11-4 OTG Driver Overall Programming Flow
  259. */
  260. /*
  261. * OEVTEN.OTGBDevHNPChngEvntEn = 0
  262. * OEVTEN.OTGBDevVBusChngEvntEn = 0
  263. * OEVTEN.OTGBDevBHostEndEvntEn = 0
  264. */
  265. dwc3_otg_disable_events(dwc, DWC3_OEVTEN_BDEVHNPCHNGEN |
  266. DWC3_OEVTEN_BDEVVBUSCHNGEN |
  267. DWC3_OEVTEN_BDEVBHOSTENDEN);
  268. /* OCTL.DevSetHNPEn = 0, OCTL.HNPReq = 0, OCTL.PeriMode=1 */
  269. reg = dwc3_readl(dwc->regs, DWC3_OCTL);
  270. reg &= ~(DWC3_OCTL_DEVSETHNPEN | DWC3_OCTL_HNPREQ);
  271. reg |= DWC3_OCTL_PERIMODE;
  272. dwc3_writel(dwc->regs, DWC3_OCTL, reg);
  273. }
  274. void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
  275. {
  276. int ret;
  277. u32 reg;
  278. int id;
  279. unsigned long flags;
  280. if (dwc->dr_mode != USB_DR_MODE_OTG)
  281. return;
  282. /* don't do anything if debug user changed role to not OTG */
  283. if (dwc->current_dr_role != DWC3_GCTL_PRTCAP_OTG)
  284. return;
  285. if (!ignore_idstatus) {
  286. reg = dwc3_readl(dwc->regs, DWC3_OSTS);
  287. id = !!(reg & DWC3_OSTS_CONIDSTS);
  288. dwc->desired_otg_role = id ? DWC3_OTG_ROLE_DEVICE :
  289. DWC3_OTG_ROLE_HOST;
  290. }
  291. if (dwc->desired_otg_role == dwc->current_otg_role)
  292. return;
  293. switch (dwc->current_otg_role) {
  294. case DWC3_OTG_ROLE_HOST:
  295. dwc3_host_exit(dwc);
  296. spin_lock_irqsave(&dwc->lock, flags);
  297. dwc3_otg_host_exit(dwc);
  298. spin_unlock_irqrestore(&dwc->lock, flags);
  299. break;
  300. case DWC3_OTG_ROLE_DEVICE:
  301. dwc3_gadget_exit(dwc);
  302. spin_lock_irqsave(&dwc->lock, flags);
  303. dwc3_event_buffers_cleanup(dwc);
  304. dwc3_otg_device_exit(dwc);
  305. spin_unlock_irqrestore(&dwc->lock, flags);
  306. break;
  307. default:
  308. break;
  309. }
  310. spin_lock_irqsave(&dwc->lock, flags);
  311. dwc->current_otg_role = dwc->desired_otg_role;
  312. spin_unlock_irqrestore(&dwc->lock, flags);
  313. switch (dwc->desired_otg_role) {
  314. case DWC3_OTG_ROLE_HOST:
  315. spin_lock_irqsave(&dwc->lock, flags);
  316. dwc3_otgregs_init(dwc);
  317. dwc3_otg_host_init(dwc);
  318. spin_unlock_irqrestore(&dwc->lock, flags);
  319. ret = dwc3_host_init(dwc);
  320. if (ret) {
  321. dev_err(dwc->dev, "failed to initialize host\n");
  322. } else {
  323. if (dwc->usb2_phy)
  324. otg_set_vbus(dwc->usb2_phy->otg, true);
  325. if (dwc->usb2_generic_phy)
  326. phy_set_mode(dwc->usb2_generic_phy,
  327. PHY_MODE_USB_HOST);
  328. }
  329. break;
  330. case DWC3_OTG_ROLE_DEVICE:
  331. spin_lock_irqsave(&dwc->lock, flags);
  332. dwc3_otgregs_init(dwc);
  333. dwc3_otg_device_init(dwc);
  334. dwc3_event_buffers_setup(dwc);
  335. spin_unlock_irqrestore(&dwc->lock, flags);
  336. if (dwc->usb2_phy)
  337. otg_set_vbus(dwc->usb2_phy->otg, false);
  338. if (dwc->usb2_generic_phy)
  339. phy_set_mode(dwc->usb2_generic_phy,
  340. PHY_MODE_USB_DEVICE);
  341. ret = dwc3_gadget_init(dwc);
  342. if (ret)
  343. dev_err(dwc->dev, "failed to initialize peripheral\n");
  344. break;
  345. default:
  346. break;
  347. }
  348. }
  349. static void dwc3_drd_update(struct dwc3 *dwc)
  350. {
  351. int id;
  352. if (dwc->edev) {
  353. id = extcon_get_state(dwc->edev, EXTCON_USB_HOST);
  354. if (id < 0)
  355. id = 0;
  356. dwc3_set_mode(dwc, id ?
  357. DWC3_GCTL_PRTCAP_HOST :
  358. DWC3_GCTL_PRTCAP_DEVICE);
  359. }
  360. }
  361. static int dwc3_drd_notifier(struct notifier_block *nb,
  362. unsigned long event, void *ptr)
  363. {
  364. struct dwc3 *dwc = container_of(nb, struct dwc3, edev_nb);
  365. dwc3_set_mode(dwc, event ?
  366. DWC3_GCTL_PRTCAP_HOST :
  367. DWC3_GCTL_PRTCAP_DEVICE);
  368. return NOTIFY_DONE;
  369. }
  370. static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
  371. {
  372. struct device *dev = dwc->dev;
  373. struct device_node *np_phy;
  374. struct extcon_dev *edev = NULL;
  375. const char *name;
  376. if (device_property_read_bool(dev, "extcon"))
  377. return extcon_get_edev_by_phandle(dev, 0);
  378. /*
  379. * Device tree platforms should get extcon via phandle.
  380. * On ACPI platforms, we get the name from a device property.
  381. * This device property is for kernel internal use only and
  382. * is expected to be set by the glue code.
  383. */
  384. if (device_property_read_string(dev, "linux,extcon-name", &name) == 0) {
  385. edev = extcon_get_extcon_dev(name);
  386. if (!edev)
  387. return ERR_PTR(-EPROBE_DEFER);
  388. return edev;
  389. }
  390. /*
  391. * Try to get an extcon device from the USB PHY controller's "port"
  392. * node. Check if it has the "port" node first, to avoid printing the
  393. * error message from underlying code, as it's a valid case: extcon
  394. * device (and "port" node) may be missing in case of "usb-role-switch"
  395. * or OTG mode.
  396. */
  397. np_phy = of_parse_phandle(dev->of_node, "phys", 0);
  398. if (of_graph_is_present(np_phy)) {
  399. struct device_node *np_conn;
  400. np_conn = of_graph_get_remote_node(np_phy, -1, -1);
  401. if (np_conn)
  402. edev = extcon_find_edev_by_node(np_conn);
  403. of_node_put(np_conn);
  404. }
  405. of_node_put(np_phy);
  406. return edev;
  407. }
  408. #if IS_ENABLED(CONFIG_USB_ROLE_SWITCH)
  409. #define ROLE_SWITCH 1
  410. static int dwc3_usb_role_switch_set(struct usb_role_switch *sw,
  411. enum usb_role role)
  412. {
  413. struct dwc3 *dwc = usb_role_switch_get_drvdata(sw);
  414. u32 mode;
  415. switch (role) {
  416. case USB_ROLE_HOST:
  417. mode = DWC3_GCTL_PRTCAP_HOST;
  418. break;
  419. case USB_ROLE_DEVICE:
  420. mode = DWC3_GCTL_PRTCAP_DEVICE;
  421. break;
  422. default:
  423. if (dwc->role_switch_default_mode == USB_DR_MODE_HOST)
  424. mode = DWC3_GCTL_PRTCAP_HOST;
  425. else
  426. mode = DWC3_GCTL_PRTCAP_DEVICE;
  427. break;
  428. }
  429. dwc3_set_mode(dwc, mode);
  430. return 0;
  431. }
  432. static enum usb_role dwc3_usb_role_switch_get(struct usb_role_switch *sw)
  433. {
  434. struct dwc3 *dwc = usb_role_switch_get_drvdata(sw);
  435. unsigned long flags;
  436. enum usb_role role;
  437. spin_lock_irqsave(&dwc->lock, flags);
  438. switch (dwc->current_dr_role) {
  439. case DWC3_GCTL_PRTCAP_HOST:
  440. role = USB_ROLE_HOST;
  441. break;
  442. case DWC3_GCTL_PRTCAP_DEVICE:
  443. role = USB_ROLE_DEVICE;
  444. break;
  445. case DWC3_GCTL_PRTCAP_OTG:
  446. role = dwc->current_otg_role;
  447. break;
  448. default:
  449. if (dwc->role_switch_default_mode == USB_DR_MODE_HOST)
  450. role = USB_ROLE_HOST;
  451. else
  452. role = USB_ROLE_DEVICE;
  453. break;
  454. }
  455. spin_unlock_irqrestore(&dwc->lock, flags);
  456. return role;
  457. }
  458. static int dwc3_setup_role_switch(struct dwc3 *dwc)
  459. {
  460. struct usb_role_switch_desc dwc3_role_switch = {NULL};
  461. const char *str;
  462. u32 mode;
  463. int ret;
  464. ret = device_property_read_string(dwc->dev, "role-switch-default-mode",
  465. &str);
  466. if (ret >= 0 && !strncmp(str, "host", strlen("host"))) {
  467. dwc->role_switch_default_mode = USB_DR_MODE_HOST;
  468. mode = DWC3_GCTL_PRTCAP_HOST;
  469. } else {
  470. dwc->role_switch_default_mode = USB_DR_MODE_PERIPHERAL;
  471. mode = DWC3_GCTL_PRTCAP_DEVICE;
  472. }
  473. dwc3_role_switch.fwnode = dev_fwnode(dwc->dev);
  474. dwc3_role_switch.set = dwc3_usb_role_switch_set;
  475. dwc3_role_switch.get = dwc3_usb_role_switch_get;
  476. dwc3_role_switch.driver_data = dwc;
  477. dwc->role_sw = usb_role_switch_register(dwc->dev, &dwc3_role_switch);
  478. if (IS_ERR(dwc->role_sw))
  479. return PTR_ERR(dwc->role_sw);
  480. dwc3_set_mode(dwc, mode);
  481. return 0;
  482. }
  483. #else
  484. #define ROLE_SWITCH 0
  485. #define dwc3_setup_role_switch(x) 0
  486. #endif
  487. int dwc3_drd_init(struct dwc3 *dwc)
  488. {
  489. int ret, irq;
  490. dwc->edev = dwc3_get_extcon(dwc);
  491. if (IS_ERR(dwc->edev))
  492. return PTR_ERR(dwc->edev);
  493. if (ROLE_SWITCH &&
  494. device_property_read_bool(dwc->dev, "usb-role-switch")) {
  495. ret = dwc3_setup_role_switch(dwc);
  496. if (ret < 0)
  497. return ret;
  498. } else if (dwc->edev) {
  499. dwc->edev_nb.notifier_call = dwc3_drd_notifier;
  500. ret = extcon_register_notifier(dwc->edev, EXTCON_USB_HOST,
  501. &dwc->edev_nb);
  502. if (ret < 0) {
  503. dev_err(dwc->dev, "couldn't register cable notifier\n");
  504. return ret;
  505. }
  506. dwc3_drd_update(dwc);
  507. } else {
  508. dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_OTG);
  509. dwc->current_dr_role = DWC3_GCTL_PRTCAP_OTG;
  510. /* use OTG block to get ID event */
  511. irq = dwc3_otg_get_irq(dwc);
  512. if (irq < 0)
  513. return irq;
  514. dwc->otg_irq = irq;
  515. /* disable all OTG IRQs */
  516. dwc3_otg_disable_events(dwc, DWC3_OTG_ALL_EVENTS);
  517. /* clear all events */
  518. dwc3_otg_clear_events(dwc);
  519. ret = request_threaded_irq(dwc->otg_irq, dwc3_otg_irq,
  520. dwc3_otg_thread_irq,
  521. IRQF_SHARED, "dwc3-otg", dwc);
  522. if (ret) {
  523. dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
  524. dwc->otg_irq, ret);
  525. ret = -ENODEV;
  526. return ret;
  527. }
  528. dwc3_otg_init(dwc);
  529. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
  530. }
  531. return 0;
  532. }
  533. void dwc3_drd_exit(struct dwc3 *dwc)
  534. {
  535. unsigned long flags;
  536. if (dwc->role_sw)
  537. usb_role_switch_unregister(dwc->role_sw);
  538. if (dwc->edev)
  539. extcon_unregister_notifier(dwc->edev, EXTCON_USB_HOST,
  540. &dwc->edev_nb);
  541. cancel_work_sync(&dwc->drd_work);
  542. /* debug user might have changed role, clean based on current role */
  543. switch (dwc->current_dr_role) {
  544. case DWC3_GCTL_PRTCAP_HOST:
  545. dwc3_host_exit(dwc);
  546. break;
  547. case DWC3_GCTL_PRTCAP_DEVICE:
  548. dwc3_gadget_exit(dwc);
  549. dwc3_event_buffers_cleanup(dwc);
  550. break;
  551. case DWC3_GCTL_PRTCAP_OTG:
  552. dwc3_otg_exit(dwc);
  553. spin_lock_irqsave(&dwc->lock, flags);
  554. dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
  555. spin_unlock_irqrestore(&dwc->lock, flags);
  556. dwc3_otg_update(dwc, 1);
  557. break;
  558. default:
  559. break;
  560. }
  561. if (dwc->otg_irq)
  562. free_irq(dwc->otg_irq, dwc);
  563. }