phy-xgene.c 59 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * AppliedMicro X-Gene Multi-purpose PHY driver
  4. *
  5. * Copyright (c) 2014, Applied Micro Circuits Corporation
  6. * Author: Loc Ho <lho@apm.com>
  7. * Tuan Phan <tphan@apm.com>
  8. * Suman Tripathi <stripathi@apm.com>
  9. *
  10. * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
  11. * The first PLL clock macro is used for internal reference clock. The second
  12. * PLL clock macro is used to generate the clock for the PHY. This driver
  13. * configures the first PLL CMU, the second PLL CMU, and programs the PHY to
  14. * operate according to the mode of operation. The first PLL CMU is only
  15. * required if internal clock is enabled.
  16. *
  17. * Logical Layer Out Of HW module units:
  18. *
  19. * -----------------
  20. * | Internal | |------|
  21. * | Ref PLL CMU |----| | ------------- ---------
  22. * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
  23. * | | | | ---------
  24. * External Clock ------| | -------------
  25. * |------|
  26. *
  27. * The Ref PLL CMU CSR (Configuration System Registers) is accessed
  28. * indirectly from the SDS offset at 0x2000. It is only required for
  29. * internal reference clock.
  30. * The PHY PLL CMU CSR is accessed indirectly from the SDS offset at 0x0000.
  31. * The Serdes CSR is accessed indirectly from the SDS offset at 0x0400.
  32. *
  33. * The Ref PLL CMU can be located within the same PHY IP or outside the PHY IP
  34. * due to shared Ref PLL CMU. For PHY with Ref PLL CMU shared with another IP,
  35. * it is located outside the PHY IP. This is the case for the PHY located
  36. * at 0x1f23a000 (SATA Port 4/5). For such PHY, another resource is required
  37. * to located the SDS/Ref PLL CMU module and its clock for that IP enabled.
  38. *
  39. * Currently, this driver only supports Gen3 SATA mode with external clock.
  40. */
  41. #include <linux/module.h>
  42. #include <linux/platform_device.h>
  43. #include <linux/io.h>
  44. #include <linux/delay.h>
  45. #include <linux/phy/phy.h>
  46. #include <linux/clk.h>
  47. /* Max 2 lanes per a PHY unit */
  48. #define MAX_LANE 2
  49. /* Register offset inside the PHY */
  50. #define SERDES_PLL_INDIRECT_OFFSET 0x0000
  51. #define SERDES_PLL_REF_INDIRECT_OFFSET 0x2000
  52. #define SERDES_INDIRECT_OFFSET 0x0400
  53. #define SERDES_LANE_STRIDE 0x0200
  54. /* Some default Serdes parameters */
  55. #define DEFAULT_SATA_TXBOOST_GAIN { 0x1e, 0x1e, 0x1e }
  56. #define DEFAULT_SATA_TXEYEDIRECTION { 0x0, 0x0, 0x0 }
  57. #define DEFAULT_SATA_TXEYETUNING { 0xa, 0xa, 0xa }
  58. #define DEFAULT_SATA_SPD_SEL { 0x1, 0x3, 0x7 }
  59. #define DEFAULT_SATA_TXAMP { 0x8, 0x8, 0x8 }
  60. #define DEFAULT_SATA_TXCN1 { 0x2, 0x2, 0x2 }
  61. #define DEFAULT_SATA_TXCN2 { 0x0, 0x0, 0x0 }
  62. #define DEFAULT_SATA_TXCP1 { 0xa, 0xa, 0xa }
  63. #define SATA_SPD_SEL_GEN3 0x7
  64. #define SATA_SPD_SEL_GEN2 0x3
  65. #define SATA_SPD_SEL_GEN1 0x1
  66. #define SSC_DISABLE 0
  67. #define SSC_ENABLE 1
  68. #define FBDIV_VAL_50M 0x77
  69. #define REFDIV_VAL_50M 0x1
  70. #define FBDIV_VAL_100M 0x3B
  71. #define REFDIV_VAL_100M 0x0
  72. /* SATA Clock/Reset CSR */
  73. #define SATACLKENREG 0x00000000
  74. #define SATA0_CORE_CLKEN 0x00000002
  75. #define SATA1_CORE_CLKEN 0x00000004
  76. #define SATASRESETREG 0x00000004
  77. #define SATA_MEM_RESET_MASK 0x00000020
  78. #define SATA_MEM_RESET_RD(src) (((src) & 0x00000020) >> 5)
  79. #define SATA_SDS_RESET_MASK 0x00000004
  80. #define SATA_CSR_RESET_MASK 0x00000001
  81. #define SATA_CORE_RESET_MASK 0x00000002
  82. #define SATA_PMCLK_RESET_MASK 0x00000010
  83. #define SATA_PCLK_RESET_MASK 0x00000008
  84. /* SDS CSR used for PHY Indirect access */
  85. #define SATA_ENET_SDS_PCS_CTL0 0x00000000
  86. #define REGSPEC_CFG_I_TX_WORDMODE0_SET(dst, src) \
  87. (((dst) & ~0x00070000) | (((u32) (src) << 16) & 0x00070000))
  88. #define REGSPEC_CFG_I_RX_WORDMODE0_SET(dst, src) \
  89. (((dst) & ~0x00e00000) | (((u32) (src) << 21) & 0x00e00000))
  90. #define SATA_ENET_SDS_CTL0 0x0000000c
  91. #define REGSPEC_CFG_I_CUSTOMER_PIN_MODE0_SET(dst, src) \
  92. (((dst) & ~0x00007fff) | (((u32) (src)) & 0x00007fff))
  93. #define SATA_ENET_SDS_CTL1 0x00000010
  94. #define CFG_I_SPD_SEL_CDR_OVR1_SET(dst, src) \
  95. (((dst) & ~0x0000000f) | (((u32) (src)) & 0x0000000f))
  96. #define SATA_ENET_SDS_RST_CTL 0x00000024
  97. #define SATA_ENET_SDS_IND_CMD_REG 0x0000003c
  98. #define CFG_IND_WR_CMD_MASK 0x00000001
  99. #define CFG_IND_RD_CMD_MASK 0x00000002
  100. #define CFG_IND_CMD_DONE_MASK 0x00000004
  101. #define CFG_IND_ADDR_SET(dst, src) \
  102. (((dst) & ~0x003ffff0) | (((u32) (src) << 4) & 0x003ffff0))
  103. #define SATA_ENET_SDS_IND_RDATA_REG 0x00000040
  104. #define SATA_ENET_SDS_IND_WDATA_REG 0x00000044
  105. #define SATA_ENET_CLK_MACRO_REG 0x0000004c
  106. #define I_RESET_B_SET(dst, src) \
  107. (((dst) & ~0x00000001) | (((u32) (src)) & 0x00000001))
  108. #define I_PLL_FBDIV_SET(dst, src) \
  109. (((dst) & ~0x001ff000) | (((u32) (src) << 12) & 0x001ff000))
  110. #define I_CUSTOMEROV_SET(dst, src) \
  111. (((dst) & ~0x00000f80) | (((u32) (src) << 7) & 0x00000f80))
  112. #define O_PLL_LOCK_RD(src) (((src) & 0x40000000) >> 30)
  113. #define O_PLL_READY_RD(src) (((src) & 0x80000000) >> 31)
  114. /* PLL Clock Macro Unit (CMU) CSR accessing from SDS indirectly */
  115. #define CMU_REG0 0x00000
  116. #define CMU_REG0_PLL_REF_SEL_MASK 0x00002000
  117. #define CMU_REG0_PLL_REF_SEL_SET(dst, src) \
  118. (((dst) & ~0x00002000) | (((u32) (src) << 13) & 0x00002000))
  119. #define CMU_REG0_PDOWN_MASK 0x00004000
  120. #define CMU_REG0_CAL_COUNT_RESOL_SET(dst, src) \
  121. (((dst) & ~0x000000e0) | (((u32) (src) << 5) & 0x000000e0))
  122. #define CMU_REG1 0x00002
  123. #define CMU_REG1_PLL_CP_SET(dst, src) \
  124. (((dst) & ~0x00003c00) | (((u32) (src) << 10) & 0x00003c00))
  125. #define CMU_REG1_PLL_MANUALCAL_SET(dst, src) \
  126. (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
  127. #define CMU_REG1_PLL_CP_SEL_SET(dst, src) \
  128. (((dst) & ~0x000003e0) | (((u32) (src) << 5) & 0x000003e0))
  129. #define CMU_REG1_REFCLK_CMOS_SEL_MASK 0x00000001
  130. #define CMU_REG1_REFCLK_CMOS_SEL_SET(dst, src) \
  131. (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
  132. #define CMU_REG2 0x00004
  133. #define CMU_REG2_PLL_REFDIV_SET(dst, src) \
  134. (((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000))
  135. #define CMU_REG2_PLL_LFRES_SET(dst, src) \
  136. (((dst) & ~0x0000001e) | (((u32) (src) << 1) & 0x0000001e))
  137. #define CMU_REG2_PLL_FBDIV_SET(dst, src) \
  138. (((dst) & ~0x00003fe0) | (((u32) (src) << 5) & 0x00003fe0))
  139. #define CMU_REG3 0x00006
  140. #define CMU_REG3_VCOVARSEL_SET(dst, src) \
  141. (((dst) & ~0x0000000f) | (((u32) (src) << 0) & 0x0000000f))
  142. #define CMU_REG3_VCO_MOMSEL_INIT_SET(dst, src) \
  143. (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
  144. #define CMU_REG3_VCO_MANMOMSEL_SET(dst, src) \
  145. (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
  146. #define CMU_REG4 0x00008
  147. #define CMU_REG5 0x0000a
  148. #define CMU_REG5_PLL_LFSMCAP_SET(dst, src) \
  149. (((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000))
  150. #define CMU_REG5_PLL_LOCK_RESOLUTION_SET(dst, src) \
  151. (((dst) & ~0x0000000e) | (((u32) (src) << 1) & 0x0000000e))
  152. #define CMU_REG5_PLL_LFCAP_SET(dst, src) \
  153. (((dst) & ~0x00003000) | (((u32) (src) << 12) & 0x00003000))
  154. #define CMU_REG5_PLL_RESETB_MASK 0x00000001
  155. #define CMU_REG6 0x0000c
  156. #define CMU_REG6_PLL_VREGTRIM_SET(dst, src) \
  157. (((dst) & ~0x00000600) | (((u32) (src) << 9) & 0x00000600))
  158. #define CMU_REG6_MAN_PVT_CAL_SET(dst, src) \
  159. (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
  160. #define CMU_REG7 0x0000e
  161. #define CMU_REG7_PLL_CALIB_DONE_RD(src) ((0x00004000 & (u32) (src)) >> 14)
  162. #define CMU_REG7_VCO_CAL_FAIL_RD(src) ((0x00000c00 & (u32) (src)) >> 10)
  163. #define CMU_REG8 0x00010
  164. #define CMU_REG9 0x00012
  165. #define CMU_REG9_WORD_LEN_8BIT 0x000
  166. #define CMU_REG9_WORD_LEN_10BIT 0x001
  167. #define CMU_REG9_WORD_LEN_16BIT 0x002
  168. #define CMU_REG9_WORD_LEN_20BIT 0x003
  169. #define CMU_REG9_WORD_LEN_32BIT 0x004
  170. #define CMU_REG9_WORD_LEN_40BIT 0x005
  171. #define CMU_REG9_WORD_LEN_64BIT 0x006
  172. #define CMU_REG9_WORD_LEN_66BIT 0x007
  173. #define CMU_REG9_TX_WORD_MODE_CH1_SET(dst, src) \
  174. (((dst) & ~0x00000380) | (((u32) (src) << 7) & 0x00000380))
  175. #define CMU_REG9_TX_WORD_MODE_CH0_SET(dst, src) \
  176. (((dst) & ~0x00000070) | (((u32) (src) << 4) & 0x00000070))
  177. #define CMU_REG9_PLL_POST_DIVBY2_SET(dst, src) \
  178. (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
  179. #define CMU_REG9_VBG_BYPASSB_SET(dst, src) \
  180. (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
  181. #define CMU_REG9_IGEN_BYPASS_SET(dst, src) \
  182. (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
  183. #define CMU_REG10 0x00014
  184. #define CMU_REG10_VREG_REFSEL_SET(dst, src) \
  185. (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
  186. #define CMU_REG11 0x00016
  187. #define CMU_REG12 0x00018
  188. #define CMU_REG12_STATE_DELAY9_SET(dst, src) \
  189. (((dst) & ~0x000000f0) | (((u32) (src) << 4) & 0x000000f0))
  190. #define CMU_REG13 0x0001a
  191. #define CMU_REG14 0x0001c
  192. #define CMU_REG15 0x0001e
  193. #define CMU_REG16 0x00020
  194. #define CMU_REG16_PVT_DN_MAN_ENA_MASK 0x00000001
  195. #define CMU_REG16_PVT_UP_MAN_ENA_MASK 0x00000002
  196. #define CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(dst, src) \
  197. (((dst) & ~0x0000001c) | (((u32) (src) << 2) & 0x0000001c))
  198. #define CMU_REG16_CALIBRATION_DONE_OVERRIDE_SET(dst, src) \
  199. (((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040))
  200. #define CMU_REG16_BYPASS_PLL_LOCK_SET(dst, src) \
  201. (((dst) & ~0x00000020) | (((u32) (src) << 5) & 0x00000020))
  202. #define CMU_REG17 0x00022
  203. #define CMU_REG17_PVT_CODE_R2A_SET(dst, src) \
  204. (((dst) & ~0x00007f00) | (((u32) (src) << 8) & 0x00007f00))
  205. #define CMU_REG17_RESERVED_7_SET(dst, src) \
  206. (((dst) & ~0x000000e0) | (((u32) (src) << 5) & 0x000000e0))
  207. #define CMU_REG17_PVT_TERM_MAN_ENA_MASK 0x00008000
  208. #define CMU_REG18 0x00024
  209. #define CMU_REG19 0x00026
  210. #define CMU_REG20 0x00028
  211. #define CMU_REG21 0x0002a
  212. #define CMU_REG22 0x0002c
  213. #define CMU_REG23 0x0002e
  214. #define CMU_REG24 0x00030
  215. #define CMU_REG25 0x00032
  216. #define CMU_REG26 0x00034
  217. #define CMU_REG26_FORCE_PLL_LOCK_SET(dst, src) \
  218. (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
  219. #define CMU_REG27 0x00036
  220. #define CMU_REG28 0x00038
  221. #define CMU_REG29 0x0003a
  222. #define CMU_REG30 0x0003c
  223. #define CMU_REG30_LOCK_COUNT_SET(dst, src) \
  224. (((dst) & ~0x00000006) | (((u32) (src) << 1) & 0x00000006))
  225. #define CMU_REG30_PCIE_MODE_SET(dst, src) \
  226. (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
  227. #define CMU_REG31 0x0003e
  228. #define CMU_REG32 0x00040
  229. #define CMU_REG32_FORCE_VCOCAL_START_MASK 0x00004000
  230. #define CMU_REG32_PVT_CAL_WAIT_SEL_SET(dst, src) \
  231. (((dst) & ~0x00000006) | (((u32) (src) << 1) & 0x00000006))
  232. #define CMU_REG32_IREF_ADJ_SET(dst, src) \
  233. (((dst) & ~0x00000180) | (((u32) (src) << 7) & 0x00000180))
  234. #define CMU_REG33 0x00042
  235. #define CMU_REG34 0x00044
  236. #define CMU_REG34_VCO_CAL_VTH_LO_MAX_SET(dst, src) \
  237. (((dst) & ~0x0000000f) | (((u32) (src) << 0) & 0x0000000f))
  238. #define CMU_REG34_VCO_CAL_VTH_HI_MAX_SET(dst, src) \
  239. (((dst) & ~0x00000f00) | (((u32) (src) << 8) & 0x00000f00))
  240. #define CMU_REG34_VCO_CAL_VTH_LO_MIN_SET(dst, src) \
  241. (((dst) & ~0x000000f0) | (((u32) (src) << 4) & 0x000000f0))
  242. #define CMU_REG34_VCO_CAL_VTH_HI_MIN_SET(dst, src) \
  243. (((dst) & ~0x0000f000) | (((u32) (src) << 12) & 0x0000f000))
  244. #define CMU_REG35 0x00046
  245. #define CMU_REG35_PLL_SSC_MOD_SET(dst, src) \
  246. (((dst) & ~0x0000fe00) | (((u32) (src) << 9) & 0x0000fe00))
  247. #define CMU_REG36 0x00048
  248. #define CMU_REG36_PLL_SSC_EN_SET(dst, src) \
  249. (((dst) & ~0x00000010) | (((u32) (src) << 4) & 0x00000010))
  250. #define CMU_REG36_PLL_SSC_VSTEP_SET(dst, src) \
  251. (((dst) & ~0x0000ffc0) | (((u32) (src) << 6) & 0x0000ffc0))
  252. #define CMU_REG36_PLL_SSC_DSMSEL_SET(dst, src) \
  253. (((dst) & ~0x00000020) | (((u32) (src) << 5) & 0x00000020))
  254. #define CMU_REG37 0x0004a
  255. #define CMU_REG38 0x0004c
  256. #define CMU_REG39 0x0004e
  257. /* PHY lane CSR accessing from SDS indirectly */
  258. #define RXTX_REG0 0x000
  259. #define RXTX_REG0_CTLE_EQ_HR_SET(dst, src) \
  260. (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
  261. #define RXTX_REG0_CTLE_EQ_QR_SET(dst, src) \
  262. (((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0))
  263. #define RXTX_REG0_CTLE_EQ_FR_SET(dst, src) \
  264. (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
  265. #define RXTX_REG1 0x002
  266. #define RXTX_REG1_RXACVCM_SET(dst, src) \
  267. (((dst) & ~0x0000f000) | (((u32) (src) << 12) & 0x0000f000))
  268. #define RXTX_REG1_CTLE_EQ_SET(dst, src) \
  269. (((dst) & ~0x00000f80) | (((u32) (src) << 7) & 0x00000f80))
  270. #define RXTX_REG1_RXVREG1_SET(dst, src) \
  271. (((dst) & ~0x00000060) | (((u32) (src) << 5) & 0x00000060))
  272. #define RXTX_REG1_RXIREF_ADJ_SET(dst, src) \
  273. (((dst) & ~0x00000006) | (((u32) (src) << 1) & 0x00000006))
  274. #define RXTX_REG2 0x004
  275. #define RXTX_REG2_VTT_ENA_SET(dst, src) \
  276. (((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100))
  277. #define RXTX_REG2_TX_FIFO_ENA_SET(dst, src) \
  278. (((dst) & ~0x00000020) | (((u32) (src) << 5) & 0x00000020))
  279. #define RXTX_REG2_VTT_SEL_SET(dst, src) \
  280. (((dst) & ~0x000000c0) | (((u32) (src) << 6) & 0x000000c0))
  281. #define RXTX_REG4 0x008
  282. #define RXTX_REG4_TX_LOOPBACK_BUF_EN_MASK 0x00000040
  283. #define RXTX_REG4_TX_DATA_RATE_SET(dst, src) \
  284. (((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000))
  285. #define RXTX_REG4_TX_WORD_MODE_SET(dst, src) \
  286. (((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800))
  287. #define RXTX_REG5 0x00a
  288. #define RXTX_REG5_TX_CN1_SET(dst, src) \
  289. (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
  290. #define RXTX_REG5_TX_CP1_SET(dst, src) \
  291. (((dst) & ~0x000007e0) | (((u32) (src) << 5) & 0x000007e0))
  292. #define RXTX_REG5_TX_CN2_SET(dst, src) \
  293. (((dst) & ~0x0000001f) | (((u32) (src) << 0) & 0x0000001f))
  294. #define RXTX_REG6 0x00c
  295. #define RXTX_REG6_TXAMP_CNTL_SET(dst, src) \
  296. (((dst) & ~0x00000780) | (((u32) (src) << 7) & 0x00000780))
  297. #define RXTX_REG6_TXAMP_ENA_SET(dst, src) \
  298. (((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040))
  299. #define RXTX_REG6_RX_BIST_ERRCNT_RD_SET(dst, src) \
  300. (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
  301. #define RXTX_REG6_TX_IDLE_SET(dst, src) \
  302. (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
  303. #define RXTX_REG6_RX_BIST_RESYNC_SET(dst, src) \
  304. (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
  305. #define RXTX_REG7 0x00e
  306. #define RXTX_REG7_RESETB_RXD_MASK 0x00000100
  307. #define RXTX_REG7_RESETB_RXA_MASK 0x00000080
  308. #define RXTX_REG7_BIST_ENA_RX_SET(dst, src) \
  309. (((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040))
  310. #define RXTX_REG7_RX_WORD_MODE_SET(dst, src) \
  311. (((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800))
  312. #define RXTX_REG8 0x010
  313. #define RXTX_REG8_CDR_LOOP_ENA_SET(dst, src) \
  314. (((dst) & ~0x00004000) | (((u32) (src) << 14) & 0x00004000))
  315. #define RXTX_REG8_CDR_BYPASS_RXLOS_SET(dst, src) \
  316. (((dst) & ~0x00000800) | (((u32) (src) << 11) & 0x00000800))
  317. #define RXTX_REG8_SSC_ENABLE_SET(dst, src) \
  318. (((dst) & ~0x00000200) | (((u32) (src) << 9) & 0x00000200))
  319. #define RXTX_REG8_SD_VREF_SET(dst, src) \
  320. (((dst) & ~0x000000f0) | (((u32) (src) << 4) & 0x000000f0))
  321. #define RXTX_REG8_SD_DISABLE_SET(dst, src) \
  322. (((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100))
  323. #define RXTX_REG7 0x00e
  324. #define RXTX_REG7_RESETB_RXD_SET(dst, src) \
  325. (((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100))
  326. #define RXTX_REG7_RESETB_RXA_SET(dst, src) \
  327. (((dst) & ~0x00000080) | (((u32) (src) << 7) & 0x00000080))
  328. #define RXTX_REG7_LOOP_BACK_ENA_CTLE_MASK 0x00004000
  329. #define RXTX_REG7_LOOP_BACK_ENA_CTLE_SET(dst, src) \
  330. (((dst) & ~0x00004000) | (((u32) (src) << 14) & 0x00004000))
  331. #define RXTX_REG11 0x016
  332. #define RXTX_REG11_PHASE_ADJUST_LIMIT_SET(dst, src) \
  333. (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
  334. #define RXTX_REG12 0x018
  335. #define RXTX_REG12_LATCH_OFF_ENA_SET(dst, src) \
  336. (((dst) & ~0x00002000) | (((u32) (src) << 13) & 0x00002000))
  337. #define RXTX_REG12_SUMOS_ENABLE_SET(dst, src) \
  338. (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
  339. #define RXTX_REG12_RX_DET_TERM_ENABLE_MASK 0x00000002
  340. #define RXTX_REG12_RX_DET_TERM_ENABLE_SET(dst, src) \
  341. (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
  342. #define RXTX_REG13 0x01a
  343. #define RXTX_REG14 0x01c
  344. #define RXTX_REG14_CLTE_LATCAL_MAN_PROG_SET(dst, src) \
  345. (((dst) & ~0x0000003f) | (((u32) (src) << 0) & 0x0000003f))
  346. #define RXTX_REG14_CTLE_LATCAL_MAN_ENA_SET(dst, src) \
  347. (((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040))
  348. #define RXTX_REG26 0x034
  349. #define RXTX_REG26_PERIOD_ERROR_LATCH_SET(dst, src) \
  350. (((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800))
  351. #define RXTX_REG26_BLWC_ENA_SET(dst, src) \
  352. (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
  353. #define RXTX_REG21 0x02a
  354. #define RXTX_REG21_DO_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10)
  355. #define RXTX_REG21_XO_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4)
  356. #define RXTX_REG21_LATCH_CAL_FAIL_ODD_RD(src) ((0x0000000f & (u32)(src)))
  357. #define RXTX_REG22 0x02c
  358. #define RXTX_REG22_SO_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4)
  359. #define RXTX_REG22_EO_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10)
  360. #define RXTX_REG22_LATCH_CAL_FAIL_EVEN_RD(src) ((0x0000000f & (u32)(src)))
  361. #define RXTX_REG23 0x02e
  362. #define RXTX_REG23_DE_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10)
  363. #define RXTX_REG23_XE_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4)
  364. #define RXTX_REG24 0x030
  365. #define RXTX_REG24_EE_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10)
  366. #define RXTX_REG24_SE_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4)
  367. #define RXTX_REG27 0x036
  368. #define RXTX_REG28 0x038
  369. #define RXTX_REG31 0x03e
  370. #define RXTX_REG38 0x04c
  371. #define RXTX_REG38_CUSTOMER_PINMODE_INV_SET(dst, src) \
  372. (((dst) & 0x0000fffe) | (((u32) (src) << 1) & 0x0000fffe))
  373. #define RXTX_REG39 0x04e
  374. #define RXTX_REG40 0x050
  375. #define RXTX_REG41 0x052
  376. #define RXTX_REG42 0x054
  377. #define RXTX_REG43 0x056
  378. #define RXTX_REG44 0x058
  379. #define RXTX_REG45 0x05a
  380. #define RXTX_REG46 0x05c
  381. #define RXTX_REG47 0x05e
  382. #define RXTX_REG48 0x060
  383. #define RXTX_REG49 0x062
  384. #define RXTX_REG50 0x064
  385. #define RXTX_REG51 0x066
  386. #define RXTX_REG52 0x068
  387. #define RXTX_REG53 0x06a
  388. #define RXTX_REG54 0x06c
  389. #define RXTX_REG55 0x06e
  390. #define RXTX_REG61 0x07a
  391. #define RXTX_REG61_ISCAN_INBERT_SET(dst, src) \
  392. (((dst) & ~0x00000010) | (((u32) (src) << 4) & 0x00000010))
  393. #define RXTX_REG61_LOADFREQ_SHIFT_SET(dst, src) \
  394. (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
  395. #define RXTX_REG61_EYE_COUNT_WIDTH_SEL_SET(dst, src) \
  396. (((dst) & ~0x000000c0) | (((u32) (src) << 6) & 0x000000c0))
  397. #define RXTX_REG61_SPD_SEL_CDR_SET(dst, src) \
  398. (((dst) & ~0x00003c00) | (((u32) (src) << 10) & 0x00003c00))
  399. #define RXTX_REG62 0x07c
  400. #define RXTX_REG62_PERIOD_H1_QLATCH_SET(dst, src) \
  401. (((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800))
  402. #define RXTX_REG81 0x0a2
  403. #define RXTX_REG89_MU_TH7_SET(dst, src) \
  404. (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
  405. #define RXTX_REG89_MU_TH8_SET(dst, src) \
  406. (((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0))
  407. #define RXTX_REG89_MU_TH9_SET(dst, src) \
  408. (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
  409. #define RXTX_REG96 0x0c0
  410. #define RXTX_REG96_MU_FREQ1_SET(dst, src) \
  411. (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
  412. #define RXTX_REG96_MU_FREQ2_SET(dst, src) \
  413. (((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0))
  414. #define RXTX_REG96_MU_FREQ3_SET(dst, src) \
  415. (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
  416. #define RXTX_REG99 0x0c6
  417. #define RXTX_REG99_MU_PHASE1_SET(dst, src) \
  418. (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
  419. #define RXTX_REG99_MU_PHASE2_SET(dst, src) \
  420. (((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0))
  421. #define RXTX_REG99_MU_PHASE3_SET(dst, src) \
  422. (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
  423. #define RXTX_REG102 0x0cc
  424. #define RXTX_REG102_FREQLOOP_LIMIT_SET(dst, src) \
  425. (((dst) & ~0x00000060) | (((u32) (src) << 5) & 0x00000060))
  426. #define RXTX_REG114 0x0e4
  427. #define RXTX_REG121 0x0f2
  428. #define RXTX_REG121_SUMOS_CAL_CODE_RD(src) ((0x0000003e & (u32)(src)) >> 0x1)
  429. #define RXTX_REG125 0x0fa
  430. #define RXTX_REG125_PQ_REG_SET(dst, src) \
  431. (((dst) & ~0x0000fe00) | (((u32) (src) << 9) & 0x0000fe00))
  432. #define RXTX_REG125_SIGN_PQ_SET(dst, src) \
  433. (((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100))
  434. #define RXTX_REG125_SIGN_PQ_2C_SET(dst, src) \
  435. (((dst) & ~0x00000080) | (((u32) (src) << 7) & 0x00000080))
  436. #define RXTX_REG125_PHZ_MANUALCODE_SET(dst, src) \
  437. (((dst) & ~0x0000007c) | (((u32) (src) << 2) & 0x0000007c))
  438. #define RXTX_REG125_PHZ_MANUAL_SET(dst, src) \
  439. (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
  440. #define RXTX_REG127 0x0fe
  441. #define RXTX_REG127_FORCE_SUM_CAL_START_MASK 0x00000002
  442. #define RXTX_REG127_FORCE_LAT_CAL_START_MASK 0x00000004
  443. #define RXTX_REG127_FORCE_SUM_CAL_START_SET(dst, src) \
  444. (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
  445. #define RXTX_REG127_FORCE_LAT_CAL_START_SET(dst, src) \
  446. (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
  447. #define RXTX_REG127_LATCH_MAN_CAL_ENA_SET(dst, src) \
  448. (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
  449. #define RXTX_REG127_DO_LATCH_MANCAL_SET(dst, src) \
  450. (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
  451. #define RXTX_REG127_XO_LATCH_MANCAL_SET(dst, src) \
  452. (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
  453. #define RXTX_REG128 0x100
  454. #define RXTX_REG128_LATCH_CAL_WAIT_SEL_SET(dst, src) \
  455. (((dst) & ~0x0000000c) | (((u32) (src) << 2) & 0x0000000c))
  456. #define RXTX_REG128_EO_LATCH_MANCAL_SET(dst, src) \
  457. (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
  458. #define RXTX_REG128_SO_LATCH_MANCAL_SET(dst, src) \
  459. (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
  460. #define RXTX_REG129 0x102
  461. #define RXTX_REG129_DE_LATCH_MANCAL_SET(dst, src) \
  462. (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
  463. #define RXTX_REG129_XE_LATCH_MANCAL_SET(dst, src) \
  464. (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
  465. #define RXTX_REG130 0x104
  466. #define RXTX_REG130_EE_LATCH_MANCAL_SET(dst, src) \
  467. (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
  468. #define RXTX_REG130_SE_LATCH_MANCAL_SET(dst, src) \
  469. (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
  470. #define RXTX_REG145 0x122
  471. #define RXTX_REG145_TX_IDLE_SATA_SET(dst, src) \
  472. (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
  473. #define RXTX_REG145_RXES_ENA_SET(dst, src) \
  474. (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
  475. #define RXTX_REG145_RXDFE_CONFIG_SET(dst, src) \
  476. (((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000))
  477. #define RXTX_REG145_RXVWES_LATENA_SET(dst, src) \
  478. (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
  479. #define RXTX_REG147 0x126
  480. #define RXTX_REG148 0x128
  481. /* Clock macro type */
  482. enum cmu_type_t {
  483. REF_CMU = 0, /* Clock macro is the internal reference clock */
  484. PHY_CMU = 1, /* Clock macro is the PLL for the Serdes */
  485. };
  486. enum mux_type_t {
  487. MUX_SELECT_ATA = 0, /* Switch the MUX to ATA */
  488. MUX_SELECT_SGMMII = 0, /* Switch the MUX to SGMII */
  489. };
  490. enum clk_type_t {
  491. CLK_EXT_DIFF = 0, /* External differential */
  492. CLK_INT_DIFF = 1, /* Internal differential */
  493. CLK_INT_SING = 2, /* Internal single ended */
  494. };
  495. enum xgene_phy_mode {
  496. MODE_SATA = 0, /* List them for simple reference */
  497. MODE_SGMII = 1,
  498. MODE_PCIE = 2,
  499. MODE_USB = 3,
  500. MODE_XFI = 4,
  501. MODE_MAX
  502. };
  503. struct xgene_sata_override_param {
  504. u32 speed[MAX_LANE]; /* Index for override parameter per lane */
  505. u32 txspeed[3]; /* Tx speed */
  506. u32 txboostgain[MAX_LANE*3]; /* Tx freq boost and gain control */
  507. u32 txeyetuning[MAX_LANE*3]; /* Tx eye tuning */
  508. u32 txeyedirection[MAX_LANE*3]; /* Tx eye tuning direction */
  509. u32 txamplitude[MAX_LANE*3]; /* Tx amplitude control */
  510. u32 txprecursor_cn1[MAX_LANE*3]; /* Tx emphasis taps 1st pre-cursor */
  511. u32 txprecursor_cn2[MAX_LANE*3]; /* Tx emphasis taps 2nd pre-cursor */
  512. u32 txpostcursor_cp1[MAX_LANE*3]; /* Tx emphasis taps post-cursor */
  513. };
  514. struct xgene_phy_ctx {
  515. struct device *dev;
  516. struct phy *phy;
  517. enum xgene_phy_mode mode; /* Mode of operation */
  518. enum clk_type_t clk_type; /* Input clock selection */
  519. void __iomem *sds_base; /* PHY CSR base addr */
  520. struct clk *clk; /* Optional clock */
  521. /* Override Serdes parameters */
  522. struct xgene_sata_override_param sata_param;
  523. };
  524. /*
  525. * For chip earlier than A3 version, enable this flag.
  526. * To enable, pass boot argument phy_xgene.preA3Chip=1
  527. */
  528. static int preA3Chip;
  529. MODULE_PARM_DESC(preA3Chip, "Enable pre-A3 chip support (1=enable 0=disable)");
  530. module_param_named(preA3Chip, preA3Chip, int, 0444);
  531. static void sds_wr(void __iomem *csr_base, u32 indirect_cmd_reg,
  532. u32 indirect_data_reg, u32 addr, u32 data)
  533. {
  534. unsigned long deadline = jiffies + HZ;
  535. u32 val;
  536. u32 cmd;
  537. cmd = CFG_IND_WR_CMD_MASK | CFG_IND_CMD_DONE_MASK;
  538. cmd = CFG_IND_ADDR_SET(cmd, addr);
  539. writel(data, csr_base + indirect_data_reg);
  540. readl(csr_base + indirect_data_reg); /* Force a barrier */
  541. writel(cmd, csr_base + indirect_cmd_reg);
  542. readl(csr_base + indirect_cmd_reg); /* Force a barrier */
  543. do {
  544. val = readl(csr_base + indirect_cmd_reg);
  545. } while (!(val & CFG_IND_CMD_DONE_MASK) &&
  546. time_before(jiffies, deadline));
  547. if (!(val & CFG_IND_CMD_DONE_MASK))
  548. pr_err("SDS WR timeout at 0x%p offset 0x%08X value 0x%08X\n",
  549. csr_base + indirect_cmd_reg, addr, data);
  550. }
  551. static void sds_rd(void __iomem *csr_base, u32 indirect_cmd_reg,
  552. u32 indirect_data_reg, u32 addr, u32 *data)
  553. {
  554. unsigned long deadline = jiffies + HZ;
  555. u32 val;
  556. u32 cmd;
  557. cmd = CFG_IND_RD_CMD_MASK | CFG_IND_CMD_DONE_MASK;
  558. cmd = CFG_IND_ADDR_SET(cmd, addr);
  559. writel(cmd, csr_base + indirect_cmd_reg);
  560. readl(csr_base + indirect_cmd_reg); /* Force a barrier */
  561. do {
  562. val = readl(csr_base + indirect_cmd_reg);
  563. } while (!(val & CFG_IND_CMD_DONE_MASK) &&
  564. time_before(jiffies, deadline));
  565. *data = readl(csr_base + indirect_data_reg);
  566. if (!(val & CFG_IND_CMD_DONE_MASK))
  567. pr_err("SDS WR timeout at 0x%p offset 0x%08X value 0x%08X\n",
  568. csr_base + indirect_cmd_reg, addr, *data);
  569. }
  570. static void cmu_wr(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type,
  571. u32 reg, u32 data)
  572. {
  573. void __iomem *sds_base = ctx->sds_base;
  574. u32 val;
  575. if (cmu_type == REF_CMU)
  576. reg += SERDES_PLL_REF_INDIRECT_OFFSET;
  577. else
  578. reg += SERDES_PLL_INDIRECT_OFFSET;
  579. sds_wr(sds_base, SATA_ENET_SDS_IND_CMD_REG,
  580. SATA_ENET_SDS_IND_WDATA_REG, reg, data);
  581. sds_rd(sds_base, SATA_ENET_SDS_IND_CMD_REG,
  582. SATA_ENET_SDS_IND_RDATA_REG, reg, &val);
  583. pr_debug("CMU WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, val);
  584. }
  585. static void cmu_rd(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type,
  586. u32 reg, u32 *data)
  587. {
  588. void __iomem *sds_base = ctx->sds_base;
  589. if (cmu_type == REF_CMU)
  590. reg += SERDES_PLL_REF_INDIRECT_OFFSET;
  591. else
  592. reg += SERDES_PLL_INDIRECT_OFFSET;
  593. sds_rd(sds_base, SATA_ENET_SDS_IND_CMD_REG,
  594. SATA_ENET_SDS_IND_RDATA_REG, reg, data);
  595. pr_debug("CMU RD addr 0x%X value 0x%08X\n", reg, *data);
  596. }
  597. static void cmu_toggle1to0(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type,
  598. u32 reg, u32 bits)
  599. {
  600. u32 val;
  601. cmu_rd(ctx, cmu_type, reg, &val);
  602. val |= bits;
  603. cmu_wr(ctx, cmu_type, reg, val);
  604. cmu_rd(ctx, cmu_type, reg, &val);
  605. val &= ~bits;
  606. cmu_wr(ctx, cmu_type, reg, val);
  607. }
  608. static void cmu_clrbits(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type,
  609. u32 reg, u32 bits)
  610. {
  611. u32 val;
  612. cmu_rd(ctx, cmu_type, reg, &val);
  613. val &= ~bits;
  614. cmu_wr(ctx, cmu_type, reg, val);
  615. }
  616. static void cmu_setbits(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type,
  617. u32 reg, u32 bits)
  618. {
  619. u32 val;
  620. cmu_rd(ctx, cmu_type, reg, &val);
  621. val |= bits;
  622. cmu_wr(ctx, cmu_type, reg, val);
  623. }
  624. static void serdes_wr(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 data)
  625. {
  626. void __iomem *sds_base = ctx->sds_base;
  627. u32 val;
  628. reg += SERDES_INDIRECT_OFFSET;
  629. reg += lane * SERDES_LANE_STRIDE;
  630. sds_wr(sds_base, SATA_ENET_SDS_IND_CMD_REG,
  631. SATA_ENET_SDS_IND_WDATA_REG, reg, data);
  632. sds_rd(sds_base, SATA_ENET_SDS_IND_CMD_REG,
  633. SATA_ENET_SDS_IND_RDATA_REG, reg, &val);
  634. pr_debug("SERDES WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data,
  635. val);
  636. }
  637. static void serdes_rd(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 *data)
  638. {
  639. void __iomem *sds_base = ctx->sds_base;
  640. reg += SERDES_INDIRECT_OFFSET;
  641. reg += lane * SERDES_LANE_STRIDE;
  642. sds_rd(sds_base, SATA_ENET_SDS_IND_CMD_REG,
  643. SATA_ENET_SDS_IND_RDATA_REG, reg, data);
  644. pr_debug("SERDES RD addr 0x%X value 0x%08X\n", reg, *data);
  645. }
  646. static void serdes_clrbits(struct xgene_phy_ctx *ctx, int lane, u32 reg,
  647. u32 bits)
  648. {
  649. u32 val;
  650. serdes_rd(ctx, lane, reg, &val);
  651. val &= ~bits;
  652. serdes_wr(ctx, lane, reg, val);
  653. }
  654. static void serdes_setbits(struct xgene_phy_ctx *ctx, int lane, u32 reg,
  655. u32 bits)
  656. {
  657. u32 val;
  658. serdes_rd(ctx, lane, reg, &val);
  659. val |= bits;
  660. serdes_wr(ctx, lane, reg, val);
  661. }
  662. static void xgene_phy_cfg_cmu_clk_type(struct xgene_phy_ctx *ctx,
  663. enum cmu_type_t cmu_type,
  664. enum clk_type_t clk_type)
  665. {
  666. u32 val;
  667. /* Set the reset sequence delay for TX ready assertion */
  668. cmu_rd(ctx, cmu_type, CMU_REG12, &val);
  669. val = CMU_REG12_STATE_DELAY9_SET(val, 0x1);
  670. cmu_wr(ctx, cmu_type, CMU_REG12, val);
  671. /* Set the programmable stage delays between various enable stages */
  672. cmu_wr(ctx, cmu_type, CMU_REG13, 0x0222);
  673. cmu_wr(ctx, cmu_type, CMU_REG14, 0x2225);
  674. /* Configure clock type */
  675. if (clk_type == CLK_EXT_DIFF) {
  676. /* Select external clock mux */
  677. cmu_rd(ctx, cmu_type, CMU_REG0, &val);
  678. val = CMU_REG0_PLL_REF_SEL_SET(val, 0x0);
  679. cmu_wr(ctx, cmu_type, CMU_REG0, val);
  680. /* Select CMOS as reference clock */
  681. cmu_rd(ctx, cmu_type, CMU_REG1, &val);
  682. val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x0);
  683. cmu_wr(ctx, cmu_type, CMU_REG1, val);
  684. dev_dbg(ctx->dev, "Set external reference clock\n");
  685. } else if (clk_type == CLK_INT_DIFF) {
  686. /* Select internal clock mux */
  687. cmu_rd(ctx, cmu_type, CMU_REG0, &val);
  688. val = CMU_REG0_PLL_REF_SEL_SET(val, 0x1);
  689. cmu_wr(ctx, cmu_type, CMU_REG0, val);
  690. /* Select CMOS as reference clock */
  691. cmu_rd(ctx, cmu_type, CMU_REG1, &val);
  692. val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x1);
  693. cmu_wr(ctx, cmu_type, CMU_REG1, val);
  694. dev_dbg(ctx->dev, "Set internal reference clock\n");
  695. } else if (clk_type == CLK_INT_SING) {
  696. /*
  697. * NOTE: This clock type is NOT support for controller
  698. * whose internal clock shared in the PCIe controller
  699. *
  700. * Select internal clock mux
  701. */
  702. cmu_rd(ctx, cmu_type, CMU_REG1, &val);
  703. val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x1);
  704. cmu_wr(ctx, cmu_type, CMU_REG1, val);
  705. /* Select CML as reference clock */
  706. cmu_rd(ctx, cmu_type, CMU_REG1, &val);
  707. val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x0);
  708. cmu_wr(ctx, cmu_type, CMU_REG1, val);
  709. dev_dbg(ctx->dev,
  710. "Set internal single ended reference clock\n");
  711. }
  712. }
  713. static void xgene_phy_sata_cfg_cmu_core(struct xgene_phy_ctx *ctx,
  714. enum cmu_type_t cmu_type,
  715. enum clk_type_t clk_type)
  716. {
  717. u32 val;
  718. int ref_100MHz;
  719. if (cmu_type == REF_CMU) {
  720. /* Set VCO calibration voltage threshold */
  721. cmu_rd(ctx, cmu_type, CMU_REG34, &val);
  722. val = CMU_REG34_VCO_CAL_VTH_LO_MAX_SET(val, 0x7);
  723. val = CMU_REG34_VCO_CAL_VTH_HI_MAX_SET(val, 0xc);
  724. val = CMU_REG34_VCO_CAL_VTH_LO_MIN_SET(val, 0x3);
  725. val = CMU_REG34_VCO_CAL_VTH_HI_MIN_SET(val, 0x8);
  726. cmu_wr(ctx, cmu_type, CMU_REG34, val);
  727. }
  728. /* Set the VCO calibration counter */
  729. cmu_rd(ctx, cmu_type, CMU_REG0, &val);
  730. if (cmu_type == REF_CMU || preA3Chip)
  731. val = CMU_REG0_CAL_COUNT_RESOL_SET(val, 0x4);
  732. else
  733. val = CMU_REG0_CAL_COUNT_RESOL_SET(val, 0x7);
  734. cmu_wr(ctx, cmu_type, CMU_REG0, val);
  735. /* Configure PLL for calibration */
  736. cmu_rd(ctx, cmu_type, CMU_REG1, &val);
  737. val = CMU_REG1_PLL_CP_SET(val, 0x1);
  738. if (cmu_type == REF_CMU || preA3Chip)
  739. val = CMU_REG1_PLL_CP_SEL_SET(val, 0x5);
  740. else
  741. val = CMU_REG1_PLL_CP_SEL_SET(val, 0x3);
  742. if (cmu_type == REF_CMU)
  743. val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x0);
  744. else
  745. val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x1);
  746. cmu_wr(ctx, cmu_type, CMU_REG1, val);
  747. if (cmu_type != REF_CMU)
  748. cmu_clrbits(ctx, cmu_type, CMU_REG5, CMU_REG5_PLL_RESETB_MASK);
  749. /* Configure the PLL for either 100MHz or 50MHz */
  750. cmu_rd(ctx, cmu_type, CMU_REG2, &val);
  751. if (cmu_type == REF_CMU) {
  752. val = CMU_REG2_PLL_LFRES_SET(val, 0xa);
  753. ref_100MHz = 1;
  754. } else {
  755. val = CMU_REG2_PLL_LFRES_SET(val, 0x3);
  756. if (clk_type == CLK_EXT_DIFF)
  757. ref_100MHz = 0;
  758. else
  759. ref_100MHz = 1;
  760. }
  761. if (ref_100MHz) {
  762. val = CMU_REG2_PLL_FBDIV_SET(val, FBDIV_VAL_100M);
  763. val = CMU_REG2_PLL_REFDIV_SET(val, REFDIV_VAL_100M);
  764. } else {
  765. val = CMU_REG2_PLL_FBDIV_SET(val, FBDIV_VAL_50M);
  766. val = CMU_REG2_PLL_REFDIV_SET(val, REFDIV_VAL_50M);
  767. }
  768. cmu_wr(ctx, cmu_type, CMU_REG2, val);
  769. /* Configure the VCO */
  770. cmu_rd(ctx, cmu_type, CMU_REG3, &val);
  771. if (cmu_type == REF_CMU) {
  772. val = CMU_REG3_VCOVARSEL_SET(val, 0x3);
  773. val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x10);
  774. } else {
  775. val = CMU_REG3_VCOVARSEL_SET(val, 0xF);
  776. if (preA3Chip)
  777. val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x15);
  778. else
  779. val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x1a);
  780. val = CMU_REG3_VCO_MANMOMSEL_SET(val, 0x15);
  781. }
  782. cmu_wr(ctx, cmu_type, CMU_REG3, val);
  783. /* Disable force PLL lock */
  784. cmu_rd(ctx, cmu_type, CMU_REG26, &val);
  785. val = CMU_REG26_FORCE_PLL_LOCK_SET(val, 0x0);
  786. cmu_wr(ctx, cmu_type, CMU_REG26, val);
  787. /* Setup PLL loop filter */
  788. cmu_rd(ctx, cmu_type, CMU_REG5, &val);
  789. val = CMU_REG5_PLL_LFSMCAP_SET(val, 0x3);
  790. val = CMU_REG5_PLL_LFCAP_SET(val, 0x3);
  791. if (cmu_type == REF_CMU || !preA3Chip)
  792. val = CMU_REG5_PLL_LOCK_RESOLUTION_SET(val, 0x7);
  793. else
  794. val = CMU_REG5_PLL_LOCK_RESOLUTION_SET(val, 0x4);
  795. cmu_wr(ctx, cmu_type, CMU_REG5, val);
  796. /* Enable or disable manual calibration */
  797. cmu_rd(ctx, cmu_type, CMU_REG6, &val);
  798. val = CMU_REG6_PLL_VREGTRIM_SET(val, preA3Chip ? 0x0 : 0x2);
  799. val = CMU_REG6_MAN_PVT_CAL_SET(val, preA3Chip ? 0x1 : 0x0);
  800. cmu_wr(ctx, cmu_type, CMU_REG6, val);
  801. /* Configure lane for 20-bits */
  802. if (cmu_type == PHY_CMU) {
  803. cmu_rd(ctx, cmu_type, CMU_REG9, &val);
  804. val = CMU_REG9_TX_WORD_MODE_CH1_SET(val,
  805. CMU_REG9_WORD_LEN_20BIT);
  806. val = CMU_REG9_TX_WORD_MODE_CH0_SET(val,
  807. CMU_REG9_WORD_LEN_20BIT);
  808. val = CMU_REG9_PLL_POST_DIVBY2_SET(val, 0x1);
  809. if (!preA3Chip) {
  810. val = CMU_REG9_VBG_BYPASSB_SET(val, 0x0);
  811. val = CMU_REG9_IGEN_BYPASS_SET(val , 0x0);
  812. }
  813. cmu_wr(ctx, cmu_type, CMU_REG9, val);
  814. if (!preA3Chip) {
  815. cmu_rd(ctx, cmu_type, CMU_REG10, &val);
  816. val = CMU_REG10_VREG_REFSEL_SET(val, 0x1);
  817. cmu_wr(ctx, cmu_type, CMU_REG10, val);
  818. }
  819. }
  820. cmu_rd(ctx, cmu_type, CMU_REG16, &val);
  821. val = CMU_REG16_CALIBRATION_DONE_OVERRIDE_SET(val, 0x1);
  822. val = CMU_REG16_BYPASS_PLL_LOCK_SET(val, 0x1);
  823. if (cmu_type == REF_CMU || preA3Chip)
  824. val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x4);
  825. else
  826. val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x7);
  827. cmu_wr(ctx, cmu_type, CMU_REG16, val);
  828. /* Configure for SATA */
  829. cmu_rd(ctx, cmu_type, CMU_REG30, &val);
  830. val = CMU_REG30_PCIE_MODE_SET(val, 0x0);
  831. val = CMU_REG30_LOCK_COUNT_SET(val, 0x3);
  832. cmu_wr(ctx, cmu_type, CMU_REG30, val);
  833. /* Disable state machine bypass */
  834. cmu_wr(ctx, cmu_type, CMU_REG31, 0xF);
  835. cmu_rd(ctx, cmu_type, CMU_REG32, &val);
  836. val = CMU_REG32_PVT_CAL_WAIT_SEL_SET(val, 0x3);
  837. if (cmu_type == REF_CMU || preA3Chip)
  838. val = CMU_REG32_IREF_ADJ_SET(val, 0x3);
  839. else
  840. val = CMU_REG32_IREF_ADJ_SET(val, 0x1);
  841. cmu_wr(ctx, cmu_type, CMU_REG32, val);
  842. /* Set VCO calibration threshold */
  843. if (cmu_type != REF_CMU && preA3Chip)
  844. cmu_wr(ctx, cmu_type, CMU_REG34, 0x8d27);
  845. else
  846. cmu_wr(ctx, cmu_type, CMU_REG34, 0x873c);
  847. /* Set CTLE Override and override waiting from state machine */
  848. cmu_wr(ctx, cmu_type, CMU_REG37, 0xF00F);
  849. }
  850. static void xgene_phy_ssc_enable(struct xgene_phy_ctx *ctx,
  851. enum cmu_type_t cmu_type)
  852. {
  853. u32 val;
  854. /* Set SSC modulation value */
  855. cmu_rd(ctx, cmu_type, CMU_REG35, &val);
  856. val = CMU_REG35_PLL_SSC_MOD_SET(val, 98);
  857. cmu_wr(ctx, cmu_type, CMU_REG35, val);
  858. /* Enable SSC, set vertical step and DSM value */
  859. cmu_rd(ctx, cmu_type, CMU_REG36, &val);
  860. val = CMU_REG36_PLL_SSC_VSTEP_SET(val, 30);
  861. val = CMU_REG36_PLL_SSC_EN_SET(val, 1);
  862. val = CMU_REG36_PLL_SSC_DSMSEL_SET(val, 1);
  863. cmu_wr(ctx, cmu_type, CMU_REG36, val);
  864. /* Reset the PLL */
  865. cmu_clrbits(ctx, cmu_type, CMU_REG5, CMU_REG5_PLL_RESETB_MASK);
  866. cmu_setbits(ctx, cmu_type, CMU_REG5, CMU_REG5_PLL_RESETB_MASK);
  867. /* Force VCO calibration to restart */
  868. cmu_toggle1to0(ctx, cmu_type, CMU_REG32,
  869. CMU_REG32_FORCE_VCOCAL_START_MASK);
  870. }
  871. static void xgene_phy_sata_cfg_lanes(struct xgene_phy_ctx *ctx)
  872. {
  873. u32 val;
  874. u32 reg;
  875. int i;
  876. int lane;
  877. for (lane = 0; lane < MAX_LANE; lane++) {
  878. serdes_wr(ctx, lane, RXTX_REG147, 0x6);
  879. /* Set boost control for quarter, half, and full rate */
  880. serdes_rd(ctx, lane, RXTX_REG0, &val);
  881. val = RXTX_REG0_CTLE_EQ_HR_SET(val, 0x10);
  882. val = RXTX_REG0_CTLE_EQ_QR_SET(val, 0x10);
  883. val = RXTX_REG0_CTLE_EQ_FR_SET(val, 0x10);
  884. serdes_wr(ctx, lane, RXTX_REG0, val);
  885. /* Set boost control value */
  886. serdes_rd(ctx, lane, RXTX_REG1, &val);
  887. val = RXTX_REG1_RXACVCM_SET(val, 0x7);
  888. val = RXTX_REG1_CTLE_EQ_SET(val,
  889. ctx->sata_param.txboostgain[lane * 3 +
  890. ctx->sata_param.speed[lane]]);
  891. serdes_wr(ctx, lane, RXTX_REG1, val);
  892. /* Latch VTT value based on the termination to ground and
  893. enable TX FIFO */
  894. serdes_rd(ctx, lane, RXTX_REG2, &val);
  895. val = RXTX_REG2_VTT_ENA_SET(val, 0x1);
  896. val = RXTX_REG2_VTT_SEL_SET(val, 0x1);
  897. val = RXTX_REG2_TX_FIFO_ENA_SET(val, 0x1);
  898. serdes_wr(ctx, lane, RXTX_REG2, val);
  899. /* Configure Tx for 20-bits */
  900. serdes_rd(ctx, lane, RXTX_REG4, &val);
  901. val = RXTX_REG4_TX_WORD_MODE_SET(val, CMU_REG9_WORD_LEN_20BIT);
  902. serdes_wr(ctx, lane, RXTX_REG4, val);
  903. if (!preA3Chip) {
  904. serdes_rd(ctx, lane, RXTX_REG1, &val);
  905. val = RXTX_REG1_RXVREG1_SET(val, 0x2);
  906. val = RXTX_REG1_RXIREF_ADJ_SET(val, 0x2);
  907. serdes_wr(ctx, lane, RXTX_REG1, val);
  908. }
  909. /* Set pre-emphasis first 1 and 2, and post-emphasis values */
  910. serdes_rd(ctx, lane, RXTX_REG5, &val);
  911. val = RXTX_REG5_TX_CN1_SET(val,
  912. ctx->sata_param.txprecursor_cn1[lane * 3 +
  913. ctx->sata_param.speed[lane]]);
  914. val = RXTX_REG5_TX_CP1_SET(val,
  915. ctx->sata_param.txpostcursor_cp1[lane * 3 +
  916. ctx->sata_param.speed[lane]]);
  917. val = RXTX_REG5_TX_CN2_SET(val,
  918. ctx->sata_param.txprecursor_cn2[lane * 3 +
  919. ctx->sata_param.speed[lane]]);
  920. serdes_wr(ctx, lane, RXTX_REG5, val);
  921. /* Set TX amplitude value */
  922. serdes_rd(ctx, lane, RXTX_REG6, &val);
  923. val = RXTX_REG6_TXAMP_CNTL_SET(val,
  924. ctx->sata_param.txamplitude[lane * 3 +
  925. ctx->sata_param.speed[lane]]);
  926. val = RXTX_REG6_TXAMP_ENA_SET(val, 0x1);
  927. val = RXTX_REG6_TX_IDLE_SET(val, 0x0);
  928. val = RXTX_REG6_RX_BIST_RESYNC_SET(val, 0x0);
  929. val = RXTX_REG6_RX_BIST_ERRCNT_RD_SET(val, 0x0);
  930. serdes_wr(ctx, lane, RXTX_REG6, val);
  931. /* Configure Rx for 20-bits */
  932. serdes_rd(ctx, lane, RXTX_REG7, &val);
  933. val = RXTX_REG7_BIST_ENA_RX_SET(val, 0x0);
  934. val = RXTX_REG7_RX_WORD_MODE_SET(val, CMU_REG9_WORD_LEN_20BIT);
  935. serdes_wr(ctx, lane, RXTX_REG7, val);
  936. /* Set CDR and LOS values and enable Rx SSC */
  937. serdes_rd(ctx, lane, RXTX_REG8, &val);
  938. val = RXTX_REG8_CDR_LOOP_ENA_SET(val, 0x1);
  939. val = RXTX_REG8_CDR_BYPASS_RXLOS_SET(val, 0x0);
  940. val = RXTX_REG8_SSC_ENABLE_SET(val, 0x1);
  941. val = RXTX_REG8_SD_DISABLE_SET(val, 0x0);
  942. val = RXTX_REG8_SD_VREF_SET(val, 0x4);
  943. serdes_wr(ctx, lane, RXTX_REG8, val);
  944. /* Set phase adjust upper/lower limits */
  945. serdes_rd(ctx, lane, RXTX_REG11, &val);
  946. val = RXTX_REG11_PHASE_ADJUST_LIMIT_SET(val, 0x0);
  947. serdes_wr(ctx, lane, RXTX_REG11, val);
  948. /* Enable Latch Off; disable SUMOS and Tx termination */
  949. serdes_rd(ctx, lane, RXTX_REG12, &val);
  950. val = RXTX_REG12_LATCH_OFF_ENA_SET(val, 0x1);
  951. val = RXTX_REG12_SUMOS_ENABLE_SET(val, 0x0);
  952. val = RXTX_REG12_RX_DET_TERM_ENABLE_SET(val, 0x0);
  953. serdes_wr(ctx, lane, RXTX_REG12, val);
  954. /* Set period error latch to 512T and enable BWL */
  955. serdes_rd(ctx, lane, RXTX_REG26, &val);
  956. val = RXTX_REG26_PERIOD_ERROR_LATCH_SET(val, 0x0);
  957. val = RXTX_REG26_BLWC_ENA_SET(val, 0x1);
  958. serdes_wr(ctx, lane, RXTX_REG26, val);
  959. serdes_wr(ctx, lane, RXTX_REG28, 0x0);
  960. /* Set DFE loop preset value */
  961. serdes_wr(ctx, lane, RXTX_REG31, 0x0);
  962. /* Set Eye Monitor counter width to 12-bit */
  963. serdes_rd(ctx, lane, RXTX_REG61, &val);
  964. val = RXTX_REG61_ISCAN_INBERT_SET(val, 0x1);
  965. val = RXTX_REG61_LOADFREQ_SHIFT_SET(val, 0x0);
  966. val = RXTX_REG61_EYE_COUNT_WIDTH_SEL_SET(val, 0x0);
  967. serdes_wr(ctx, lane, RXTX_REG61, val);
  968. serdes_rd(ctx, lane, RXTX_REG62, &val);
  969. val = RXTX_REG62_PERIOD_H1_QLATCH_SET(val, 0x0);
  970. serdes_wr(ctx, lane, RXTX_REG62, val);
  971. /* Set BW select tap X for DFE loop */
  972. for (i = 0; i < 9; i++) {
  973. reg = RXTX_REG81 + i * 2;
  974. serdes_rd(ctx, lane, reg, &val);
  975. val = RXTX_REG89_MU_TH7_SET(val, 0xe);
  976. val = RXTX_REG89_MU_TH8_SET(val, 0xe);
  977. val = RXTX_REG89_MU_TH9_SET(val, 0xe);
  978. serdes_wr(ctx, lane, reg, val);
  979. }
  980. /* Set BW select tap X for frequency adjust loop */
  981. for (i = 0; i < 3; i++) {
  982. reg = RXTX_REG96 + i * 2;
  983. serdes_rd(ctx, lane, reg, &val);
  984. val = RXTX_REG96_MU_FREQ1_SET(val, 0x10);
  985. val = RXTX_REG96_MU_FREQ2_SET(val, 0x10);
  986. val = RXTX_REG96_MU_FREQ3_SET(val, 0x10);
  987. serdes_wr(ctx, lane, reg, val);
  988. }
  989. /* Set BW select tap X for phase adjust loop */
  990. for (i = 0; i < 3; i++) {
  991. reg = RXTX_REG99 + i * 2;
  992. serdes_rd(ctx, lane, reg, &val);
  993. val = RXTX_REG99_MU_PHASE1_SET(val, 0x7);
  994. val = RXTX_REG99_MU_PHASE2_SET(val, 0x7);
  995. val = RXTX_REG99_MU_PHASE3_SET(val, 0x7);
  996. serdes_wr(ctx, lane, reg, val);
  997. }
  998. serdes_rd(ctx, lane, RXTX_REG102, &val);
  999. val = RXTX_REG102_FREQLOOP_LIMIT_SET(val, 0x0);
  1000. serdes_wr(ctx, lane, RXTX_REG102, val);
  1001. serdes_wr(ctx, lane, RXTX_REG114, 0xffe0);
  1002. serdes_rd(ctx, lane, RXTX_REG125, &val);
  1003. val = RXTX_REG125_SIGN_PQ_SET(val,
  1004. ctx->sata_param.txeyedirection[lane * 3 +
  1005. ctx->sata_param.speed[lane]]);
  1006. val = RXTX_REG125_PQ_REG_SET(val,
  1007. ctx->sata_param.txeyetuning[lane * 3 +
  1008. ctx->sata_param.speed[lane]]);
  1009. val = RXTX_REG125_PHZ_MANUAL_SET(val, 0x1);
  1010. serdes_wr(ctx, lane, RXTX_REG125, val);
  1011. serdes_rd(ctx, lane, RXTX_REG127, &val);
  1012. val = RXTX_REG127_LATCH_MAN_CAL_ENA_SET(val, 0x0);
  1013. serdes_wr(ctx, lane, RXTX_REG127, val);
  1014. serdes_rd(ctx, lane, RXTX_REG128, &val);
  1015. val = RXTX_REG128_LATCH_CAL_WAIT_SEL_SET(val, 0x3);
  1016. serdes_wr(ctx, lane, RXTX_REG128, val);
  1017. serdes_rd(ctx, lane, RXTX_REG145, &val);
  1018. val = RXTX_REG145_RXDFE_CONFIG_SET(val, 0x3);
  1019. val = RXTX_REG145_TX_IDLE_SATA_SET(val, 0x0);
  1020. if (preA3Chip) {
  1021. val = RXTX_REG145_RXES_ENA_SET(val, 0x1);
  1022. val = RXTX_REG145_RXVWES_LATENA_SET(val, 0x1);
  1023. } else {
  1024. val = RXTX_REG145_RXES_ENA_SET(val, 0x0);
  1025. val = RXTX_REG145_RXVWES_LATENA_SET(val, 0x0);
  1026. }
  1027. serdes_wr(ctx, lane, RXTX_REG145, val);
  1028. /*
  1029. * Set Rx LOS filter clock rate, sample rate, and threshold
  1030. * windows
  1031. */
  1032. for (i = 0; i < 4; i++) {
  1033. reg = RXTX_REG148 + i * 2;
  1034. serdes_wr(ctx, lane, reg, 0xFFFF);
  1035. }
  1036. }
  1037. }
  1038. static int xgene_phy_cal_rdy_chk(struct xgene_phy_ctx *ctx,
  1039. enum cmu_type_t cmu_type,
  1040. enum clk_type_t clk_type)
  1041. {
  1042. void __iomem *csr_serdes = ctx->sds_base;
  1043. int loop;
  1044. u32 val;
  1045. /* Release PHY main reset */
  1046. writel(0xdf, csr_serdes + SATA_ENET_SDS_RST_CTL);
  1047. readl(csr_serdes + SATA_ENET_SDS_RST_CTL); /* Force a barrier */
  1048. if (cmu_type != REF_CMU) {
  1049. cmu_setbits(ctx, cmu_type, CMU_REG5, CMU_REG5_PLL_RESETB_MASK);
  1050. /*
  1051. * As per PHY design spec, the PLL reset requires a minimum
  1052. * of 800us.
  1053. */
  1054. usleep_range(800, 1000);
  1055. cmu_rd(ctx, cmu_type, CMU_REG1, &val);
  1056. val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x0);
  1057. cmu_wr(ctx, cmu_type, CMU_REG1, val);
  1058. /*
  1059. * As per PHY design spec, the PLL auto calibration requires
  1060. * a minimum of 800us.
  1061. */
  1062. usleep_range(800, 1000);
  1063. cmu_toggle1to0(ctx, cmu_type, CMU_REG32,
  1064. CMU_REG32_FORCE_VCOCAL_START_MASK);
  1065. /*
  1066. * As per PHY design spec, the PLL requires a minimum of
  1067. * 800us to settle.
  1068. */
  1069. usleep_range(800, 1000);
  1070. }
  1071. if (!preA3Chip)
  1072. goto skip_manual_cal;
  1073. /*
  1074. * Configure the termination resister calibration
  1075. * The serial receive pins, RXP/RXN, have TERMination resistor
  1076. * that is required to be calibrated.
  1077. */
  1078. cmu_rd(ctx, cmu_type, CMU_REG17, &val);
  1079. val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x12);
  1080. val = CMU_REG17_RESERVED_7_SET(val, 0x0);
  1081. cmu_wr(ctx, cmu_type, CMU_REG17, val);
  1082. cmu_toggle1to0(ctx, cmu_type, CMU_REG17,
  1083. CMU_REG17_PVT_TERM_MAN_ENA_MASK);
  1084. /*
  1085. * The serial transmit pins, TXP/TXN, have Pull-UP and Pull-DOWN
  1086. * resistors that are required to the calibrated.
  1087. * Configure the pull DOWN calibration
  1088. */
  1089. cmu_rd(ctx, cmu_type, CMU_REG17, &val);
  1090. val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x29);
  1091. val = CMU_REG17_RESERVED_7_SET(val, 0x0);
  1092. cmu_wr(ctx, cmu_type, CMU_REG17, val);
  1093. cmu_toggle1to0(ctx, cmu_type, CMU_REG16,
  1094. CMU_REG16_PVT_DN_MAN_ENA_MASK);
  1095. /* Configure the pull UP calibration */
  1096. cmu_rd(ctx, cmu_type, CMU_REG17, &val);
  1097. val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x28);
  1098. val = CMU_REG17_RESERVED_7_SET(val, 0x0);
  1099. cmu_wr(ctx, cmu_type, CMU_REG17, val);
  1100. cmu_toggle1to0(ctx, cmu_type, CMU_REG16,
  1101. CMU_REG16_PVT_UP_MAN_ENA_MASK);
  1102. skip_manual_cal:
  1103. /* Poll the PLL calibration completion status for at least 1 ms */
  1104. loop = 100;
  1105. do {
  1106. cmu_rd(ctx, cmu_type, CMU_REG7, &val);
  1107. if (CMU_REG7_PLL_CALIB_DONE_RD(val))
  1108. break;
  1109. /*
  1110. * As per PHY design spec, PLL calibration status requires
  1111. * a minimum of 10us to be updated.
  1112. */
  1113. usleep_range(10, 100);
  1114. } while (--loop > 0);
  1115. cmu_rd(ctx, cmu_type, CMU_REG7, &val);
  1116. dev_dbg(ctx->dev, "PLL calibration %s\n",
  1117. CMU_REG7_PLL_CALIB_DONE_RD(val) ? "done" : "failed");
  1118. if (CMU_REG7_VCO_CAL_FAIL_RD(val)) {
  1119. dev_err(ctx->dev,
  1120. "PLL calibration failed due to VCO failure\n");
  1121. return -1;
  1122. }
  1123. dev_dbg(ctx->dev, "PLL calibration successful\n");
  1124. cmu_rd(ctx, cmu_type, CMU_REG15, &val);
  1125. dev_dbg(ctx->dev, "PHY Tx is %sready\n", val & 0x300 ? "" : "not ");
  1126. return 0;
  1127. }
  1128. static void xgene_phy_pdwn_force_vco(struct xgene_phy_ctx *ctx,
  1129. enum cmu_type_t cmu_type,
  1130. enum clk_type_t clk_type)
  1131. {
  1132. u32 val;
  1133. dev_dbg(ctx->dev, "Reset VCO and re-start again\n");
  1134. if (cmu_type == PHY_CMU) {
  1135. cmu_rd(ctx, cmu_type, CMU_REG16, &val);
  1136. val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x7);
  1137. cmu_wr(ctx, cmu_type, CMU_REG16, val);
  1138. }
  1139. cmu_toggle1to0(ctx, cmu_type, CMU_REG0, CMU_REG0_PDOWN_MASK);
  1140. cmu_toggle1to0(ctx, cmu_type, CMU_REG32,
  1141. CMU_REG32_FORCE_VCOCAL_START_MASK);
  1142. }
  1143. static int xgene_phy_hw_init_sata(struct xgene_phy_ctx *ctx,
  1144. enum clk_type_t clk_type, int ssc_enable)
  1145. {
  1146. void __iomem *sds_base = ctx->sds_base;
  1147. u32 val;
  1148. int i;
  1149. /* Configure the PHY for operation */
  1150. dev_dbg(ctx->dev, "Reset PHY\n");
  1151. /* Place PHY into reset */
  1152. writel(0x0, sds_base + SATA_ENET_SDS_RST_CTL);
  1153. val = readl(sds_base + SATA_ENET_SDS_RST_CTL); /* Force a barrier */
  1154. /* Release PHY lane from reset (active high) */
  1155. writel(0x20, sds_base + SATA_ENET_SDS_RST_CTL);
  1156. readl(sds_base + SATA_ENET_SDS_RST_CTL); /* Force a barrier */
  1157. /* Release all PHY module out of reset except PHY main reset */
  1158. writel(0xde, sds_base + SATA_ENET_SDS_RST_CTL);
  1159. readl(sds_base + SATA_ENET_SDS_RST_CTL); /* Force a barrier */
  1160. /* Set the operation speed */
  1161. val = readl(sds_base + SATA_ENET_SDS_CTL1);
  1162. val = CFG_I_SPD_SEL_CDR_OVR1_SET(val,
  1163. ctx->sata_param.txspeed[ctx->sata_param.speed[0]]);
  1164. writel(val, sds_base + SATA_ENET_SDS_CTL1);
  1165. dev_dbg(ctx->dev, "Set the customer pin mode to SATA\n");
  1166. val = readl(sds_base + SATA_ENET_SDS_CTL0);
  1167. val = REGSPEC_CFG_I_CUSTOMER_PIN_MODE0_SET(val, 0x4421);
  1168. writel(val, sds_base + SATA_ENET_SDS_CTL0);
  1169. /* Configure the clock macro unit (CMU) clock type */
  1170. xgene_phy_cfg_cmu_clk_type(ctx, PHY_CMU, clk_type);
  1171. /* Configure the clock macro */
  1172. xgene_phy_sata_cfg_cmu_core(ctx, PHY_CMU, clk_type);
  1173. /* Enable SSC if enabled */
  1174. if (ssc_enable)
  1175. xgene_phy_ssc_enable(ctx, PHY_CMU);
  1176. /* Configure PHY lanes */
  1177. xgene_phy_sata_cfg_lanes(ctx);
  1178. /* Set Rx/Tx 20-bit */
  1179. val = readl(sds_base + SATA_ENET_SDS_PCS_CTL0);
  1180. val = REGSPEC_CFG_I_RX_WORDMODE0_SET(val, 0x3);
  1181. val = REGSPEC_CFG_I_TX_WORDMODE0_SET(val, 0x3);
  1182. writel(val, sds_base + SATA_ENET_SDS_PCS_CTL0);
  1183. /* Start PLL calibration and try for three times */
  1184. i = 10;
  1185. do {
  1186. if (!xgene_phy_cal_rdy_chk(ctx, PHY_CMU, clk_type))
  1187. break;
  1188. /* If failed, toggle the VCO power signal and start again */
  1189. xgene_phy_pdwn_force_vco(ctx, PHY_CMU, clk_type);
  1190. } while (--i > 0);
  1191. /* Even on failure, allow to continue any way */
  1192. if (i <= 0)
  1193. dev_err(ctx->dev, "PLL calibration failed\n");
  1194. return 0;
  1195. }
  1196. static int xgene_phy_hw_initialize(struct xgene_phy_ctx *ctx,
  1197. enum clk_type_t clk_type,
  1198. int ssc_enable)
  1199. {
  1200. int rc;
  1201. dev_dbg(ctx->dev, "PHY init clk type %d\n", clk_type);
  1202. if (ctx->mode == MODE_SATA) {
  1203. rc = xgene_phy_hw_init_sata(ctx, clk_type, ssc_enable);
  1204. if (rc)
  1205. return rc;
  1206. } else {
  1207. dev_err(ctx->dev, "Un-supported customer pin mode %d\n",
  1208. ctx->mode);
  1209. return -ENODEV;
  1210. }
  1211. return 0;
  1212. }
  1213. /*
  1214. * Receiver Offset Calibration:
  1215. *
  1216. * Calibrate the receiver signal path offset in two steps - summar and
  1217. * latch calibrations
  1218. */
  1219. static void xgene_phy_force_lat_summer_cal(struct xgene_phy_ctx *ctx, int lane)
  1220. {
  1221. int i;
  1222. static const struct {
  1223. u32 reg;
  1224. u32 val;
  1225. } serdes_reg[] = {
  1226. {RXTX_REG38, 0x0},
  1227. {RXTX_REG39, 0xff00},
  1228. {RXTX_REG40, 0xffff},
  1229. {RXTX_REG41, 0xffff},
  1230. {RXTX_REG42, 0xffff},
  1231. {RXTX_REG43, 0xffff},
  1232. {RXTX_REG44, 0xffff},
  1233. {RXTX_REG45, 0xffff},
  1234. {RXTX_REG46, 0xffff},
  1235. {RXTX_REG47, 0xfffc},
  1236. {RXTX_REG48, 0x0},
  1237. {RXTX_REG49, 0x0},
  1238. {RXTX_REG50, 0x0},
  1239. {RXTX_REG51, 0x0},
  1240. {RXTX_REG52, 0x0},
  1241. {RXTX_REG53, 0x0},
  1242. {RXTX_REG54, 0x0},
  1243. {RXTX_REG55, 0x0},
  1244. };
  1245. /* Start SUMMER calibration */
  1246. serdes_setbits(ctx, lane, RXTX_REG127,
  1247. RXTX_REG127_FORCE_SUM_CAL_START_MASK);
  1248. /*
  1249. * As per PHY design spec, the Summer calibration requires a minimum
  1250. * of 100us to complete.
  1251. */
  1252. usleep_range(100, 500);
  1253. serdes_clrbits(ctx, lane, RXTX_REG127,
  1254. RXTX_REG127_FORCE_SUM_CAL_START_MASK);
  1255. /*
  1256. * As per PHY design spec, the auto calibration requires a minimum
  1257. * of 100us to complete.
  1258. */
  1259. usleep_range(100, 500);
  1260. /* Start latch calibration */
  1261. serdes_setbits(ctx, lane, RXTX_REG127,
  1262. RXTX_REG127_FORCE_LAT_CAL_START_MASK);
  1263. /*
  1264. * As per PHY design spec, the latch calibration requires a minimum
  1265. * of 100us to complete.
  1266. */
  1267. usleep_range(100, 500);
  1268. serdes_clrbits(ctx, lane, RXTX_REG127,
  1269. RXTX_REG127_FORCE_LAT_CAL_START_MASK);
  1270. /* Configure the PHY lane for calibration */
  1271. serdes_wr(ctx, lane, RXTX_REG28, 0x7);
  1272. serdes_wr(ctx, lane, RXTX_REG31, 0x7e00);
  1273. serdes_clrbits(ctx, lane, RXTX_REG4,
  1274. RXTX_REG4_TX_LOOPBACK_BUF_EN_MASK);
  1275. serdes_clrbits(ctx, lane, RXTX_REG7,
  1276. RXTX_REG7_LOOP_BACK_ENA_CTLE_MASK);
  1277. for (i = 0; i < ARRAY_SIZE(serdes_reg); i++)
  1278. serdes_wr(ctx, lane, serdes_reg[i].reg,
  1279. serdes_reg[i].val);
  1280. }
  1281. static void xgene_phy_reset_rxd(struct xgene_phy_ctx *ctx, int lane)
  1282. {
  1283. /* Reset digital Rx */
  1284. serdes_clrbits(ctx, lane, RXTX_REG7, RXTX_REG7_RESETB_RXD_MASK);
  1285. /* As per PHY design spec, the reset requires a minimum of 100us. */
  1286. usleep_range(100, 150);
  1287. serdes_setbits(ctx, lane, RXTX_REG7, RXTX_REG7_RESETB_RXD_MASK);
  1288. }
  1289. static int xgene_phy_get_avg(int accum, int samples)
  1290. {
  1291. return (accum + (samples / 2)) / samples;
  1292. }
  1293. static void xgene_phy_gen_avg_val(struct xgene_phy_ctx *ctx, int lane)
  1294. {
  1295. int max_loop = 10;
  1296. int avg_loop = 0;
  1297. int lat_do = 0, lat_xo = 0, lat_eo = 0, lat_so = 0;
  1298. int lat_de = 0, lat_xe = 0, lat_ee = 0, lat_se = 0;
  1299. int sum_cal = 0;
  1300. int lat_do_itr, lat_xo_itr, lat_eo_itr, lat_so_itr;
  1301. int lat_de_itr, lat_xe_itr, lat_ee_itr, lat_se_itr;
  1302. int sum_cal_itr;
  1303. int fail_even;
  1304. int fail_odd;
  1305. u32 val;
  1306. dev_dbg(ctx->dev, "Generating avg calibration value for lane %d\n",
  1307. lane);
  1308. /* Enable RX Hi-Z termination */
  1309. serdes_setbits(ctx, lane, RXTX_REG12,
  1310. RXTX_REG12_RX_DET_TERM_ENABLE_MASK);
  1311. /* Turn off DFE */
  1312. serdes_wr(ctx, lane, RXTX_REG28, 0x0000);
  1313. /* DFE Presets to zero */
  1314. serdes_wr(ctx, lane, RXTX_REG31, 0x0000);
  1315. /*
  1316. * Receiver Offset Calibration:
  1317. * Calibrate the receiver signal path offset in two steps - summar
  1318. * and latch calibration.
  1319. * Runs the "Receiver Offset Calibration multiple times to determine
  1320. * the average value to use.
  1321. */
  1322. while (avg_loop < max_loop) {
  1323. /* Start the calibration */
  1324. xgene_phy_force_lat_summer_cal(ctx, lane);
  1325. serdes_rd(ctx, lane, RXTX_REG21, &val);
  1326. lat_do_itr = RXTX_REG21_DO_LATCH_CALOUT_RD(val);
  1327. lat_xo_itr = RXTX_REG21_XO_LATCH_CALOUT_RD(val);
  1328. fail_odd = RXTX_REG21_LATCH_CAL_FAIL_ODD_RD(val);
  1329. serdes_rd(ctx, lane, RXTX_REG22, &val);
  1330. lat_eo_itr = RXTX_REG22_EO_LATCH_CALOUT_RD(val);
  1331. lat_so_itr = RXTX_REG22_SO_LATCH_CALOUT_RD(val);
  1332. fail_even = RXTX_REG22_LATCH_CAL_FAIL_EVEN_RD(val);
  1333. serdes_rd(ctx, lane, RXTX_REG23, &val);
  1334. lat_de_itr = RXTX_REG23_DE_LATCH_CALOUT_RD(val);
  1335. lat_xe_itr = RXTX_REG23_XE_LATCH_CALOUT_RD(val);
  1336. serdes_rd(ctx, lane, RXTX_REG24, &val);
  1337. lat_ee_itr = RXTX_REG24_EE_LATCH_CALOUT_RD(val);
  1338. lat_se_itr = RXTX_REG24_SE_LATCH_CALOUT_RD(val);
  1339. serdes_rd(ctx, lane, RXTX_REG121, &val);
  1340. sum_cal_itr = RXTX_REG121_SUMOS_CAL_CODE_RD(val);
  1341. /* Check for failure. If passed, sum them for averaging */
  1342. if ((fail_even == 0 || fail_even == 1) &&
  1343. (fail_odd == 0 || fail_odd == 1)) {
  1344. lat_do += lat_do_itr;
  1345. lat_xo += lat_xo_itr;
  1346. lat_eo += lat_eo_itr;
  1347. lat_so += lat_so_itr;
  1348. lat_de += lat_de_itr;
  1349. lat_xe += lat_xe_itr;
  1350. lat_ee += lat_ee_itr;
  1351. lat_se += lat_se_itr;
  1352. sum_cal += sum_cal_itr;
  1353. dev_dbg(ctx->dev, "Iteration %d:\n", avg_loop);
  1354. dev_dbg(ctx->dev, "DO 0x%x XO 0x%x EO 0x%x SO 0x%x\n",
  1355. lat_do_itr, lat_xo_itr, lat_eo_itr,
  1356. lat_so_itr);
  1357. dev_dbg(ctx->dev, "DE 0x%x XE 0x%x EE 0x%x SE 0x%x\n",
  1358. lat_de_itr, lat_xe_itr, lat_ee_itr,
  1359. lat_se_itr);
  1360. dev_dbg(ctx->dev, "SUM 0x%x\n", sum_cal_itr);
  1361. ++avg_loop;
  1362. } else {
  1363. dev_err(ctx->dev,
  1364. "Receiver calibration failed at %d loop\n",
  1365. avg_loop);
  1366. }
  1367. xgene_phy_reset_rxd(ctx, lane);
  1368. }
  1369. /* Update latch manual calibration with average value */
  1370. serdes_rd(ctx, lane, RXTX_REG127, &val);
  1371. val = RXTX_REG127_DO_LATCH_MANCAL_SET(val,
  1372. xgene_phy_get_avg(lat_do, max_loop));
  1373. val = RXTX_REG127_XO_LATCH_MANCAL_SET(val,
  1374. xgene_phy_get_avg(lat_xo, max_loop));
  1375. serdes_wr(ctx, lane, RXTX_REG127, val);
  1376. serdes_rd(ctx, lane, RXTX_REG128, &val);
  1377. val = RXTX_REG128_EO_LATCH_MANCAL_SET(val,
  1378. xgene_phy_get_avg(lat_eo, max_loop));
  1379. val = RXTX_REG128_SO_LATCH_MANCAL_SET(val,
  1380. xgene_phy_get_avg(lat_so, max_loop));
  1381. serdes_wr(ctx, lane, RXTX_REG128, val);
  1382. serdes_rd(ctx, lane, RXTX_REG129, &val);
  1383. val = RXTX_REG129_DE_LATCH_MANCAL_SET(val,
  1384. xgene_phy_get_avg(lat_de, max_loop));
  1385. val = RXTX_REG129_XE_LATCH_MANCAL_SET(val,
  1386. xgene_phy_get_avg(lat_xe, max_loop));
  1387. serdes_wr(ctx, lane, RXTX_REG129, val);
  1388. serdes_rd(ctx, lane, RXTX_REG130, &val);
  1389. val = RXTX_REG130_EE_LATCH_MANCAL_SET(val,
  1390. xgene_phy_get_avg(lat_ee, max_loop));
  1391. val = RXTX_REG130_SE_LATCH_MANCAL_SET(val,
  1392. xgene_phy_get_avg(lat_se, max_loop));
  1393. serdes_wr(ctx, lane, RXTX_REG130, val);
  1394. /* Update SUMMER calibration with average value */
  1395. serdes_rd(ctx, lane, RXTX_REG14, &val);
  1396. val = RXTX_REG14_CLTE_LATCAL_MAN_PROG_SET(val,
  1397. xgene_phy_get_avg(sum_cal, max_loop));
  1398. serdes_wr(ctx, lane, RXTX_REG14, val);
  1399. dev_dbg(ctx->dev, "Average Value:\n");
  1400. dev_dbg(ctx->dev, "DO 0x%x XO 0x%x EO 0x%x SO 0x%x\n",
  1401. xgene_phy_get_avg(lat_do, max_loop),
  1402. xgene_phy_get_avg(lat_xo, max_loop),
  1403. xgene_phy_get_avg(lat_eo, max_loop),
  1404. xgene_phy_get_avg(lat_so, max_loop));
  1405. dev_dbg(ctx->dev, "DE 0x%x XE 0x%x EE 0x%x SE 0x%x\n",
  1406. xgene_phy_get_avg(lat_de, max_loop),
  1407. xgene_phy_get_avg(lat_xe, max_loop),
  1408. xgene_phy_get_avg(lat_ee, max_loop),
  1409. xgene_phy_get_avg(lat_se, max_loop));
  1410. dev_dbg(ctx->dev, "SUM 0x%x\n",
  1411. xgene_phy_get_avg(sum_cal, max_loop));
  1412. serdes_rd(ctx, lane, RXTX_REG14, &val);
  1413. val = RXTX_REG14_CTLE_LATCAL_MAN_ENA_SET(val, 0x1);
  1414. serdes_wr(ctx, lane, RXTX_REG14, val);
  1415. dev_dbg(ctx->dev, "Enable Manual Summer calibration\n");
  1416. serdes_rd(ctx, lane, RXTX_REG127, &val);
  1417. val = RXTX_REG127_LATCH_MAN_CAL_ENA_SET(val, 0x1);
  1418. dev_dbg(ctx->dev, "Enable Manual Latch calibration\n");
  1419. serdes_wr(ctx, lane, RXTX_REG127, val);
  1420. /* Disable RX Hi-Z termination */
  1421. serdes_rd(ctx, lane, RXTX_REG12, &val);
  1422. val = RXTX_REG12_RX_DET_TERM_ENABLE_SET(val, 0);
  1423. serdes_wr(ctx, lane, RXTX_REG12, val);
  1424. /* Turn on DFE */
  1425. serdes_wr(ctx, lane, RXTX_REG28, 0x0007);
  1426. /* Set DFE preset */
  1427. serdes_wr(ctx, lane, RXTX_REG31, 0x7e00);
  1428. }
  1429. static int xgene_phy_hw_init(struct phy *phy)
  1430. {
  1431. struct xgene_phy_ctx *ctx = phy_get_drvdata(phy);
  1432. int rc;
  1433. int i;
  1434. rc = xgene_phy_hw_initialize(ctx, CLK_EXT_DIFF, SSC_DISABLE);
  1435. if (rc) {
  1436. dev_err(ctx->dev, "PHY initialize failed %d\n", rc);
  1437. return rc;
  1438. }
  1439. /* Setup clock properly after PHY configuration */
  1440. if (!IS_ERR(ctx->clk)) {
  1441. /* HW requires an toggle of the clock */
  1442. clk_prepare_enable(ctx->clk);
  1443. clk_disable_unprepare(ctx->clk);
  1444. clk_prepare_enable(ctx->clk);
  1445. }
  1446. /* Compute average value */
  1447. for (i = 0; i < MAX_LANE; i++)
  1448. xgene_phy_gen_avg_val(ctx, i);
  1449. dev_dbg(ctx->dev, "PHY initialized\n");
  1450. return 0;
  1451. }
  1452. static const struct phy_ops xgene_phy_ops = {
  1453. .init = xgene_phy_hw_init,
  1454. .owner = THIS_MODULE,
  1455. };
  1456. static struct phy *xgene_phy_xlate(struct device *dev,
  1457. struct of_phandle_args *args)
  1458. {
  1459. struct xgene_phy_ctx *ctx = dev_get_drvdata(dev);
  1460. if (args->args_count <= 0)
  1461. return ERR_PTR(-EINVAL);
  1462. if (args->args[0] >= MODE_MAX)
  1463. return ERR_PTR(-EINVAL);
  1464. ctx->mode = args->args[0];
  1465. return ctx->phy;
  1466. }
  1467. static void xgene_phy_get_param(struct platform_device *pdev,
  1468. const char *name, u32 *buffer,
  1469. int count, u32 *default_val,
  1470. u32 conv_factor)
  1471. {
  1472. int i;
  1473. if (!of_property_read_u32_array(pdev->dev.of_node, name, buffer,
  1474. count)) {
  1475. for (i = 0; i < count; i++)
  1476. buffer[i] /= conv_factor;
  1477. return;
  1478. }
  1479. /* Does not exist, load default */
  1480. for (i = 0; i < count; i++)
  1481. buffer[i] = default_val[i % 3];
  1482. }
  1483. static int xgene_phy_probe(struct platform_device *pdev)
  1484. {
  1485. struct phy_provider *phy_provider;
  1486. struct xgene_phy_ctx *ctx;
  1487. struct resource *res;
  1488. u32 default_spd[] = DEFAULT_SATA_SPD_SEL;
  1489. u32 default_txboost_gain[] = DEFAULT_SATA_TXBOOST_GAIN;
  1490. u32 default_txeye_direction[] = DEFAULT_SATA_TXEYEDIRECTION;
  1491. u32 default_txeye_tuning[] = DEFAULT_SATA_TXEYETUNING;
  1492. u32 default_txamp[] = DEFAULT_SATA_TXAMP;
  1493. u32 default_txcn1[] = DEFAULT_SATA_TXCN1;
  1494. u32 default_txcn2[] = DEFAULT_SATA_TXCN2;
  1495. u32 default_txcp1[] = DEFAULT_SATA_TXCP1;
  1496. int i;
  1497. ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
  1498. if (!ctx)
  1499. return -ENOMEM;
  1500. ctx->dev = &pdev->dev;
  1501. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1502. ctx->sds_base = devm_ioremap_resource(&pdev->dev, res);
  1503. if (IS_ERR(ctx->sds_base))
  1504. return PTR_ERR(ctx->sds_base);
  1505. /* Retrieve optional clock */
  1506. ctx->clk = clk_get(&pdev->dev, NULL);
  1507. /* Load override paramaters */
  1508. xgene_phy_get_param(pdev, "apm,tx-eye-tuning",
  1509. ctx->sata_param.txeyetuning, 6, default_txeye_tuning, 1);
  1510. xgene_phy_get_param(pdev, "apm,tx-eye-direction",
  1511. ctx->sata_param.txeyedirection, 6, default_txeye_direction, 1);
  1512. xgene_phy_get_param(pdev, "apm,tx-boost-gain",
  1513. ctx->sata_param.txboostgain, 6, default_txboost_gain, 1);
  1514. xgene_phy_get_param(pdev, "apm,tx-amplitude",
  1515. ctx->sata_param.txamplitude, 6, default_txamp, 13300);
  1516. xgene_phy_get_param(pdev, "apm,tx-pre-cursor1",
  1517. ctx->sata_param.txprecursor_cn1, 6, default_txcn1, 18200);
  1518. xgene_phy_get_param(pdev, "apm,tx-pre-cursor2",
  1519. ctx->sata_param.txprecursor_cn2, 6, default_txcn2, 18200);
  1520. xgene_phy_get_param(pdev, "apm,tx-post-cursor",
  1521. ctx->sata_param.txpostcursor_cp1, 6, default_txcp1, 18200);
  1522. xgene_phy_get_param(pdev, "apm,tx-speed",
  1523. ctx->sata_param.txspeed, 3, default_spd, 1);
  1524. for (i = 0; i < MAX_LANE; i++)
  1525. ctx->sata_param.speed[i] = 2; /* Default to Gen3 */
  1526. platform_set_drvdata(pdev, ctx);
  1527. ctx->phy = devm_phy_create(ctx->dev, NULL, &xgene_phy_ops);
  1528. if (IS_ERR(ctx->phy)) {
  1529. dev_dbg(&pdev->dev, "Failed to create PHY\n");
  1530. return PTR_ERR(ctx->phy);
  1531. }
  1532. phy_set_drvdata(ctx->phy, ctx);
  1533. phy_provider = devm_of_phy_provider_register(ctx->dev, xgene_phy_xlate);
  1534. return PTR_ERR_OR_ZERO(phy_provider);
  1535. }
  1536. static const struct of_device_id xgene_phy_of_match[] = {
  1537. {.compatible = "apm,xgene-phy",},
  1538. {},
  1539. };
  1540. MODULE_DEVICE_TABLE(of, xgene_phy_of_match);
  1541. static struct platform_driver xgene_phy_driver = {
  1542. .probe = xgene_phy_probe,
  1543. .driver = {
  1544. .name = "xgene-phy",
  1545. .of_match_table = xgene_phy_of_match,
  1546. },
  1547. };
  1548. module_platform_driver(xgene_phy_driver);
  1549. MODULE_DESCRIPTION("APM X-Gene Multi-Purpose PHY driver");
  1550. MODULE_AUTHOR("Loc Ho <lho@apm.com>");
  1551. MODULE_LICENSE("GPL v2");
  1552. MODULE_VERSION("0.1");