realtek.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /* drivers/net/phy/realtek.c
  3. *
  4. * Driver for Realtek PHYs
  5. *
  6. * Author: Johnson Leung <r58129@freescale.com>
  7. *
  8. * Copyright (c) 2004 Freescale Semiconductor, Inc.
  9. */
  10. #include <linux/bitops.h>
  11. #include <linux/phy.h>
  12. #include <linux/module.h>
  13. #include <linux/delay.h>
  14. #define RTL821x_PHYSR 0x11
  15. #define RTL821x_PHYSR_DUPLEX BIT(13)
  16. #define RTL821x_PHYSR_SPEED GENMASK(15, 14)
  17. #define RTL821x_INER 0x12
  18. #define RTL8211B_INER_INIT 0x6400
  19. #define RTL8211E_INER_LINK_STATUS BIT(10)
  20. #define RTL8211F_INER_LINK_STATUS BIT(4)
  21. #define RTL821x_INSR 0x13
  22. #define RTL821x_EXT_PAGE_SELECT 0x1e
  23. #define RTL821x_PAGE_SELECT 0x1f
  24. #define RTL8211F_PHYCR1 0x18
  25. #define RTL8211F_INSR 0x1d
  26. #define RTL8211F_TX_DELAY BIT(8)
  27. #define RTL8211F_RX_DELAY BIT(3)
  28. #define RTL8211F_ALDPS_PLL_OFF BIT(1)
  29. #define RTL8211F_ALDPS_ENABLE BIT(2)
  30. #define RTL8211F_ALDPS_XTAL_OFF BIT(12)
  31. #define RTL8211E_CTRL_DELAY BIT(13)
  32. #define RTL8211E_TX_DELAY BIT(12)
  33. #define RTL8211E_RX_DELAY BIT(11)
  34. #define RTL8201F_ISR 0x1e
  35. #define RTL8201F_IER 0x13
  36. #define RTL8366RB_POWER_SAVE 0x15
  37. #define RTL8366RB_POWER_SAVE_ON BIT(12)
  38. #define RTL_SUPPORTS_5000FULL BIT(14)
  39. #define RTL_SUPPORTS_2500FULL BIT(13)
  40. #define RTL_SUPPORTS_10000FULL BIT(0)
  41. #define RTL_ADV_2500FULL BIT(7)
  42. #define RTL_LPADV_10000FULL BIT(11)
  43. #define RTL_LPADV_5000FULL BIT(6)
  44. #define RTL_LPADV_2500FULL BIT(5)
  45. #define RTLGEN_SPEED_MASK 0x0630
  46. #define RTL_GENERIC_PHYID 0x001cc800
  47. MODULE_DESCRIPTION("Realtek PHY driver");
  48. MODULE_AUTHOR("Johnson Leung");
  49. MODULE_LICENSE("GPL");
  50. static int rtl821x_read_page(struct phy_device *phydev)
  51. {
  52. return __phy_read(phydev, RTL821x_PAGE_SELECT);
  53. }
  54. static int rtl821x_write_page(struct phy_device *phydev, int page)
  55. {
  56. return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
  57. }
  58. static int rtl8201_ack_interrupt(struct phy_device *phydev)
  59. {
  60. int err;
  61. err = phy_read(phydev, RTL8201F_ISR);
  62. return (err < 0) ? err : 0;
  63. }
  64. static int rtl821x_ack_interrupt(struct phy_device *phydev)
  65. {
  66. int err;
  67. err = phy_read(phydev, RTL821x_INSR);
  68. return (err < 0) ? err : 0;
  69. }
  70. static int rtl8211f_ack_interrupt(struct phy_device *phydev)
  71. {
  72. int err;
  73. err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
  74. return (err < 0) ? err : 0;
  75. }
  76. static int rtl8201_config_intr(struct phy_device *phydev)
  77. {
  78. u16 val;
  79. if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
  80. val = BIT(13) | BIT(12) | BIT(11);
  81. else
  82. val = 0;
  83. return phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
  84. }
  85. static int rtl8211b_config_intr(struct phy_device *phydev)
  86. {
  87. int err;
  88. if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
  89. err = phy_write(phydev, RTL821x_INER,
  90. RTL8211B_INER_INIT);
  91. else
  92. err = phy_write(phydev, RTL821x_INER, 0);
  93. return err;
  94. }
  95. static int rtl8211e_config_intr(struct phy_device *phydev)
  96. {
  97. int err;
  98. if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
  99. err = phy_write(phydev, RTL821x_INER,
  100. RTL8211E_INER_LINK_STATUS);
  101. else
  102. err = phy_write(phydev, RTL821x_INER, 0);
  103. return err;
  104. }
  105. static int rtl8211f_config_intr(struct phy_device *phydev)
  106. {
  107. u16 val;
  108. if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
  109. val = RTL8211F_INER_LINK_STATUS;
  110. else
  111. val = 0;
  112. return phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
  113. }
  114. static int rtl8211_config_aneg(struct phy_device *phydev)
  115. {
  116. int ret;
  117. ret = genphy_config_aneg(phydev);
  118. if (ret < 0)
  119. return ret;
  120. /* Quirk was copied from vendor driver. Unfortunately it includes no
  121. * description of the magic numbers.
  122. */
  123. if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
  124. phy_write(phydev, 0x17, 0x2138);
  125. phy_write(phydev, 0x0e, 0x0260);
  126. } else {
  127. phy_write(phydev, 0x17, 0x2108);
  128. phy_write(phydev, 0x0e, 0x0000);
  129. }
  130. return 0;
  131. }
  132. static int rtl8211c_config_init(struct phy_device *phydev)
  133. {
  134. /* RTL8211C has an issue when operating in Gigabit slave mode */
  135. return phy_set_bits(phydev, MII_CTRL1000,
  136. CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
  137. }
  138. static int rtl8211f_config_init(struct phy_device *phydev)
  139. {
  140. struct device *dev = &phydev->mdio.dev;
  141. u16 val_txdly, val_rxdly;
  142. u16 val;
  143. int ret;
  144. val = RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_XTAL_OFF;
  145. phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1, val, val);
  146. switch (phydev->interface) {
  147. case PHY_INTERFACE_MODE_RGMII:
  148. val_txdly = 0;
  149. val_rxdly = 0;
  150. break;
  151. case PHY_INTERFACE_MODE_RGMII_RXID:
  152. val_txdly = 0;
  153. val_rxdly = RTL8211F_RX_DELAY;
  154. break;
  155. case PHY_INTERFACE_MODE_RGMII_TXID:
  156. val_txdly = RTL8211F_TX_DELAY;
  157. val_rxdly = 0;
  158. break;
  159. case PHY_INTERFACE_MODE_RGMII_ID:
  160. val_txdly = RTL8211F_TX_DELAY;
  161. val_rxdly = RTL8211F_RX_DELAY;
  162. break;
  163. default: /* the rest of the modes imply leaving delay as is. */
  164. return 0;
  165. }
  166. ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY,
  167. val_txdly);
  168. if (ret < 0) {
  169. dev_err(dev, "Failed to update the TX delay register\n");
  170. return ret;
  171. } else if (ret) {
  172. dev_dbg(dev,
  173. "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n",
  174. val_txdly ? "Enabling" : "Disabling");
  175. } else {
  176. dev_dbg(dev,
  177. "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n",
  178. val_txdly ? "enabled" : "disabled");
  179. }
  180. ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY,
  181. val_rxdly);
  182. if (ret < 0) {
  183. dev_err(dev, "Failed to update the RX delay register\n");
  184. return ret;
  185. } else if (ret) {
  186. dev_dbg(dev,
  187. "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n",
  188. val_rxdly ? "Enabling" : "Disabling");
  189. } else {
  190. dev_dbg(dev,
  191. "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n",
  192. val_rxdly ? "enabled" : "disabled");
  193. }
  194. return 0;
  195. }
  196. static int rtl821x_resume(struct phy_device *phydev)
  197. {
  198. int ret;
  199. ret = genphy_resume(phydev);
  200. if (ret < 0)
  201. return ret;
  202. msleep(20);
  203. return 0;
  204. }
  205. static int rtl8211e_config_init(struct phy_device *phydev)
  206. {
  207. int ret = 0, oldpage;
  208. u16 val;
  209. /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
  210. switch (phydev->interface) {
  211. case PHY_INTERFACE_MODE_RGMII:
  212. val = RTL8211E_CTRL_DELAY | 0;
  213. break;
  214. case PHY_INTERFACE_MODE_RGMII_ID:
  215. val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
  216. break;
  217. case PHY_INTERFACE_MODE_RGMII_RXID:
  218. val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY;
  219. break;
  220. case PHY_INTERFACE_MODE_RGMII_TXID:
  221. val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY;
  222. break;
  223. default: /* the rest of the modes imply leaving delays as is. */
  224. return 0;
  225. }
  226. /* According to a sample driver there is a 0x1c config register on the
  227. * 0xa4 extension page (0x7) layout. It can be used to disable/enable
  228. * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins.
  229. * The configuration register definition:
  230. * 14 = reserved
  231. * 13 = Force Tx RX Delay controlled by bit12 bit11,
  232. * 12 = RX Delay, 11 = TX Delay
  233. * 10:0 = Test && debug settings reserved by realtek
  234. */
  235. oldpage = phy_select_page(phydev, 0x7);
  236. if (oldpage < 0)
  237. goto err_restore_page;
  238. ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);
  239. if (ret)
  240. goto err_restore_page;
  241. ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY
  242. | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
  243. val);
  244. err_restore_page:
  245. return phy_restore_page(phydev, oldpage, ret);
  246. }
  247. static int rtl8211b_suspend(struct phy_device *phydev)
  248. {
  249. phy_write(phydev, MII_MMD_DATA, BIT(9));
  250. return genphy_suspend(phydev);
  251. }
  252. static int rtl8211b_resume(struct phy_device *phydev)
  253. {
  254. phy_write(phydev, MII_MMD_DATA, 0);
  255. return genphy_resume(phydev);
  256. }
  257. static int rtl8366rb_config_init(struct phy_device *phydev)
  258. {
  259. int ret;
  260. ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
  261. RTL8366RB_POWER_SAVE_ON);
  262. if (ret) {
  263. dev_err(&phydev->mdio.dev,
  264. "error enabling power management\n");
  265. }
  266. return ret;
  267. }
  268. /* get actual speed to cover the downshift case */
  269. static int rtlgen_get_speed(struct phy_device *phydev)
  270. {
  271. int val;
  272. if (!phydev->link)
  273. return 0;
  274. val = phy_read_paged(phydev, 0xa43, 0x12);
  275. if (val < 0)
  276. return val;
  277. switch (val & RTLGEN_SPEED_MASK) {
  278. case 0x0000:
  279. phydev->speed = SPEED_10;
  280. break;
  281. case 0x0010:
  282. phydev->speed = SPEED_100;
  283. break;
  284. case 0x0020:
  285. phydev->speed = SPEED_1000;
  286. break;
  287. case 0x0200:
  288. phydev->speed = SPEED_10000;
  289. break;
  290. case 0x0210:
  291. phydev->speed = SPEED_2500;
  292. break;
  293. case 0x0220:
  294. phydev->speed = SPEED_5000;
  295. break;
  296. default:
  297. break;
  298. }
  299. return 0;
  300. }
  301. static int rtlgen_read_status(struct phy_device *phydev)
  302. {
  303. int ret;
  304. ret = genphy_read_status(phydev);
  305. if (ret < 0)
  306. return ret;
  307. return rtlgen_get_speed(phydev);
  308. }
  309. static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
  310. {
  311. int ret;
  312. if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) {
  313. rtl821x_write_page(phydev, 0xa5c);
  314. ret = __phy_read(phydev, 0x12);
  315. rtl821x_write_page(phydev, 0);
  316. } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
  317. rtl821x_write_page(phydev, 0xa5d);
  318. ret = __phy_read(phydev, 0x10);
  319. rtl821x_write_page(phydev, 0);
  320. } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) {
  321. rtl821x_write_page(phydev, 0xa5d);
  322. ret = __phy_read(phydev, 0x11);
  323. rtl821x_write_page(phydev, 0);
  324. } else {
  325. ret = -EOPNOTSUPP;
  326. }
  327. return ret;
  328. }
  329. static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
  330. u16 val)
  331. {
  332. int ret;
  333. if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
  334. rtl821x_write_page(phydev, 0xa5d);
  335. ret = __phy_write(phydev, 0x10, val);
  336. rtl821x_write_page(phydev, 0);
  337. } else {
  338. ret = -EOPNOTSUPP;
  339. }
  340. return ret;
  341. }
  342. static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
  343. {
  344. int ret = rtlgen_read_mmd(phydev, devnum, regnum);
  345. if (ret != -EOPNOTSUPP)
  346. return ret;
  347. if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) {
  348. rtl821x_write_page(phydev, 0xa6e);
  349. ret = __phy_read(phydev, 0x16);
  350. rtl821x_write_page(phydev, 0);
  351. } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
  352. rtl821x_write_page(phydev, 0xa6d);
  353. ret = __phy_read(phydev, 0x12);
  354. rtl821x_write_page(phydev, 0);
  355. } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) {
  356. rtl821x_write_page(phydev, 0xa6d);
  357. ret = __phy_read(phydev, 0x10);
  358. rtl821x_write_page(phydev, 0);
  359. }
  360. return ret;
  361. }
  362. static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
  363. u16 val)
  364. {
  365. int ret = rtlgen_write_mmd(phydev, devnum, regnum, val);
  366. if (ret != -EOPNOTSUPP)
  367. return ret;
  368. if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
  369. rtl821x_write_page(phydev, 0xa6d);
  370. ret = __phy_write(phydev, 0x12, val);
  371. rtl821x_write_page(phydev, 0);
  372. }
  373. return ret;
  374. }
  375. static int rtl822x_get_features(struct phy_device *phydev)
  376. {
  377. int val;
  378. val = phy_read_paged(phydev, 0xa61, 0x13);
  379. if (val < 0)
  380. return val;
  381. linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
  382. phydev->supported, val & RTL_SUPPORTS_2500FULL);
  383. linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
  384. phydev->supported, val & RTL_SUPPORTS_5000FULL);
  385. linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
  386. phydev->supported, val & RTL_SUPPORTS_10000FULL);
  387. return genphy_read_abilities(phydev);
  388. }
  389. static int rtl822x_config_aneg(struct phy_device *phydev)
  390. {
  391. int ret = 0;
  392. if (phydev->autoneg == AUTONEG_ENABLE) {
  393. u16 adv2500 = 0;
  394. if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
  395. phydev->advertising))
  396. adv2500 = RTL_ADV_2500FULL;
  397. ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12,
  398. RTL_ADV_2500FULL, adv2500);
  399. if (ret < 0)
  400. return ret;
  401. }
  402. return __genphy_config_aneg(phydev, ret);
  403. }
  404. static int rtl822x_read_status(struct phy_device *phydev)
  405. {
  406. int ret;
  407. if (phydev->autoneg == AUTONEG_ENABLE) {
  408. int lpadv = phy_read_paged(phydev, 0xa5d, 0x13);
  409. if (lpadv < 0)
  410. return lpadv;
  411. linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
  412. phydev->lp_advertising, lpadv & RTL_LPADV_10000FULL);
  413. linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
  414. phydev->lp_advertising, lpadv & RTL_LPADV_5000FULL);
  415. linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
  416. phydev->lp_advertising, lpadv & RTL_LPADV_2500FULL);
  417. }
  418. ret = genphy_read_status(phydev);
  419. if (ret < 0)
  420. return ret;
  421. return rtlgen_get_speed(phydev);
  422. }
  423. static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
  424. {
  425. int val;
  426. phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61);
  427. val = phy_read(phydev, 0x13);
  428. phy_write(phydev, RTL821x_PAGE_SELECT, 0);
  429. return val >= 0 && val & RTL_SUPPORTS_2500FULL;
  430. }
  431. static int rtlgen_match_phy_device(struct phy_device *phydev)
  432. {
  433. return phydev->phy_id == RTL_GENERIC_PHYID &&
  434. !rtlgen_supports_2_5gbps(phydev);
  435. }
  436. static int rtl8226_match_phy_device(struct phy_device *phydev)
  437. {
  438. return phydev->phy_id == RTL_GENERIC_PHYID &&
  439. rtlgen_supports_2_5gbps(phydev);
  440. }
  441. static int rtlgen_resume(struct phy_device *phydev)
  442. {
  443. int ret = genphy_resume(phydev);
  444. /* Internal PHY's from RTL8168h up may not be instantly ready */
  445. msleep(20);
  446. return ret;
  447. }
  448. static struct phy_driver realtek_drvs[] = {
  449. {
  450. PHY_ID_MATCH_EXACT(0x00008201),
  451. .name = "RTL8201CP Ethernet",
  452. .read_page = rtl821x_read_page,
  453. .write_page = rtl821x_write_page,
  454. }, {
  455. PHY_ID_MATCH_EXACT(0x001cc816),
  456. .name = "RTL8201F Fast Ethernet",
  457. .ack_interrupt = &rtl8201_ack_interrupt,
  458. .config_intr = &rtl8201_config_intr,
  459. .suspend = genphy_suspend,
  460. .resume = genphy_resume,
  461. .read_page = rtl821x_read_page,
  462. .write_page = rtl821x_write_page,
  463. }, {
  464. PHY_ID_MATCH_MODEL(0x001cc880),
  465. .name = "RTL8208 Fast Ethernet",
  466. .read_mmd = genphy_read_mmd_unsupported,
  467. .write_mmd = genphy_write_mmd_unsupported,
  468. .suspend = genphy_suspend,
  469. .resume = genphy_resume,
  470. .read_page = rtl821x_read_page,
  471. .write_page = rtl821x_write_page,
  472. }, {
  473. PHY_ID_MATCH_EXACT(0x001cc910),
  474. .name = "RTL8211 Gigabit Ethernet",
  475. .config_aneg = rtl8211_config_aneg,
  476. .read_mmd = &genphy_read_mmd_unsupported,
  477. .write_mmd = &genphy_write_mmd_unsupported,
  478. .read_page = rtl821x_read_page,
  479. .write_page = rtl821x_write_page,
  480. }, {
  481. PHY_ID_MATCH_EXACT(0x001cc912),
  482. .name = "RTL8211B Gigabit Ethernet",
  483. .ack_interrupt = &rtl821x_ack_interrupt,
  484. .config_intr = &rtl8211b_config_intr,
  485. .read_mmd = &genphy_read_mmd_unsupported,
  486. .write_mmd = &genphy_write_mmd_unsupported,
  487. .suspend = rtl8211b_suspend,
  488. .resume = rtl8211b_resume,
  489. .read_page = rtl821x_read_page,
  490. .write_page = rtl821x_write_page,
  491. }, {
  492. PHY_ID_MATCH_EXACT(0x001cc913),
  493. .name = "RTL8211C Gigabit Ethernet",
  494. .config_init = rtl8211c_config_init,
  495. .read_mmd = &genphy_read_mmd_unsupported,
  496. .write_mmd = &genphy_write_mmd_unsupported,
  497. .read_page = rtl821x_read_page,
  498. .write_page = rtl821x_write_page,
  499. }, {
  500. PHY_ID_MATCH_EXACT(0x001cc914),
  501. .name = "RTL8211DN Gigabit Ethernet",
  502. .ack_interrupt = rtl821x_ack_interrupt,
  503. .config_intr = rtl8211e_config_intr,
  504. .suspend = genphy_suspend,
  505. .resume = genphy_resume,
  506. .read_page = rtl821x_read_page,
  507. .write_page = rtl821x_write_page,
  508. }, {
  509. PHY_ID_MATCH_EXACT(0x001cc915),
  510. .name = "RTL8211E Gigabit Ethernet",
  511. .config_init = &rtl8211e_config_init,
  512. .ack_interrupt = &rtl821x_ack_interrupt,
  513. .config_intr = &rtl8211e_config_intr,
  514. .suspend = genphy_suspend,
  515. .resume = genphy_resume,
  516. .read_page = rtl821x_read_page,
  517. .write_page = rtl821x_write_page,
  518. }, {
  519. PHY_ID_MATCH_EXACT(0x001cc916),
  520. .name = "RTL8211F Gigabit Ethernet",
  521. .config_init = &rtl8211f_config_init,
  522. .ack_interrupt = &rtl8211f_ack_interrupt,
  523. .read_status = rtlgen_read_status,
  524. .config_intr = &rtl8211f_config_intr,
  525. .suspend = genphy_suspend,
  526. .resume = rtl821x_resume,
  527. .read_page = rtl821x_read_page,
  528. .write_page = rtl821x_write_page,
  529. }, {
  530. .name = "Generic FE-GE Realtek PHY",
  531. .match_phy_device = rtlgen_match_phy_device,
  532. .read_status = rtlgen_read_status,
  533. .suspend = genphy_suspend,
  534. .resume = rtlgen_resume,
  535. .read_page = rtl821x_read_page,
  536. .write_page = rtl821x_write_page,
  537. .read_mmd = rtlgen_read_mmd,
  538. .write_mmd = rtlgen_write_mmd,
  539. }, {
  540. .name = "RTL8226 2.5Gbps PHY",
  541. .match_phy_device = rtl8226_match_phy_device,
  542. .get_features = rtl822x_get_features,
  543. .config_aneg = rtl822x_config_aneg,
  544. .read_status = rtl822x_read_status,
  545. .suspend = genphy_suspend,
  546. .resume = rtlgen_resume,
  547. .read_page = rtl821x_read_page,
  548. .write_page = rtl821x_write_page,
  549. .read_mmd = rtl822x_read_mmd,
  550. .write_mmd = rtl822x_write_mmd,
  551. }, {
  552. PHY_ID_MATCH_EXACT(0x001cc840),
  553. .name = "RTL8226B_RTL8221B 2.5Gbps PHY",
  554. .get_features = rtl822x_get_features,
  555. .config_aneg = rtl822x_config_aneg,
  556. .read_status = rtl822x_read_status,
  557. .suspend = genphy_suspend,
  558. .resume = rtlgen_resume,
  559. .read_page = rtl821x_read_page,
  560. .write_page = rtl821x_write_page,
  561. .read_mmd = rtl822x_read_mmd,
  562. .write_mmd = rtl822x_write_mmd,
  563. }, {
  564. PHY_ID_MATCH_EXACT(0x001cc961),
  565. .name = "RTL8366RB Gigabit Ethernet",
  566. .config_init = &rtl8366rb_config_init,
  567. /* These interrupts are handled by the irq controller
  568. * embedded inside the RTL8366RB, they get unmasked when the
  569. * irq is requested and ACKed by reading the status register,
  570. * which is done by the irqchip code.
  571. */
  572. .ack_interrupt = genphy_no_ack_interrupt,
  573. .config_intr = genphy_no_config_intr,
  574. .suspend = genphy_suspend,
  575. .resume = genphy_resume,
  576. },
  577. };
  578. module_phy_driver(realtek_drvs);
  579. static const struct mdio_device_id __maybe_unused realtek_tbl[] = {
  580. { PHY_ID_MATCH_VENDOR(0x001cc800) },
  581. { }
  582. };
  583. MODULE_DEVICE_TABLE(mdio, realtek_tbl);