micrel.c 36 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * drivers/net/phy/micrel.c
  4. *
  5. * Driver for Micrel PHYs
  6. *
  7. * Author: David J. Choi
  8. *
  9. * Copyright (c) 2010-2013 Micrel, Inc.
  10. * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
  11. *
  12. * Support : Micrel Phys:
  13. * Giga phys: ksz9021, ksz9031, ksz9131
  14. * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
  15. * ksz8021, ksz8031, ksz8051,
  16. * ksz8081, ksz8091,
  17. * ksz8061,
  18. * Switch : ksz8873, ksz886x
  19. * ksz9477
  20. */
  21. #include <linux/bitfield.h>
  22. #include <linux/kernel.h>
  23. #include <linux/module.h>
  24. #include <linux/phy.h>
  25. #include <linux/micrel_phy.h>
  26. #include <linux/of.h>
  27. #include <linux/clk.h>
  28. #include <linux/delay.h>
  29. /* Operation Mode Strap Override */
  30. #define MII_KSZPHY_OMSO 0x16
  31. #define KSZPHY_OMSO_FACTORY_TEST BIT(15)
  32. #define KSZPHY_OMSO_B_CAST_OFF BIT(9)
  33. #define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
  34. #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
  35. #define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
  36. /* general Interrupt control/status reg in vendor specific block. */
  37. #define MII_KSZPHY_INTCS 0x1B
  38. #define KSZPHY_INTCS_JABBER BIT(15)
  39. #define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
  40. #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
  41. #define KSZPHY_INTCS_PARELLEL BIT(12)
  42. #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
  43. #define KSZPHY_INTCS_LINK_DOWN BIT(10)
  44. #define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
  45. #define KSZPHY_INTCS_LINK_UP BIT(8)
  46. #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
  47. KSZPHY_INTCS_LINK_DOWN)
  48. /* PHY Control 1 */
  49. #define MII_KSZPHY_CTRL_1 0x1e
  50. /* PHY Control 2 / PHY Control (if no PHY Control 1) */
  51. #define MII_KSZPHY_CTRL_2 0x1f
  52. #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
  53. /* bitmap of PHY register to set interrupt mode */
  54. #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
  55. #define KSZPHY_RMII_REF_CLK_SEL BIT(7)
  56. /* Write/read to/from extended registers */
  57. #define MII_KSZPHY_EXTREG 0x0b
  58. #define KSZPHY_EXTREG_WRITE 0x8000
  59. #define MII_KSZPHY_EXTREG_WRITE 0x0c
  60. #define MII_KSZPHY_EXTREG_READ 0x0d
  61. /* Extended registers */
  62. #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
  63. #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
  64. #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
  65. #define PS_TO_REG 200
  66. struct kszphy_hw_stat {
  67. const char *string;
  68. u8 reg;
  69. u8 bits;
  70. };
  71. static struct kszphy_hw_stat kszphy_hw_stats[] = {
  72. { "phy_receive_errors", 21, 16},
  73. { "phy_idle_errors", 10, 8 },
  74. };
  75. struct kszphy_type {
  76. u32 led_mode_reg;
  77. u16 interrupt_level_mask;
  78. bool has_broadcast_disable;
  79. bool has_nand_tree_disable;
  80. bool has_rmii_ref_clk_sel;
  81. };
  82. struct kszphy_priv {
  83. const struct kszphy_type *type;
  84. int led_mode;
  85. bool rmii_ref_clk_sel;
  86. bool rmii_ref_clk_sel_val;
  87. u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
  88. };
  89. static const struct kszphy_type ksz8021_type = {
  90. .led_mode_reg = MII_KSZPHY_CTRL_2,
  91. .has_broadcast_disable = true,
  92. .has_nand_tree_disable = true,
  93. .has_rmii_ref_clk_sel = true,
  94. };
  95. static const struct kszphy_type ksz8041_type = {
  96. .led_mode_reg = MII_KSZPHY_CTRL_1,
  97. };
  98. static const struct kszphy_type ksz8051_type = {
  99. .led_mode_reg = MII_KSZPHY_CTRL_2,
  100. .has_nand_tree_disable = true,
  101. };
  102. static const struct kszphy_type ksz8081_type = {
  103. .led_mode_reg = MII_KSZPHY_CTRL_2,
  104. .has_broadcast_disable = true,
  105. .has_nand_tree_disable = true,
  106. .has_rmii_ref_clk_sel = true,
  107. };
  108. static const struct kszphy_type ks8737_type = {
  109. .interrupt_level_mask = BIT(14),
  110. };
  111. static const struct kszphy_type ksz9021_type = {
  112. .interrupt_level_mask = BIT(14),
  113. };
  114. static int kszphy_extended_write(struct phy_device *phydev,
  115. u32 regnum, u16 val)
  116. {
  117. phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
  118. return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
  119. }
  120. static int kszphy_extended_read(struct phy_device *phydev,
  121. u32 regnum)
  122. {
  123. phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
  124. return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
  125. }
  126. static int kszphy_ack_interrupt(struct phy_device *phydev)
  127. {
  128. /* bit[7..0] int status, which is a read and clear register. */
  129. int rc;
  130. rc = phy_read(phydev, MII_KSZPHY_INTCS);
  131. return (rc < 0) ? rc : 0;
  132. }
  133. static int kszphy_config_intr(struct phy_device *phydev)
  134. {
  135. const struct kszphy_type *type = phydev->drv->driver_data;
  136. int temp;
  137. u16 mask;
  138. if (type && type->interrupt_level_mask)
  139. mask = type->interrupt_level_mask;
  140. else
  141. mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
  142. /* set the interrupt pin active low */
  143. temp = phy_read(phydev, MII_KSZPHY_CTRL);
  144. if (temp < 0)
  145. return temp;
  146. temp &= ~mask;
  147. phy_write(phydev, MII_KSZPHY_CTRL, temp);
  148. /* enable / disable interrupts */
  149. if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
  150. temp = KSZPHY_INTCS_ALL;
  151. else
  152. temp = 0;
  153. return phy_write(phydev, MII_KSZPHY_INTCS, temp);
  154. }
  155. static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
  156. {
  157. int ctrl;
  158. ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
  159. if (ctrl < 0)
  160. return ctrl;
  161. if (val)
  162. ctrl |= KSZPHY_RMII_REF_CLK_SEL;
  163. else
  164. ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
  165. return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
  166. }
  167. static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
  168. {
  169. int rc, temp, shift;
  170. switch (reg) {
  171. case MII_KSZPHY_CTRL_1:
  172. shift = 14;
  173. break;
  174. case MII_KSZPHY_CTRL_2:
  175. shift = 4;
  176. break;
  177. default:
  178. return -EINVAL;
  179. }
  180. temp = phy_read(phydev, reg);
  181. if (temp < 0) {
  182. rc = temp;
  183. goto out;
  184. }
  185. temp &= ~(3 << shift);
  186. temp |= val << shift;
  187. rc = phy_write(phydev, reg, temp);
  188. out:
  189. if (rc < 0)
  190. phydev_err(phydev, "failed to set led mode\n");
  191. return rc;
  192. }
  193. /* Disable PHY address 0 as the broadcast address, so that it can be used as a
  194. * unique (non-broadcast) address on a shared bus.
  195. */
  196. static int kszphy_broadcast_disable(struct phy_device *phydev)
  197. {
  198. int ret;
  199. ret = phy_read(phydev, MII_KSZPHY_OMSO);
  200. if (ret < 0)
  201. goto out;
  202. ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
  203. out:
  204. if (ret)
  205. phydev_err(phydev, "failed to disable broadcast address\n");
  206. return ret;
  207. }
  208. static int kszphy_nand_tree_disable(struct phy_device *phydev)
  209. {
  210. int ret;
  211. ret = phy_read(phydev, MII_KSZPHY_OMSO);
  212. if (ret < 0)
  213. goto out;
  214. if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
  215. return 0;
  216. ret = phy_write(phydev, MII_KSZPHY_OMSO,
  217. ret & ~KSZPHY_OMSO_NAND_TREE_ON);
  218. out:
  219. if (ret)
  220. phydev_err(phydev, "failed to disable NAND tree mode\n");
  221. return ret;
  222. }
  223. /* Some config bits need to be set again on resume, handle them here. */
  224. static int kszphy_config_reset(struct phy_device *phydev)
  225. {
  226. struct kszphy_priv *priv = phydev->priv;
  227. int ret;
  228. if (priv->rmii_ref_clk_sel) {
  229. ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
  230. if (ret) {
  231. phydev_err(phydev,
  232. "failed to set rmii reference clock\n");
  233. return ret;
  234. }
  235. }
  236. if (priv->led_mode >= 0)
  237. kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
  238. return 0;
  239. }
  240. static int kszphy_config_init(struct phy_device *phydev)
  241. {
  242. struct kszphy_priv *priv = phydev->priv;
  243. const struct kszphy_type *type;
  244. if (!priv)
  245. return 0;
  246. type = priv->type;
  247. if (type->has_broadcast_disable)
  248. kszphy_broadcast_disable(phydev);
  249. if (type->has_nand_tree_disable)
  250. kszphy_nand_tree_disable(phydev);
  251. return kszphy_config_reset(phydev);
  252. }
  253. static int ksz8041_fiber_mode(struct phy_device *phydev)
  254. {
  255. struct device_node *of_node = phydev->mdio.dev.of_node;
  256. return of_property_read_bool(of_node, "micrel,fiber-mode");
  257. }
  258. static int ksz8041_config_init(struct phy_device *phydev)
  259. {
  260. __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
  261. /* Limit supported and advertised modes in fiber mode */
  262. if (ksz8041_fiber_mode(phydev)) {
  263. phydev->dev_flags |= MICREL_PHY_FXEN;
  264. linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
  265. linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
  266. linkmode_and(phydev->supported, phydev->supported, mask);
  267. linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
  268. phydev->supported);
  269. linkmode_and(phydev->advertising, phydev->advertising, mask);
  270. linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
  271. phydev->advertising);
  272. phydev->autoneg = AUTONEG_DISABLE;
  273. }
  274. return kszphy_config_init(phydev);
  275. }
  276. static int ksz8041_config_aneg(struct phy_device *phydev)
  277. {
  278. /* Skip auto-negotiation in fiber mode */
  279. if (phydev->dev_flags & MICREL_PHY_FXEN) {
  280. phydev->speed = SPEED_100;
  281. return 0;
  282. }
  283. return genphy_config_aneg(phydev);
  284. }
  285. static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev,
  286. const bool ksz_8051)
  287. {
  288. int ret;
  289. if ((phydev->phy_id & MICREL_PHY_ID_MASK) != PHY_ID_KSZ8051)
  290. return 0;
  291. ret = phy_read(phydev, MII_BMSR);
  292. if (ret < 0)
  293. return ret;
  294. /* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same
  295. * exact PHY ID. However, they can be told apart by the extended
  296. * capability registers presence. The KSZ8051 PHY has them while
  297. * the switch does not.
  298. */
  299. ret &= BMSR_ERCAP;
  300. if (ksz_8051)
  301. return ret;
  302. else
  303. return !ret;
  304. }
  305. static int ksz8051_match_phy_device(struct phy_device *phydev)
  306. {
  307. return ksz8051_ksz8795_match_phy_device(phydev, true);
  308. }
  309. static int ksz8081_config_init(struct phy_device *phydev)
  310. {
  311. /* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line
  312. * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a
  313. * pull-down is missing, the factory test mode should be cleared by
  314. * manually writing a 0.
  315. */
  316. phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);
  317. return kszphy_config_init(phydev);
  318. }
  319. static int ksz8061_config_init(struct phy_device *phydev)
  320. {
  321. int ret;
  322. ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
  323. if (ret)
  324. return ret;
  325. return kszphy_config_init(phydev);
  326. }
  327. static int ksz8795_match_phy_device(struct phy_device *phydev)
  328. {
  329. return ksz8051_ksz8795_match_phy_device(phydev, false);
  330. }
  331. static int ksz9021_load_values_from_of(struct phy_device *phydev,
  332. const struct device_node *of_node,
  333. u16 reg,
  334. const char *field1, const char *field2,
  335. const char *field3, const char *field4)
  336. {
  337. int val1 = -1;
  338. int val2 = -2;
  339. int val3 = -3;
  340. int val4 = -4;
  341. int newval;
  342. int matches = 0;
  343. if (!of_property_read_u32(of_node, field1, &val1))
  344. matches++;
  345. if (!of_property_read_u32(of_node, field2, &val2))
  346. matches++;
  347. if (!of_property_read_u32(of_node, field3, &val3))
  348. matches++;
  349. if (!of_property_read_u32(of_node, field4, &val4))
  350. matches++;
  351. if (!matches)
  352. return 0;
  353. if (matches < 4)
  354. newval = kszphy_extended_read(phydev, reg);
  355. else
  356. newval = 0;
  357. if (val1 != -1)
  358. newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
  359. if (val2 != -2)
  360. newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
  361. if (val3 != -3)
  362. newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
  363. if (val4 != -4)
  364. newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
  365. return kszphy_extended_write(phydev, reg, newval);
  366. }
  367. static int ksz9021_config_init(struct phy_device *phydev)
  368. {
  369. const struct device *dev = &phydev->mdio.dev;
  370. const struct device_node *of_node = dev->of_node;
  371. const struct device *dev_walker;
  372. /* The Micrel driver has a deprecated option to place phy OF
  373. * properties in the MAC node. Walk up the tree of devices to
  374. * find a device with an OF node.
  375. */
  376. dev_walker = &phydev->mdio.dev;
  377. do {
  378. of_node = dev_walker->of_node;
  379. dev_walker = dev_walker->parent;
  380. } while (!of_node && dev_walker);
  381. if (of_node) {
  382. ksz9021_load_values_from_of(phydev, of_node,
  383. MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
  384. "txen-skew-ps", "txc-skew-ps",
  385. "rxdv-skew-ps", "rxc-skew-ps");
  386. ksz9021_load_values_from_of(phydev, of_node,
  387. MII_KSZPHY_RX_DATA_PAD_SKEW,
  388. "rxd0-skew-ps", "rxd1-skew-ps",
  389. "rxd2-skew-ps", "rxd3-skew-ps");
  390. ksz9021_load_values_from_of(phydev, of_node,
  391. MII_KSZPHY_TX_DATA_PAD_SKEW,
  392. "txd0-skew-ps", "txd1-skew-ps",
  393. "txd2-skew-ps", "txd3-skew-ps");
  394. }
  395. return 0;
  396. }
  397. #define KSZ9031_PS_TO_REG 60
  398. /* Extended registers */
  399. /* MMD Address 0x0 */
  400. #define MII_KSZ9031RN_FLP_BURST_TX_LO 3
  401. #define MII_KSZ9031RN_FLP_BURST_TX_HI 4
  402. /* MMD Address 0x2 */
  403. #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
  404. #define MII_KSZ9031RN_RX_CTL_M GENMASK(7, 4)
  405. #define MII_KSZ9031RN_TX_CTL_M GENMASK(3, 0)
  406. #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
  407. #define MII_KSZ9031RN_RXD3 GENMASK(15, 12)
  408. #define MII_KSZ9031RN_RXD2 GENMASK(11, 8)
  409. #define MII_KSZ9031RN_RXD1 GENMASK(7, 4)
  410. #define MII_KSZ9031RN_RXD0 GENMASK(3, 0)
  411. #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
  412. #define MII_KSZ9031RN_TXD3 GENMASK(15, 12)
  413. #define MII_KSZ9031RN_TXD2 GENMASK(11, 8)
  414. #define MII_KSZ9031RN_TXD1 GENMASK(7, 4)
  415. #define MII_KSZ9031RN_TXD0 GENMASK(3, 0)
  416. #define MII_KSZ9031RN_CLK_PAD_SKEW 8
  417. #define MII_KSZ9031RN_GTX_CLK GENMASK(9, 5)
  418. #define MII_KSZ9031RN_RX_CLK GENMASK(4, 0)
  419. /* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To
  420. * provide different RGMII options we need to configure delay offset
  421. * for each pad relative to build in delay.
  422. */
  423. /* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of
  424. * 1.80ns
  425. */
  426. #define RX_ID 0x7
  427. #define RX_CLK_ID 0x19
  428. /* set rx to +0.30ns and rx_clk to -0.90ns to compensate the
  429. * internal 1.2ns delay.
  430. */
  431. #define RX_ND 0xc
  432. #define RX_CLK_ND 0x0
  433. /* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */
  434. #define TX_ID 0x0
  435. #define TX_CLK_ID 0x1f
  436. /* set tx and tx_clk to "No delay adjustment" to keep 0ns
  437. * dealy
  438. */
  439. #define TX_ND 0x7
  440. #define TX_CLK_ND 0xf
  441. /* MMD Address 0x1C */
  442. #define MII_KSZ9031RN_EDPD 0x23
  443. #define MII_KSZ9031RN_EDPD_ENABLE BIT(0)
  444. static int ksz9031_of_load_skew_values(struct phy_device *phydev,
  445. const struct device_node *of_node,
  446. u16 reg, size_t field_sz,
  447. const char *field[], u8 numfields,
  448. bool *update)
  449. {
  450. int val[4] = {-1, -2, -3, -4};
  451. int matches = 0;
  452. u16 mask;
  453. u16 maxval;
  454. u16 newval;
  455. int i;
  456. for (i = 0; i < numfields; i++)
  457. if (!of_property_read_u32(of_node, field[i], val + i))
  458. matches++;
  459. if (!matches)
  460. return 0;
  461. *update |= true;
  462. if (matches < numfields)
  463. newval = phy_read_mmd(phydev, 2, reg);
  464. else
  465. newval = 0;
  466. maxval = (field_sz == 4) ? 0xf : 0x1f;
  467. for (i = 0; i < numfields; i++)
  468. if (val[i] != -(i + 1)) {
  469. mask = 0xffff;
  470. mask ^= maxval << (field_sz * i);
  471. newval = (newval & mask) |
  472. (((val[i] / KSZ9031_PS_TO_REG) & maxval)
  473. << (field_sz * i));
  474. }
  475. return phy_write_mmd(phydev, 2, reg, newval);
  476. }
  477. /* Center KSZ9031RNX FLP timing at 16ms. */
  478. static int ksz9031_center_flp_timing(struct phy_device *phydev)
  479. {
  480. int result;
  481. result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI,
  482. 0x0006);
  483. if (result)
  484. return result;
  485. result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO,
  486. 0x1A80);
  487. if (result)
  488. return result;
  489. return genphy_restart_aneg(phydev);
  490. }
  491. /* Enable energy-detect power-down mode */
  492. static int ksz9031_enable_edpd(struct phy_device *phydev)
  493. {
  494. int reg;
  495. reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD);
  496. if (reg < 0)
  497. return reg;
  498. return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD,
  499. reg | MII_KSZ9031RN_EDPD_ENABLE);
  500. }
  501. static int ksz9031_config_rgmii_delay(struct phy_device *phydev)
  502. {
  503. u16 rx, tx, rx_clk, tx_clk;
  504. int ret;
  505. switch (phydev->interface) {
  506. case PHY_INTERFACE_MODE_RGMII:
  507. tx = TX_ND;
  508. tx_clk = TX_CLK_ND;
  509. rx = RX_ND;
  510. rx_clk = RX_CLK_ND;
  511. break;
  512. case PHY_INTERFACE_MODE_RGMII_ID:
  513. tx = TX_ID;
  514. tx_clk = TX_CLK_ID;
  515. rx = RX_ID;
  516. rx_clk = RX_CLK_ID;
  517. break;
  518. case PHY_INTERFACE_MODE_RGMII_RXID:
  519. tx = TX_ND;
  520. tx_clk = TX_CLK_ND;
  521. rx = RX_ID;
  522. rx_clk = RX_CLK_ID;
  523. break;
  524. case PHY_INTERFACE_MODE_RGMII_TXID:
  525. tx = TX_ID;
  526. tx_clk = TX_CLK_ID;
  527. rx = RX_ND;
  528. rx_clk = RX_CLK_ND;
  529. break;
  530. default:
  531. return 0;
  532. }
  533. ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW,
  534. FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) |
  535. FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx));
  536. if (ret < 0)
  537. return ret;
  538. ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW,
  539. FIELD_PREP(MII_KSZ9031RN_RXD3, rx) |
  540. FIELD_PREP(MII_KSZ9031RN_RXD2, rx) |
  541. FIELD_PREP(MII_KSZ9031RN_RXD1, rx) |
  542. FIELD_PREP(MII_KSZ9031RN_RXD0, rx));
  543. if (ret < 0)
  544. return ret;
  545. ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW,
  546. FIELD_PREP(MII_KSZ9031RN_TXD3, tx) |
  547. FIELD_PREP(MII_KSZ9031RN_TXD2, tx) |
  548. FIELD_PREP(MII_KSZ9031RN_TXD1, tx) |
  549. FIELD_PREP(MII_KSZ9031RN_TXD0, tx));
  550. if (ret < 0)
  551. return ret;
  552. return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW,
  553. FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) |
  554. FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk));
  555. }
  556. static int ksz9031_config_init(struct phy_device *phydev)
  557. {
  558. const struct device *dev = &phydev->mdio.dev;
  559. const struct device_node *of_node = dev->of_node;
  560. static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
  561. static const char *rx_data_skews[4] = {
  562. "rxd0-skew-ps", "rxd1-skew-ps",
  563. "rxd2-skew-ps", "rxd3-skew-ps"
  564. };
  565. static const char *tx_data_skews[4] = {
  566. "txd0-skew-ps", "txd1-skew-ps",
  567. "txd2-skew-ps", "txd3-skew-ps"
  568. };
  569. static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
  570. const struct device *dev_walker;
  571. int result;
  572. result = ksz9031_enable_edpd(phydev);
  573. if (result < 0)
  574. return result;
  575. /* The Micrel driver has a deprecated option to place phy OF
  576. * properties in the MAC node. Walk up the tree of devices to
  577. * find a device with an OF node.
  578. */
  579. dev_walker = &phydev->mdio.dev;
  580. do {
  581. of_node = dev_walker->of_node;
  582. dev_walker = dev_walker->parent;
  583. } while (!of_node && dev_walker);
  584. if (of_node) {
  585. bool update = false;
  586. if (phy_interface_is_rgmii(phydev)) {
  587. result = ksz9031_config_rgmii_delay(phydev);
  588. if (result < 0)
  589. return result;
  590. }
  591. ksz9031_of_load_skew_values(phydev, of_node,
  592. MII_KSZ9031RN_CLK_PAD_SKEW, 5,
  593. clk_skews, 2, &update);
  594. ksz9031_of_load_skew_values(phydev, of_node,
  595. MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
  596. control_skews, 2, &update);
  597. ksz9031_of_load_skew_values(phydev, of_node,
  598. MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
  599. rx_data_skews, 4, &update);
  600. ksz9031_of_load_skew_values(phydev, of_node,
  601. MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
  602. tx_data_skews, 4, &update);
  603. if (update && !phy_interface_is_rgmii(phydev))
  604. phydev_warn(phydev,
  605. "*-skew-ps values should be used only with RGMII PHY modes\n");
  606. /* Silicon Errata Sheet (DS80000691D or DS80000692D):
  607. * When the device links in the 1000BASE-T slave mode only,
  608. * the optional 125MHz reference output clock (CLK125_NDO)
  609. * has wide duty cycle variation.
  610. *
  611. * The optional CLK125_NDO clock does not meet the RGMII
  612. * 45/55 percent (min/max) duty cycle requirement and therefore
  613. * cannot be used directly by the MAC side for clocking
  614. * applications that have setup/hold time requirements on
  615. * rising and falling clock edges.
  616. *
  617. * Workaround:
  618. * Force the phy to be the master to receive a stable clock
  619. * which meets the duty cycle requirement.
  620. */
  621. if (of_property_read_bool(of_node, "micrel,force-master")) {
  622. result = phy_read(phydev, MII_CTRL1000);
  623. if (result < 0)
  624. goto err_force_master;
  625. /* enable master mode, config & prefer master */
  626. result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
  627. result = phy_write(phydev, MII_CTRL1000, result);
  628. if (result < 0)
  629. goto err_force_master;
  630. }
  631. }
  632. return ksz9031_center_flp_timing(phydev);
  633. err_force_master:
  634. phydev_err(phydev, "failed to force the phy to master mode\n");
  635. return result;
  636. }
  637. #define KSZ9131_SKEW_5BIT_MAX 2400
  638. #define KSZ9131_SKEW_4BIT_MAX 800
  639. #define KSZ9131_OFFSET 700
  640. #define KSZ9131_STEP 100
  641. static int ksz9131_of_load_skew_values(struct phy_device *phydev,
  642. struct device_node *of_node,
  643. u16 reg, size_t field_sz,
  644. char *field[], u8 numfields)
  645. {
  646. int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
  647. -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};
  648. int skewval, skewmax = 0;
  649. int matches = 0;
  650. u16 maxval;
  651. u16 newval;
  652. u16 mask;
  653. int i;
  654. /* psec properties in dts should mean x pico seconds */
  655. if (field_sz == 5)
  656. skewmax = KSZ9131_SKEW_5BIT_MAX;
  657. else
  658. skewmax = KSZ9131_SKEW_4BIT_MAX;
  659. for (i = 0; i < numfields; i++)
  660. if (!of_property_read_s32(of_node, field[i], &skewval)) {
  661. if (skewval < -KSZ9131_OFFSET)
  662. skewval = -KSZ9131_OFFSET;
  663. else if (skewval > skewmax)
  664. skewval = skewmax;
  665. val[i] = skewval + KSZ9131_OFFSET;
  666. matches++;
  667. }
  668. if (!matches)
  669. return 0;
  670. if (matches < numfields)
  671. newval = phy_read_mmd(phydev, 2, reg);
  672. else
  673. newval = 0;
  674. maxval = (field_sz == 4) ? 0xf : 0x1f;
  675. for (i = 0; i < numfields; i++)
  676. if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
  677. mask = 0xffff;
  678. mask ^= maxval << (field_sz * i);
  679. newval = (newval & mask) |
  680. (((val[i] / KSZ9131_STEP) & maxval)
  681. << (field_sz * i));
  682. }
  683. return phy_write_mmd(phydev, 2, reg, newval);
  684. }
  685. #define KSZ9131RN_MMD_COMMON_CTRL_REG 2
  686. #define KSZ9131RN_RXC_DLL_CTRL 76
  687. #define KSZ9131RN_TXC_DLL_CTRL 77
  688. #define KSZ9131RN_DLL_CTRL_BYPASS BIT_MASK(12)
  689. #define KSZ9131RN_DLL_ENABLE_DELAY 0
  690. #define KSZ9131RN_DLL_DISABLE_DELAY BIT(12)
  691. static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
  692. {
  693. u16 rxcdll_val, txcdll_val;
  694. int ret;
  695. switch (phydev->interface) {
  696. case PHY_INTERFACE_MODE_RGMII:
  697. rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
  698. txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
  699. break;
  700. case PHY_INTERFACE_MODE_RGMII_ID:
  701. rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
  702. txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
  703. break;
  704. case PHY_INTERFACE_MODE_RGMII_RXID:
  705. rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
  706. txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
  707. break;
  708. case PHY_INTERFACE_MODE_RGMII_TXID:
  709. rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
  710. txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
  711. break;
  712. default:
  713. return 0;
  714. }
  715. ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
  716. KSZ9131RN_RXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
  717. rxcdll_val);
  718. if (ret < 0)
  719. return ret;
  720. return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
  721. KSZ9131RN_TXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
  722. txcdll_val);
  723. }
  724. static int ksz9131_config_init(struct phy_device *phydev)
  725. {
  726. const struct device *dev = &phydev->mdio.dev;
  727. struct device_node *of_node = dev->of_node;
  728. char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};
  729. char *rx_data_skews[4] = {
  730. "rxd0-skew-psec", "rxd1-skew-psec",
  731. "rxd2-skew-psec", "rxd3-skew-psec"
  732. };
  733. char *tx_data_skews[4] = {
  734. "txd0-skew-psec", "txd1-skew-psec",
  735. "txd2-skew-psec", "txd3-skew-psec"
  736. };
  737. char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};
  738. const struct device *dev_walker;
  739. int ret;
  740. dev_walker = &phydev->mdio.dev;
  741. do {
  742. of_node = dev_walker->of_node;
  743. dev_walker = dev_walker->parent;
  744. } while (!of_node && dev_walker);
  745. if (!of_node)
  746. return 0;
  747. if (phy_interface_is_rgmii(phydev)) {
  748. ret = ksz9131_config_rgmii_delay(phydev);
  749. if (ret < 0)
  750. return ret;
  751. }
  752. ret = ksz9131_of_load_skew_values(phydev, of_node,
  753. MII_KSZ9031RN_CLK_PAD_SKEW, 5,
  754. clk_skews, 2);
  755. if (ret < 0)
  756. return ret;
  757. ret = ksz9131_of_load_skew_values(phydev, of_node,
  758. MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
  759. control_skews, 2);
  760. if (ret < 0)
  761. return ret;
  762. ret = ksz9131_of_load_skew_values(phydev, of_node,
  763. MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
  764. rx_data_skews, 4);
  765. if (ret < 0)
  766. return ret;
  767. ret = ksz9131_of_load_skew_values(phydev, of_node,
  768. MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
  769. tx_data_skews, 4);
  770. if (ret < 0)
  771. return ret;
  772. return 0;
  773. }
  774. #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
  775. #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
  776. #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
  777. static int ksz8873mll_read_status(struct phy_device *phydev)
  778. {
  779. int regval;
  780. /* dummy read */
  781. regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
  782. regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
  783. if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
  784. phydev->duplex = DUPLEX_HALF;
  785. else
  786. phydev->duplex = DUPLEX_FULL;
  787. if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
  788. phydev->speed = SPEED_10;
  789. else
  790. phydev->speed = SPEED_100;
  791. phydev->link = 1;
  792. phydev->pause = phydev->asym_pause = 0;
  793. return 0;
  794. }
  795. static int ksz9031_get_features(struct phy_device *phydev)
  796. {
  797. int ret;
  798. ret = genphy_read_abilities(phydev);
  799. if (ret < 0)
  800. return ret;
  801. /* Silicon Errata Sheet (DS80000691D or DS80000692D):
  802. * Whenever the device's Asymmetric Pause capability is set to 1,
  803. * link-up may fail after a link-up to link-down transition.
  804. *
  805. * The Errata Sheet is for ksz9031, but ksz9021 has the same issue
  806. *
  807. * Workaround:
  808. * Do not enable the Asymmetric Pause capability bit.
  809. */
  810. linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
  811. /* We force setting the Pause capability as the core will force the
  812. * Asymmetric Pause capability to 1 otherwise.
  813. */
  814. linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
  815. return 0;
  816. }
  817. static int ksz9031_read_status(struct phy_device *phydev)
  818. {
  819. int err;
  820. int regval;
  821. err = genphy_read_status(phydev);
  822. if (err)
  823. return err;
  824. /* Make sure the PHY is not broken. Read idle error count,
  825. * and reset the PHY if it is maxed out.
  826. */
  827. regval = phy_read(phydev, MII_STAT1000);
  828. if ((regval & 0xFF) == 0xFF) {
  829. phy_init_hw(phydev);
  830. phydev->link = 0;
  831. if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
  832. phydev->drv->config_intr(phydev);
  833. return genphy_config_aneg(phydev);
  834. }
  835. return 0;
  836. }
  837. static int ksz8873mll_config_aneg(struct phy_device *phydev)
  838. {
  839. return 0;
  840. }
  841. static int kszphy_get_sset_count(struct phy_device *phydev)
  842. {
  843. return ARRAY_SIZE(kszphy_hw_stats);
  844. }
  845. static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
  846. {
  847. int i;
  848. for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
  849. strlcpy(data + i * ETH_GSTRING_LEN,
  850. kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
  851. }
  852. }
  853. static u64 kszphy_get_stat(struct phy_device *phydev, int i)
  854. {
  855. struct kszphy_hw_stat stat = kszphy_hw_stats[i];
  856. struct kszphy_priv *priv = phydev->priv;
  857. int val;
  858. u64 ret;
  859. val = phy_read(phydev, stat.reg);
  860. if (val < 0) {
  861. ret = U64_MAX;
  862. } else {
  863. val = val & ((1 << stat.bits) - 1);
  864. priv->stats[i] += val;
  865. ret = priv->stats[i];
  866. }
  867. return ret;
  868. }
  869. static void kszphy_get_stats(struct phy_device *phydev,
  870. struct ethtool_stats *stats, u64 *data)
  871. {
  872. int i;
  873. for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
  874. data[i] = kszphy_get_stat(phydev, i);
  875. }
  876. static int kszphy_suspend(struct phy_device *phydev)
  877. {
  878. /* Disable PHY Interrupts */
  879. if (phy_interrupt_is_valid(phydev)) {
  880. phydev->interrupts = PHY_INTERRUPT_DISABLED;
  881. if (phydev->drv->config_intr)
  882. phydev->drv->config_intr(phydev);
  883. }
  884. return genphy_suspend(phydev);
  885. }
  886. static int kszphy_resume(struct phy_device *phydev)
  887. {
  888. int ret;
  889. genphy_resume(phydev);
  890. /* After switching from power-down to normal mode, an internal global
  891. * reset is automatically generated. Wait a minimum of 1 ms before
  892. * read/write access to the PHY registers.
  893. */
  894. usleep_range(1000, 2000);
  895. ret = kszphy_config_reset(phydev);
  896. if (ret)
  897. return ret;
  898. /* Enable PHY Interrupts */
  899. if (phy_interrupt_is_valid(phydev)) {
  900. phydev->interrupts = PHY_INTERRUPT_ENABLED;
  901. if (phydev->drv->config_intr)
  902. phydev->drv->config_intr(phydev);
  903. }
  904. return 0;
  905. }
  906. static int kszphy_probe(struct phy_device *phydev)
  907. {
  908. const struct kszphy_type *type = phydev->drv->driver_data;
  909. const struct device_node *np = phydev->mdio.dev.of_node;
  910. struct kszphy_priv *priv;
  911. struct clk *clk;
  912. int ret;
  913. priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
  914. if (!priv)
  915. return -ENOMEM;
  916. phydev->priv = priv;
  917. priv->type = type;
  918. if (type->led_mode_reg) {
  919. ret = of_property_read_u32(np, "micrel,led-mode",
  920. &priv->led_mode);
  921. if (ret)
  922. priv->led_mode = -1;
  923. if (priv->led_mode > 3) {
  924. phydev_err(phydev, "invalid led mode: 0x%02x\n",
  925. priv->led_mode);
  926. priv->led_mode = -1;
  927. }
  928. } else {
  929. priv->led_mode = -1;
  930. }
  931. clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
  932. /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
  933. if (!IS_ERR_OR_NULL(clk)) {
  934. unsigned long rate = clk_get_rate(clk);
  935. bool rmii_ref_clk_sel_25_mhz;
  936. priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
  937. rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
  938. "micrel,rmii-reference-clock-select-25-mhz");
  939. if (rate > 24500000 && rate < 25500000) {
  940. priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
  941. } else if (rate > 49500000 && rate < 50500000) {
  942. priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
  943. } else {
  944. phydev_err(phydev, "Clock rate out of range: %ld\n",
  945. rate);
  946. return -EINVAL;
  947. }
  948. }
  949. if (ksz8041_fiber_mode(phydev))
  950. phydev->port = PORT_FIBRE;
  951. /* Support legacy board-file configuration */
  952. if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
  953. priv->rmii_ref_clk_sel = true;
  954. priv->rmii_ref_clk_sel_val = true;
  955. }
  956. return 0;
  957. }
  958. static struct phy_driver ksphy_driver[] = {
  959. {
  960. .phy_id = PHY_ID_KS8737,
  961. .phy_id_mask = MICREL_PHY_ID_MASK,
  962. .name = "Micrel KS8737",
  963. /* PHY_BASIC_FEATURES */
  964. .driver_data = &ks8737_type,
  965. .config_init = kszphy_config_init,
  966. .ack_interrupt = kszphy_ack_interrupt,
  967. .config_intr = kszphy_config_intr,
  968. .suspend = genphy_suspend,
  969. .resume = genphy_resume,
  970. }, {
  971. .phy_id = PHY_ID_KSZ8021,
  972. .phy_id_mask = 0x00ffffff,
  973. .name = "Micrel KSZ8021 or KSZ8031",
  974. /* PHY_BASIC_FEATURES */
  975. .driver_data = &ksz8021_type,
  976. .probe = kszphy_probe,
  977. .config_init = kszphy_config_init,
  978. .ack_interrupt = kszphy_ack_interrupt,
  979. .config_intr = kszphy_config_intr,
  980. .get_sset_count = kszphy_get_sset_count,
  981. .get_strings = kszphy_get_strings,
  982. .get_stats = kszphy_get_stats,
  983. .suspend = genphy_suspend,
  984. .resume = genphy_resume,
  985. }, {
  986. .phy_id = PHY_ID_KSZ8031,
  987. .phy_id_mask = 0x00ffffff,
  988. .name = "Micrel KSZ8031",
  989. /* PHY_BASIC_FEATURES */
  990. .driver_data = &ksz8021_type,
  991. .probe = kszphy_probe,
  992. .config_init = kszphy_config_init,
  993. .ack_interrupt = kszphy_ack_interrupt,
  994. .config_intr = kszphy_config_intr,
  995. .get_sset_count = kszphy_get_sset_count,
  996. .get_strings = kszphy_get_strings,
  997. .get_stats = kszphy_get_stats,
  998. .suspend = genphy_suspend,
  999. .resume = genphy_resume,
  1000. }, {
  1001. .phy_id = PHY_ID_KSZ8041,
  1002. .phy_id_mask = MICREL_PHY_ID_MASK,
  1003. .name = "Micrel KSZ8041",
  1004. /* PHY_BASIC_FEATURES */
  1005. .driver_data = &ksz8041_type,
  1006. .probe = kszphy_probe,
  1007. .config_init = ksz8041_config_init,
  1008. .config_aneg = ksz8041_config_aneg,
  1009. .ack_interrupt = kszphy_ack_interrupt,
  1010. .config_intr = kszphy_config_intr,
  1011. .get_sset_count = kszphy_get_sset_count,
  1012. .get_strings = kszphy_get_strings,
  1013. .get_stats = kszphy_get_stats,
  1014. /* No suspend/resume callbacks because of errata DS80000700A,
  1015. * receiver error following software power down.
  1016. */
  1017. }, {
  1018. .phy_id = PHY_ID_KSZ8041RNLI,
  1019. .phy_id_mask = MICREL_PHY_ID_MASK,
  1020. .name = "Micrel KSZ8041RNLI",
  1021. /* PHY_BASIC_FEATURES */
  1022. .driver_data = &ksz8041_type,
  1023. .probe = kszphy_probe,
  1024. .config_init = kszphy_config_init,
  1025. .ack_interrupt = kszphy_ack_interrupt,
  1026. .config_intr = kszphy_config_intr,
  1027. .get_sset_count = kszphy_get_sset_count,
  1028. .get_strings = kszphy_get_strings,
  1029. .get_stats = kszphy_get_stats,
  1030. .suspend = genphy_suspend,
  1031. .resume = genphy_resume,
  1032. }, {
  1033. .name = "Micrel KSZ8051",
  1034. /* PHY_BASIC_FEATURES */
  1035. .driver_data = &ksz8051_type,
  1036. .probe = kszphy_probe,
  1037. .config_init = kszphy_config_init,
  1038. .ack_interrupt = kszphy_ack_interrupt,
  1039. .config_intr = kszphy_config_intr,
  1040. .get_sset_count = kszphy_get_sset_count,
  1041. .get_strings = kszphy_get_strings,
  1042. .get_stats = kszphy_get_stats,
  1043. .match_phy_device = ksz8051_match_phy_device,
  1044. .suspend = genphy_suspend,
  1045. .resume = genphy_resume,
  1046. }, {
  1047. .phy_id = PHY_ID_KSZ8001,
  1048. .name = "Micrel KSZ8001 or KS8721",
  1049. .phy_id_mask = 0x00fffffc,
  1050. /* PHY_BASIC_FEATURES */
  1051. .driver_data = &ksz8041_type,
  1052. .probe = kszphy_probe,
  1053. .config_init = kszphy_config_init,
  1054. .ack_interrupt = kszphy_ack_interrupt,
  1055. .config_intr = kszphy_config_intr,
  1056. .get_sset_count = kszphy_get_sset_count,
  1057. .get_strings = kszphy_get_strings,
  1058. .get_stats = kszphy_get_stats,
  1059. .suspend = genphy_suspend,
  1060. .resume = genphy_resume,
  1061. }, {
  1062. .phy_id = PHY_ID_KSZ8081,
  1063. .name = "Micrel KSZ8081 or KSZ8091",
  1064. .phy_id_mask = MICREL_PHY_ID_MASK,
  1065. /* PHY_BASIC_FEATURES */
  1066. .driver_data = &ksz8081_type,
  1067. .probe = kszphy_probe,
  1068. .config_init = ksz8081_config_init,
  1069. .ack_interrupt = kszphy_ack_interrupt,
  1070. .soft_reset = genphy_soft_reset,
  1071. .config_intr = kszphy_config_intr,
  1072. .get_sset_count = kszphy_get_sset_count,
  1073. .get_strings = kszphy_get_strings,
  1074. .get_stats = kszphy_get_stats,
  1075. .suspend = kszphy_suspend,
  1076. .resume = kszphy_resume,
  1077. }, {
  1078. .phy_id = PHY_ID_KSZ8061,
  1079. .name = "Micrel KSZ8061",
  1080. .phy_id_mask = MICREL_PHY_ID_MASK,
  1081. /* PHY_BASIC_FEATURES */
  1082. .config_init = ksz8061_config_init,
  1083. .ack_interrupt = kszphy_ack_interrupt,
  1084. .config_intr = kszphy_config_intr,
  1085. .suspend = genphy_suspend,
  1086. .resume = genphy_resume,
  1087. }, {
  1088. .phy_id = PHY_ID_KSZ9021,
  1089. .phy_id_mask = 0x000ffffe,
  1090. .name = "Micrel KSZ9021 Gigabit PHY",
  1091. /* PHY_GBIT_FEATURES */
  1092. .driver_data = &ksz9021_type,
  1093. .probe = kszphy_probe,
  1094. .get_features = ksz9031_get_features,
  1095. .config_init = ksz9021_config_init,
  1096. .ack_interrupt = kszphy_ack_interrupt,
  1097. .config_intr = kszphy_config_intr,
  1098. .get_sset_count = kszphy_get_sset_count,
  1099. .get_strings = kszphy_get_strings,
  1100. .get_stats = kszphy_get_stats,
  1101. .suspend = genphy_suspend,
  1102. .resume = genphy_resume,
  1103. .read_mmd = genphy_read_mmd_unsupported,
  1104. .write_mmd = genphy_write_mmd_unsupported,
  1105. }, {
  1106. .phy_id = PHY_ID_KSZ9031,
  1107. .phy_id_mask = MICREL_PHY_ID_MASK,
  1108. .name = "Micrel KSZ9031 Gigabit PHY",
  1109. .driver_data = &ksz9021_type,
  1110. .probe = kszphy_probe,
  1111. .get_features = ksz9031_get_features,
  1112. .config_init = ksz9031_config_init,
  1113. .soft_reset = genphy_soft_reset,
  1114. .read_status = ksz9031_read_status,
  1115. .ack_interrupt = kszphy_ack_interrupt,
  1116. .config_intr = kszphy_config_intr,
  1117. .get_sset_count = kszphy_get_sset_count,
  1118. .get_strings = kszphy_get_strings,
  1119. .get_stats = kszphy_get_stats,
  1120. .suspend = genphy_suspend,
  1121. .resume = kszphy_resume,
  1122. }, {
  1123. .phy_id = PHY_ID_LAN8814,
  1124. .phy_id_mask = MICREL_PHY_ID_MASK,
  1125. .name = "Microchip INDY Gigabit Quad PHY",
  1126. .driver_data = &ksz9021_type,
  1127. .probe = kszphy_probe,
  1128. .soft_reset = genphy_soft_reset,
  1129. .read_status = ksz9031_read_status,
  1130. .get_sset_count = kszphy_get_sset_count,
  1131. .get_strings = kszphy_get_strings,
  1132. .get_stats = kszphy_get_stats,
  1133. .suspend = genphy_suspend,
  1134. .resume = kszphy_resume,
  1135. }, {
  1136. .phy_id = PHY_ID_KSZ9131,
  1137. .phy_id_mask = MICREL_PHY_ID_MASK,
  1138. .name = "Microchip KSZ9131 Gigabit PHY",
  1139. /* PHY_GBIT_FEATURES */
  1140. .driver_data = &ksz9021_type,
  1141. .probe = kszphy_probe,
  1142. .config_init = ksz9131_config_init,
  1143. .read_status = genphy_read_status,
  1144. .ack_interrupt = kszphy_ack_interrupt,
  1145. .config_intr = kszphy_config_intr,
  1146. .get_sset_count = kszphy_get_sset_count,
  1147. .get_strings = kszphy_get_strings,
  1148. .get_stats = kszphy_get_stats,
  1149. .suspend = genphy_suspend,
  1150. .resume = kszphy_resume,
  1151. }, {
  1152. .phy_id = PHY_ID_KSZ8873MLL,
  1153. .phy_id_mask = MICREL_PHY_ID_MASK,
  1154. .name = "Micrel KSZ8873MLL Switch",
  1155. /* PHY_BASIC_FEATURES */
  1156. .config_init = kszphy_config_init,
  1157. .config_aneg = ksz8873mll_config_aneg,
  1158. .read_status = ksz8873mll_read_status,
  1159. .suspend = genphy_suspend,
  1160. .resume = genphy_resume,
  1161. }, {
  1162. .phy_id = PHY_ID_KSZ886X,
  1163. .phy_id_mask = MICREL_PHY_ID_MASK,
  1164. .name = "Micrel KSZ886X Switch",
  1165. /* PHY_BASIC_FEATURES */
  1166. .config_init = kszphy_config_init,
  1167. .suspend = genphy_suspend,
  1168. .resume = genphy_resume,
  1169. }, {
  1170. .name = "Micrel KSZ87XX Switch",
  1171. /* PHY_BASIC_FEATURES */
  1172. .config_init = kszphy_config_init,
  1173. .match_phy_device = ksz8795_match_phy_device,
  1174. .suspend = genphy_suspend,
  1175. .resume = genphy_resume,
  1176. }, {
  1177. .phy_id = PHY_ID_KSZ9477,
  1178. .phy_id_mask = MICREL_PHY_ID_MASK,
  1179. .name = "Microchip KSZ9477",
  1180. /* PHY_GBIT_FEATURES */
  1181. .config_init = kszphy_config_init,
  1182. .suspend = genphy_suspend,
  1183. .resume = genphy_resume,
  1184. } };
  1185. module_phy_driver(ksphy_driver);
  1186. MODULE_DESCRIPTION("Micrel PHY driver");
  1187. MODULE_AUTHOR("David J. Choi");
  1188. MODULE_LICENSE("GPL");
  1189. static struct mdio_device_id __maybe_unused micrel_tbl[] = {
  1190. { PHY_ID_KSZ9021, 0x000ffffe },
  1191. { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
  1192. { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK },
  1193. { PHY_ID_KSZ8001, 0x00fffffc },
  1194. { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
  1195. { PHY_ID_KSZ8021, 0x00ffffff },
  1196. { PHY_ID_KSZ8031, 0x00ffffff },
  1197. { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
  1198. { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
  1199. { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
  1200. { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
  1201. { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
  1202. { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
  1203. { PHY_ID_LAN8814, MICREL_PHY_ID_MASK },
  1204. { }
  1205. };
  1206. MODULE_DEVICE_TABLE(mdio, micrel_tbl);