dp83tc811.c 9.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for the Texas Instruments DP83TC811 PHY
  4. *
  5. * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
  6. *
  7. */
  8. #include <linux/ethtool.h>
  9. #include <linux/etherdevice.h>
  10. #include <linux/kernel.h>
  11. #include <linux/mii.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/phy.h>
  15. #include <linux/netdevice.h>
  16. #define DP83TC811_PHY_ID 0x2000a253
  17. #define DP83811_DEVADDR 0x1f
  18. #define MII_DP83811_SGMII_CTRL 0x09
  19. #define MII_DP83811_INT_STAT1 0x12
  20. #define MII_DP83811_INT_STAT2 0x13
  21. #define MII_DP83811_INT_STAT3 0x18
  22. #define MII_DP83811_RESET_CTRL 0x1f
  23. #define DP83811_HW_RESET BIT(15)
  24. #define DP83811_SW_RESET BIT(14)
  25. /* INT_STAT1 bits */
  26. #define DP83811_RX_ERR_HF_INT_EN BIT(0)
  27. #define DP83811_MS_TRAINING_INT_EN BIT(1)
  28. #define DP83811_ANEG_COMPLETE_INT_EN BIT(2)
  29. #define DP83811_ESD_EVENT_INT_EN BIT(3)
  30. #define DP83811_WOL_INT_EN BIT(4)
  31. #define DP83811_LINK_STAT_INT_EN BIT(5)
  32. #define DP83811_ENERGY_DET_INT_EN BIT(6)
  33. #define DP83811_LINK_QUAL_INT_EN BIT(7)
  34. /* INT_STAT2 bits */
  35. #define DP83811_JABBER_DET_INT_EN BIT(0)
  36. #define DP83811_POLARITY_INT_EN BIT(1)
  37. #define DP83811_SLEEP_MODE_INT_EN BIT(2)
  38. #define DP83811_OVERTEMP_INT_EN BIT(3)
  39. #define DP83811_OVERVOLTAGE_INT_EN BIT(6)
  40. #define DP83811_UNDERVOLTAGE_INT_EN BIT(7)
  41. /* INT_STAT3 bits */
  42. #define DP83811_LPS_INT_EN BIT(0)
  43. #define DP83811_NO_FRAME_INT_EN BIT(3)
  44. #define DP83811_POR_DONE_INT_EN BIT(4)
  45. #define MII_DP83811_RXSOP1 0x04a5
  46. #define MII_DP83811_RXSOP2 0x04a6
  47. #define MII_DP83811_RXSOP3 0x04a7
  48. /* WoL Registers */
  49. #define MII_DP83811_WOL_CFG 0x04a0
  50. #define MII_DP83811_WOL_STAT 0x04a1
  51. #define MII_DP83811_WOL_DA1 0x04a2
  52. #define MII_DP83811_WOL_DA2 0x04a3
  53. #define MII_DP83811_WOL_DA3 0x04a4
  54. /* WoL bits */
  55. #define DP83811_WOL_MAGIC_EN BIT(0)
  56. #define DP83811_WOL_SECURE_ON BIT(5)
  57. #define DP83811_WOL_EN BIT(7)
  58. #define DP83811_WOL_INDICATION_SEL BIT(8)
  59. #define DP83811_WOL_CLR_INDICATION BIT(11)
  60. /* SGMII CTRL bits */
  61. #define DP83811_TDR_AUTO BIT(8)
  62. #define DP83811_SGMII_EN BIT(12)
  63. #define DP83811_SGMII_AUTO_NEG_EN BIT(13)
  64. #define DP83811_SGMII_TX_ERR_DIS BIT(14)
  65. #define DP83811_SGMII_SOFT_RESET BIT(15)
  66. static int dp83811_ack_interrupt(struct phy_device *phydev)
  67. {
  68. int err;
  69. err = phy_read(phydev, MII_DP83811_INT_STAT1);
  70. if (err < 0)
  71. return err;
  72. err = phy_read(phydev, MII_DP83811_INT_STAT2);
  73. if (err < 0)
  74. return err;
  75. err = phy_read(phydev, MII_DP83811_INT_STAT3);
  76. if (err < 0)
  77. return err;
  78. return 0;
  79. }
  80. static int dp83811_set_wol(struct phy_device *phydev,
  81. struct ethtool_wolinfo *wol)
  82. {
  83. struct net_device *ndev = phydev->attached_dev;
  84. const u8 *mac;
  85. u16 value;
  86. if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) {
  87. mac = (const u8 *)ndev->dev_addr;
  88. if (!is_valid_ether_addr(mac))
  89. return -EINVAL;
  90. /* MAC addresses start with byte 5, but stored in mac[0].
  91. * 811 PHYs store bytes 4|5, 2|3, 0|1
  92. */
  93. phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA1,
  94. (mac[1] << 8) | mac[0]);
  95. phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA2,
  96. (mac[3] << 8) | mac[2]);
  97. phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA3,
  98. (mac[5] << 8) | mac[4]);
  99. value = phy_read_mmd(phydev, DP83811_DEVADDR,
  100. MII_DP83811_WOL_CFG);
  101. if (wol->wolopts & WAKE_MAGIC)
  102. value |= DP83811_WOL_MAGIC_EN;
  103. else
  104. value &= ~DP83811_WOL_MAGIC_EN;
  105. if (wol->wolopts & WAKE_MAGICSECURE) {
  106. phy_write_mmd(phydev, DP83811_DEVADDR,
  107. MII_DP83811_RXSOP1,
  108. (wol->sopass[1] << 8) | wol->sopass[0]);
  109. phy_write_mmd(phydev, DP83811_DEVADDR,
  110. MII_DP83811_RXSOP2,
  111. (wol->sopass[3] << 8) | wol->sopass[2]);
  112. phy_write_mmd(phydev, DP83811_DEVADDR,
  113. MII_DP83811_RXSOP3,
  114. (wol->sopass[5] << 8) | wol->sopass[4]);
  115. value |= DP83811_WOL_SECURE_ON;
  116. } else {
  117. value &= ~DP83811_WOL_SECURE_ON;
  118. }
  119. /* Clear any pending WoL interrupt */
  120. phy_read(phydev, MII_DP83811_INT_STAT1);
  121. value |= DP83811_WOL_EN | DP83811_WOL_INDICATION_SEL |
  122. DP83811_WOL_CLR_INDICATION;
  123. return phy_write_mmd(phydev, DP83811_DEVADDR,
  124. MII_DP83811_WOL_CFG, value);
  125. } else {
  126. return phy_clear_bits_mmd(phydev, DP83811_DEVADDR,
  127. MII_DP83811_WOL_CFG, DP83811_WOL_EN);
  128. }
  129. }
  130. static void dp83811_get_wol(struct phy_device *phydev,
  131. struct ethtool_wolinfo *wol)
  132. {
  133. u16 sopass_val;
  134. int value;
  135. wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE);
  136. wol->wolopts = 0;
  137. value = phy_read_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG);
  138. if (value & DP83811_WOL_MAGIC_EN)
  139. wol->wolopts |= WAKE_MAGIC;
  140. if (value & DP83811_WOL_SECURE_ON) {
  141. sopass_val = phy_read_mmd(phydev, DP83811_DEVADDR,
  142. MII_DP83811_RXSOP1);
  143. wol->sopass[0] = (sopass_val & 0xff);
  144. wol->sopass[1] = (sopass_val >> 8);
  145. sopass_val = phy_read_mmd(phydev, DP83811_DEVADDR,
  146. MII_DP83811_RXSOP2);
  147. wol->sopass[2] = (sopass_val & 0xff);
  148. wol->sopass[3] = (sopass_val >> 8);
  149. sopass_val = phy_read_mmd(phydev, DP83811_DEVADDR,
  150. MII_DP83811_RXSOP3);
  151. wol->sopass[4] = (sopass_val & 0xff);
  152. wol->sopass[5] = (sopass_val >> 8);
  153. wol->wolopts |= WAKE_MAGICSECURE;
  154. }
  155. /* WoL is not enabled so set wolopts to 0 */
  156. if (!(value & DP83811_WOL_EN))
  157. wol->wolopts = 0;
  158. }
  159. static int dp83811_config_intr(struct phy_device *phydev)
  160. {
  161. int misr_status, err;
  162. if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
  163. misr_status = phy_read(phydev, MII_DP83811_INT_STAT1);
  164. if (misr_status < 0)
  165. return misr_status;
  166. misr_status |= (DP83811_RX_ERR_HF_INT_EN |
  167. DP83811_MS_TRAINING_INT_EN |
  168. DP83811_ANEG_COMPLETE_INT_EN |
  169. DP83811_ESD_EVENT_INT_EN |
  170. DP83811_WOL_INT_EN |
  171. DP83811_LINK_STAT_INT_EN |
  172. DP83811_ENERGY_DET_INT_EN |
  173. DP83811_LINK_QUAL_INT_EN);
  174. err = phy_write(phydev, MII_DP83811_INT_STAT1, misr_status);
  175. if (err < 0)
  176. return err;
  177. misr_status = phy_read(phydev, MII_DP83811_INT_STAT2);
  178. if (misr_status < 0)
  179. return misr_status;
  180. misr_status |= (DP83811_JABBER_DET_INT_EN |
  181. DP83811_POLARITY_INT_EN |
  182. DP83811_SLEEP_MODE_INT_EN |
  183. DP83811_OVERTEMP_INT_EN |
  184. DP83811_OVERVOLTAGE_INT_EN |
  185. DP83811_UNDERVOLTAGE_INT_EN);
  186. err = phy_write(phydev, MII_DP83811_INT_STAT2, misr_status);
  187. if (err < 0)
  188. return err;
  189. misr_status = phy_read(phydev, MII_DP83811_INT_STAT3);
  190. if (misr_status < 0)
  191. return misr_status;
  192. misr_status |= (DP83811_LPS_INT_EN |
  193. DP83811_NO_FRAME_INT_EN |
  194. DP83811_POR_DONE_INT_EN);
  195. err = phy_write(phydev, MII_DP83811_INT_STAT3, misr_status);
  196. } else {
  197. err = phy_write(phydev, MII_DP83811_INT_STAT1, 0);
  198. if (err < 0)
  199. return err;
  200. err = phy_write(phydev, MII_DP83811_INT_STAT2, 0);
  201. if (err < 0)
  202. return err;
  203. err = phy_write(phydev, MII_DP83811_INT_STAT3, 0);
  204. }
  205. return err;
  206. }
  207. static int dp83811_config_aneg(struct phy_device *phydev)
  208. {
  209. int value, err;
  210. if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
  211. value = phy_read(phydev, MII_DP83811_SGMII_CTRL);
  212. if (phydev->autoneg == AUTONEG_ENABLE) {
  213. err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
  214. (DP83811_SGMII_AUTO_NEG_EN | value));
  215. if (err < 0)
  216. return err;
  217. } else {
  218. err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
  219. (~DP83811_SGMII_AUTO_NEG_EN & value));
  220. if (err < 0)
  221. return err;
  222. }
  223. }
  224. return genphy_config_aneg(phydev);
  225. }
  226. static int dp83811_config_init(struct phy_device *phydev)
  227. {
  228. int value, err;
  229. value = phy_read(phydev, MII_DP83811_SGMII_CTRL);
  230. if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
  231. err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
  232. (DP83811_SGMII_EN | value));
  233. } else {
  234. err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
  235. (~DP83811_SGMII_EN & value));
  236. }
  237. if (err < 0)
  238. return err;
  239. value = DP83811_WOL_MAGIC_EN | DP83811_WOL_SECURE_ON | DP83811_WOL_EN;
  240. return phy_clear_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
  241. value);
  242. }
  243. static int dp83811_phy_reset(struct phy_device *phydev)
  244. {
  245. int err;
  246. err = phy_write(phydev, MII_DP83811_RESET_CTRL, DP83811_HW_RESET);
  247. if (err < 0)
  248. return err;
  249. return 0;
  250. }
  251. static int dp83811_suspend(struct phy_device *phydev)
  252. {
  253. int value;
  254. value = phy_read_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG);
  255. if (!(value & DP83811_WOL_EN))
  256. genphy_suspend(phydev);
  257. return 0;
  258. }
  259. static int dp83811_resume(struct phy_device *phydev)
  260. {
  261. genphy_resume(phydev);
  262. phy_set_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
  263. DP83811_WOL_CLR_INDICATION);
  264. return 0;
  265. }
  266. static struct phy_driver dp83811_driver[] = {
  267. {
  268. .phy_id = DP83TC811_PHY_ID,
  269. .phy_id_mask = 0xfffffff0,
  270. .name = "TI DP83TC811",
  271. /* PHY_BASIC_FEATURES */
  272. .config_init = dp83811_config_init,
  273. .config_aneg = dp83811_config_aneg,
  274. .soft_reset = dp83811_phy_reset,
  275. .get_wol = dp83811_get_wol,
  276. .set_wol = dp83811_set_wol,
  277. .ack_interrupt = dp83811_ack_interrupt,
  278. .config_intr = dp83811_config_intr,
  279. .suspend = dp83811_suspend,
  280. .resume = dp83811_resume,
  281. },
  282. };
  283. module_phy_driver(dp83811_driver);
  284. static struct mdio_device_id __maybe_unused dp83811_tbl[] = {
  285. { DP83TC811_PHY_ID, 0xfffffff0 },
  286. { },
  287. };
  288. MODULE_DEVICE_TABLE(mdio, dp83811_tbl);
  289. MODULE_DESCRIPTION("Texas Instruments DP83TC811 PHY driver");
  290. MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
  291. MODULE_LICENSE("GPL");