cicada.c 3.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * drivers/net/phy/cicada.c
  4. *
  5. * Driver for Cicada PHYs
  6. *
  7. * Author: Andy Fleming
  8. *
  9. * Copyright (c) 2004 Freescale Semiconductor, Inc.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/string.h>
  13. #include <linux/errno.h>
  14. #include <linux/unistd.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/init.h>
  17. #include <linux/delay.h>
  18. #include <linux/netdevice.h>
  19. #include <linux/etherdevice.h>
  20. #include <linux/skbuff.h>
  21. #include <linux/spinlock.h>
  22. #include <linux/mm.h>
  23. #include <linux/module.h>
  24. #include <linux/mii.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/phy.h>
  27. #include <linux/io.h>
  28. #include <asm/irq.h>
  29. #include <linux/uaccess.h>
  30. /* Cicada Extended Control Register 1 */
  31. #define MII_CIS8201_EXT_CON1 0x17
  32. #define MII_CIS8201_EXTCON1_INIT 0x0000
  33. /* Cicada Interrupt Mask Register */
  34. #define MII_CIS8201_IMASK 0x19
  35. #define MII_CIS8201_IMASK_IEN 0x8000
  36. #define MII_CIS8201_IMASK_SPEED 0x4000
  37. #define MII_CIS8201_IMASK_LINK 0x2000
  38. #define MII_CIS8201_IMASK_DUPLEX 0x1000
  39. #define MII_CIS8201_IMASK_MASK 0xf000
  40. /* Cicada Interrupt Status Register */
  41. #define MII_CIS8201_ISTAT 0x1a
  42. #define MII_CIS8201_ISTAT_STATUS 0x8000
  43. #define MII_CIS8201_ISTAT_SPEED 0x4000
  44. #define MII_CIS8201_ISTAT_LINK 0x2000
  45. #define MII_CIS8201_ISTAT_DUPLEX 0x1000
  46. /* Cicada Auxiliary Control/Status Register */
  47. #define MII_CIS8201_AUX_CONSTAT 0x1c
  48. #define MII_CIS8201_AUXCONSTAT_INIT 0x0004
  49. #define MII_CIS8201_AUXCONSTAT_DUPLEX 0x0020
  50. #define MII_CIS8201_AUXCONSTAT_SPEED 0x0018
  51. #define MII_CIS8201_AUXCONSTAT_GBIT 0x0010
  52. #define MII_CIS8201_AUXCONSTAT_100 0x0008
  53. MODULE_DESCRIPTION("Cicadia PHY driver");
  54. MODULE_AUTHOR("Andy Fleming");
  55. MODULE_LICENSE("GPL");
  56. static int cis820x_config_init(struct phy_device *phydev)
  57. {
  58. int err;
  59. err = phy_write(phydev, MII_CIS8201_AUX_CONSTAT,
  60. MII_CIS8201_AUXCONSTAT_INIT);
  61. if (err < 0)
  62. return err;
  63. err = phy_write(phydev, MII_CIS8201_EXT_CON1,
  64. MII_CIS8201_EXTCON1_INIT);
  65. return err;
  66. }
  67. static int cis820x_ack_interrupt(struct phy_device *phydev)
  68. {
  69. int err = phy_read(phydev, MII_CIS8201_ISTAT);
  70. return (err < 0) ? err : 0;
  71. }
  72. static int cis820x_config_intr(struct phy_device *phydev)
  73. {
  74. int err;
  75. if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
  76. err = phy_write(phydev, MII_CIS8201_IMASK,
  77. MII_CIS8201_IMASK_MASK);
  78. else
  79. err = phy_write(phydev, MII_CIS8201_IMASK, 0);
  80. return err;
  81. }
  82. /* Cicada 8201, a.k.a Vitesse VSC8201 */
  83. static struct phy_driver cis820x_driver[] = {
  84. {
  85. .phy_id = 0x000fc410,
  86. .name = "Cicada Cis8201",
  87. .phy_id_mask = 0x000ffff0,
  88. /* PHY_GBIT_FEATURES */
  89. .config_init = &cis820x_config_init,
  90. .ack_interrupt = &cis820x_ack_interrupt,
  91. .config_intr = &cis820x_config_intr,
  92. }, {
  93. .phy_id = 0x000fc440,
  94. .name = "Cicada Cis8204",
  95. .phy_id_mask = 0x000fffc0,
  96. /* PHY_GBIT_FEATURES */
  97. .config_init = &cis820x_config_init,
  98. .ack_interrupt = &cis820x_ack_interrupt,
  99. .config_intr = &cis820x_config_intr,
  100. } };
  101. module_phy_driver(cis820x_driver);
  102. static struct mdio_device_id __maybe_unused cicada_tbl[] = {
  103. { 0x000fc410, 0x000ffff0 },
  104. { 0x000fc440, 0x000fffc0 },
  105. { }
  106. };
  107. MODULE_DEVICE_TABLE(mdio, cicada_tbl);