bcm84881.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Broadcom BCM84881 NBASE-T PHY driver, as found on a SFP+ module.
  3. // Copyright (C) 2019 Russell King, Deep Blue Solutions Ltd.
  4. //
  5. // Like the Marvell 88x3310, the Broadcom 84881 changes its host-side
  6. // interface according to the operating speed between 10GBASE-R,
  7. // 2500BASE-X and SGMII (but unlike the 88x3310, without the control
  8. // word).
  9. //
  10. // This driver only supports those aspects of the PHY that I'm able to
  11. // observe and test with the SFP+ module, which is an incomplete subset
  12. // of what this PHY is able to support. For example, I only assume it
  13. // supports a single lane Serdes connection, but it may be that the PHY
  14. // is able to support more than that.
  15. #include <linux/delay.h>
  16. #include <linux/module.h>
  17. #include <linux/phy.h>
  18. enum {
  19. MDIO_AN_C22 = 0xffe0,
  20. };
  21. static int bcm84881_wait_init(struct phy_device *phydev)
  22. {
  23. int val;
  24. return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
  25. val, !(val & MDIO_CTRL1_RESET),
  26. 100000, 2000000, false);
  27. }
  28. static int bcm84881_config_init(struct phy_device *phydev)
  29. {
  30. switch (phydev->interface) {
  31. case PHY_INTERFACE_MODE_SGMII:
  32. case PHY_INTERFACE_MODE_2500BASEX:
  33. case PHY_INTERFACE_MODE_10GBASER:
  34. break;
  35. default:
  36. return -ENODEV;
  37. }
  38. return 0;
  39. }
  40. static int bcm84881_probe(struct phy_device *phydev)
  41. {
  42. /* This driver requires PMAPMD and AN blocks */
  43. const u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
  44. if (!phydev->is_c45 ||
  45. (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
  46. return -ENODEV;
  47. return 0;
  48. }
  49. static int bcm84881_get_features(struct phy_device *phydev)
  50. {
  51. int ret;
  52. ret = genphy_c45_pma_read_abilities(phydev);
  53. if (ret)
  54. return ret;
  55. /* Although the PHY sets bit 1.11.8, it does not support 10M modes */
  56. linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
  57. phydev->supported);
  58. linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
  59. phydev->supported);
  60. return 0;
  61. }
  62. static int bcm84881_config_aneg(struct phy_device *phydev)
  63. {
  64. bool changed = false;
  65. u32 adv;
  66. int ret;
  67. /* Wait for the PHY to finish initialising, otherwise our
  68. * advertisement may be overwritten.
  69. */
  70. ret = bcm84881_wait_init(phydev);
  71. if (ret)
  72. return ret;
  73. /* We don't support manual MDI control */
  74. phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
  75. /* disabled autoneg doesn't seem to work with this PHY */
  76. if (phydev->autoneg == AUTONEG_DISABLE)
  77. return -EINVAL;
  78. ret = genphy_c45_an_config_aneg(phydev);
  79. if (ret < 0)
  80. return ret;
  81. if (ret > 0)
  82. changed = true;
  83. adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
  84. ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN,
  85. MDIO_AN_C22 + MII_CTRL1000,
  86. ADVERTISE_1000FULL | ADVERTISE_1000HALF,
  87. adv);
  88. if (ret < 0)
  89. return ret;
  90. if (ret > 0)
  91. changed = true;
  92. return genphy_c45_check_and_restart_aneg(phydev, changed);
  93. }
  94. static int bcm84881_aneg_done(struct phy_device *phydev)
  95. {
  96. int bmsr, val;
  97. val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
  98. if (val < 0)
  99. return val;
  100. bmsr = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_C22 + MII_BMSR);
  101. if (bmsr < 0)
  102. return val;
  103. return !!(val & MDIO_AN_STAT1_COMPLETE) &&
  104. !!(bmsr & BMSR_ANEGCOMPLETE);
  105. }
  106. static int bcm84881_read_status(struct phy_device *phydev)
  107. {
  108. unsigned int mode;
  109. int bmsr, val;
  110. val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
  111. if (val < 0)
  112. return val;
  113. if (val & MDIO_AN_CTRL1_RESTART) {
  114. phydev->link = 0;
  115. return 0;
  116. }
  117. val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
  118. if (val < 0)
  119. return val;
  120. bmsr = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_C22 + MII_BMSR);
  121. if (bmsr < 0)
  122. return val;
  123. phydev->autoneg_complete = !!(val & MDIO_AN_STAT1_COMPLETE) &&
  124. !!(bmsr & BMSR_ANEGCOMPLETE);
  125. phydev->link = !!(val & MDIO_STAT1_LSTATUS) &&
  126. !!(bmsr & BMSR_LSTATUS);
  127. if (phydev->autoneg == AUTONEG_ENABLE && !phydev->autoneg_complete)
  128. phydev->link = false;
  129. linkmode_zero(phydev->lp_advertising);
  130. phydev->speed = SPEED_UNKNOWN;
  131. phydev->duplex = DUPLEX_UNKNOWN;
  132. phydev->pause = 0;
  133. phydev->asym_pause = 0;
  134. phydev->mdix = 0;
  135. if (!phydev->link)
  136. return 0;
  137. if (phydev->autoneg_complete) {
  138. val = genphy_c45_read_lpa(phydev);
  139. if (val < 0)
  140. return val;
  141. val = phy_read_mmd(phydev, MDIO_MMD_AN,
  142. MDIO_AN_C22 + MII_STAT1000);
  143. if (val < 0)
  144. return val;
  145. mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
  146. if (phydev->autoneg == AUTONEG_ENABLE)
  147. phy_resolve_aneg_linkmode(phydev);
  148. }
  149. if (phydev->autoneg == AUTONEG_DISABLE) {
  150. /* disabled autoneg doesn't seem to work, so force the link
  151. * down.
  152. */
  153. phydev->link = 0;
  154. return 0;
  155. }
  156. /* Set the host link mode - we set the phy interface mode and
  157. * the speed according to this register so that downshift works.
  158. * We leave the duplex setting as per the resolution from the
  159. * above.
  160. */
  161. val = phy_read_mmd(phydev, MDIO_MMD_VEND1, 0x4011);
  162. mode = (val & 0x1e) >> 1;
  163. if (mode == 1 || mode == 2)
  164. phydev->interface = PHY_INTERFACE_MODE_SGMII;
  165. else if (mode == 3)
  166. phydev->interface = PHY_INTERFACE_MODE_10GBASER;
  167. else if (mode == 4)
  168. phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
  169. switch (mode & 7) {
  170. case 1:
  171. phydev->speed = SPEED_100;
  172. break;
  173. case 2:
  174. phydev->speed = SPEED_1000;
  175. break;
  176. case 3:
  177. phydev->speed = SPEED_10000;
  178. break;
  179. case 4:
  180. phydev->speed = SPEED_2500;
  181. break;
  182. case 5:
  183. phydev->speed = SPEED_5000;
  184. break;
  185. }
  186. return genphy_c45_read_mdix(phydev);
  187. }
  188. static struct phy_driver bcm84881_drivers[] = {
  189. {
  190. .phy_id = 0xae025150,
  191. .phy_id_mask = 0xfffffff0,
  192. .name = "Broadcom BCM84881",
  193. .config_init = bcm84881_config_init,
  194. .probe = bcm84881_probe,
  195. .get_features = bcm84881_get_features,
  196. .config_aneg = bcm84881_config_aneg,
  197. .aneg_done = bcm84881_aneg_done,
  198. .read_status = bcm84881_read_status,
  199. },
  200. };
  201. module_phy_driver(bcm84881_drivers);
  202. /* FIXME: module auto-loading for Clause 45 PHYs seems non-functional */
  203. static struct mdio_device_id __maybe_unused bcm84881_tbl[] = {
  204. { 0xae025150, 0xfffffff0 },
  205. { },
  206. };
  207. MODULE_AUTHOR("Russell King");
  208. MODULE_DESCRIPTION("Broadcom BCM84881 PHY driver");
  209. MODULE_DEVICE_TABLE(mdio, bcm84881_tbl);
  210. MODULE_LICENSE("GPL");