bcm7xxx.c 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Broadcom BCM7xxx internal transceivers support.
  4. *
  5. * Copyright (C) 2014-2017 Broadcom
  6. */
  7. #include <linux/module.h>
  8. #include <linux/phy.h>
  9. #include <linux/delay.h>
  10. #include "bcm-phy-lib.h"
  11. #include <linux/bitops.h>
  12. #include <linux/brcmphy.h>
  13. #include <linux/clk.h>
  14. #include <linux/mdio.h>
  15. /* Broadcom BCM7xxx internal PHY registers */
  16. /* EPHY only register definitions */
  17. #define MII_BCM7XXX_100TX_AUX_CTL 0x10
  18. #define MII_BCM7XXX_100TX_FALSE_CAR 0x13
  19. #define MII_BCM7XXX_100TX_DISC 0x14
  20. #define MII_BCM7XXX_AUX_MODE 0x1d
  21. #define MII_BCM7XXX_64CLK_MDIO BIT(12)
  22. #define MII_BCM7XXX_TEST 0x1f
  23. #define MII_BCM7XXX_SHD_MODE_2 BIT(2)
  24. #define MII_BCM7XXX_SHD_2_ADDR_CTRL 0xe
  25. #define MII_BCM7XXX_SHD_2_CTRL_STAT 0xf
  26. #define MII_BCM7XXX_SHD_2_BIAS_TRIM 0x1a
  27. #define MII_BCM7XXX_SHD_3_PCS_CTRL 0x0
  28. #define MII_BCM7XXX_SHD_3_PCS_STATUS 0x1
  29. #define MII_BCM7XXX_SHD_3_EEE_CAP 0x2
  30. #define MII_BCM7XXX_SHD_3_AN_EEE_ADV 0x3
  31. #define MII_BCM7XXX_SHD_3_EEE_LP 0x4
  32. #define MII_BCM7XXX_SHD_3_EEE_WK_ERR 0x5
  33. #define MII_BCM7XXX_SHD_3_PCS_CTRL_2 0x6
  34. #define MII_BCM7XXX_PCS_CTRL_2_DEF 0x4400
  35. #define MII_BCM7XXX_SHD_3_AN_STAT 0xb
  36. #define MII_BCM7XXX_AN_NULL_MSG_EN BIT(0)
  37. #define MII_BCM7XXX_AN_EEE_EN BIT(1)
  38. #define MII_BCM7XXX_SHD_3_EEE_THRESH 0xe
  39. #define MII_BCM7XXX_EEE_THRESH_DEF 0x50
  40. #define MII_BCM7XXX_SHD_3_TL4 0x23
  41. #define MII_BCM7XXX_TL4_RST_MSK (BIT(2) | BIT(1))
  42. struct bcm7xxx_phy_priv {
  43. u64 *stats;
  44. struct clk *clk;
  45. };
  46. static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev)
  47. {
  48. /* AFE_RXCONFIG_0 */
  49. bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15);
  50. /* AFE_RXCONFIG_1 */
  51. bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);
  52. /* AFE_RXCONFIG_2, set rCal offset for HT=0 code and LT=-2 code */
  53. bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003);
  54. /* AFE_RX_LP_COUNTER, set RX bandwidth to maximum */
  55. bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
  56. /* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
  57. bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);
  58. /* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
  59. bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);
  60. /* AFE_VDAC_OTHERS_0, set 1000BT Cidac=010 for all ports */
  61. bcm_phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020);
  62. /* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
  63. * offset for HT=0 code
  64. */
  65. bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
  66. /* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
  67. phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
  68. /* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
  69. bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);
  70. /* Reset R_CAL/RC_CAL engine */
  71. bcm_phy_r_rc_cal_reset(phydev);
  72. return 0;
  73. }
  74. static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev)
  75. {
  76. /* AFE_RXCONFIG_1, provide more margin for INL/DNL measurement */
  77. bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);
  78. /* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
  79. bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);
  80. /* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
  81. bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);
  82. /* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
  83. * offset for HT=0 code
  84. */
  85. bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
  86. /* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
  87. phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
  88. /* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
  89. bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);
  90. /* Reset R_CAL/RC_CAL engine */
  91. bcm_phy_r_rc_cal_reset(phydev);
  92. return 0;
  93. }
  94. static int bcm7xxx_28nm_a0_patch_afe_config_init(struct phy_device *phydev)
  95. {
  96. /* +1 RC_CAL codes for RL centering for both LT and HT conditions */
  97. bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0xd003);
  98. /* Cut master bias current by 2% to compensate for RC_CAL offset */
  99. bcm_phy_write_misc(phydev, DSP_TAP10, 0x791b);
  100. /* Improve hybrid leakage */
  101. bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x10e3);
  102. /* Change rx_on_tune 8 to 0xf */
  103. bcm_phy_write_misc(phydev, 0x21, 0x2, 0x87f6);
  104. /* Change 100Tx EEE bandwidth */
  105. bcm_phy_write_misc(phydev, 0x22, 0x2, 0x017d);
  106. /* Enable ffe zero detection for Vitesse interoperability */
  107. bcm_phy_write_misc(phydev, 0x26, 0x2, 0x0015);
  108. bcm_phy_r_rc_cal_reset(phydev);
  109. return 0;
  110. }
  111. static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
  112. {
  113. u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);
  114. u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);
  115. u8 count;
  116. int ret = 0;
  117. /* Newer devices have moved the revision information back into a
  118. * standard location in MII_PHYS_ID[23]
  119. */
  120. if (rev == 0)
  121. rev = phydev->phy_id & ~phydev->drv->phy_id_mask;
  122. pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n",
  123. phydev_name(phydev), phydev->drv->name, rev, patch);
  124. /* Dummy read to a register to workaround an issue upon reset where the
  125. * internal inverter may not allow the first MDIO transaction to pass
  126. * the MDIO management controller and make us return 0xffff for such
  127. * reads.
  128. */
  129. phy_read(phydev, MII_BMSR);
  130. switch (rev) {
  131. case 0xa0:
  132. case 0xb0:
  133. ret = bcm_phy_28nm_a0b0_afe_config_init(phydev);
  134. break;
  135. case 0xd0:
  136. ret = bcm7xxx_28nm_d0_afe_config_init(phydev);
  137. break;
  138. case 0xe0:
  139. case 0xf0:
  140. /* Rev G0 introduces a roll over */
  141. case 0x10:
  142. ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev);
  143. break;
  144. case 0x01:
  145. ret = bcm7xxx_28nm_a0_patch_afe_config_init(phydev);
  146. break;
  147. default:
  148. break;
  149. }
  150. if (ret)
  151. return ret;
  152. ret = bcm_phy_enable_jumbo(phydev);
  153. if (ret)
  154. return ret;
  155. ret = bcm_phy_downshift_get(phydev, &count);
  156. if (ret)
  157. return ret;
  158. /* Only enable EEE if Wirespeed/downshift is disabled */
  159. ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE);
  160. if (ret)
  161. return ret;
  162. return bcm_phy_enable_apd(phydev, true);
  163. }
  164. static int bcm7xxx_28nm_resume(struct phy_device *phydev)
  165. {
  166. int ret;
  167. /* Re-apply workarounds coming out suspend/resume */
  168. ret = bcm7xxx_28nm_config_init(phydev);
  169. if (ret)
  170. return ret;
  171. /* 28nm Gigabit PHYs come out of reset without any half-duplex
  172. * or "hub" compliant advertised mode, fix that. This does not
  173. * cause any problems with the PHY library since genphy_config_aneg()
  174. * gracefully handles auto-negotiated and forced modes.
  175. */
  176. return genphy_config_aneg(phydev);
  177. }
  178. static int __phy_set_clr_bits(struct phy_device *dev, int location,
  179. int set_mask, int clr_mask)
  180. {
  181. int v, ret;
  182. v = __phy_read(dev, location);
  183. if (v < 0)
  184. return v;
  185. v &= ~clr_mask;
  186. v |= set_mask;
  187. ret = __phy_write(dev, location, v);
  188. if (ret < 0)
  189. return ret;
  190. return v;
  191. }
  192. static int phy_set_clr_bits(struct phy_device *dev, int location,
  193. int set_mask, int clr_mask)
  194. {
  195. int ret;
  196. mutex_lock(&dev->mdio.bus->mdio_lock);
  197. ret = __phy_set_clr_bits(dev, location, set_mask, clr_mask);
  198. mutex_unlock(&dev->mdio.bus->mdio_lock);
  199. return ret;
  200. }
  201. static int bcm7xxx_28nm_ephy_01_afe_config_init(struct phy_device *phydev)
  202. {
  203. int ret;
  204. /* set shadow mode 2 */
  205. ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
  206. MII_BCM7XXX_SHD_MODE_2, 0);
  207. if (ret < 0)
  208. return ret;
  209. /* Set current trim values INT_trim = -1, Ext_trim =0 */
  210. ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0);
  211. if (ret < 0)
  212. goto reset_shadow_mode;
  213. /* Cal reset */
  214. ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
  215. MII_BCM7XXX_SHD_3_TL4);
  216. if (ret < 0)
  217. goto reset_shadow_mode;
  218. ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
  219. MII_BCM7XXX_TL4_RST_MSK, 0);
  220. if (ret < 0)
  221. goto reset_shadow_mode;
  222. /* Cal reset disable */
  223. ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
  224. MII_BCM7XXX_SHD_3_TL4);
  225. if (ret < 0)
  226. goto reset_shadow_mode;
  227. ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
  228. 0, MII_BCM7XXX_TL4_RST_MSK);
  229. if (ret < 0)
  230. goto reset_shadow_mode;
  231. reset_shadow_mode:
  232. /* reset shadow mode 2 */
  233. ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
  234. MII_BCM7XXX_SHD_MODE_2);
  235. if (ret < 0)
  236. return ret;
  237. return 0;
  238. }
  239. /* The 28nm EPHY does not support Clause 45 (MMD) used by bcm-phy-lib */
  240. static int bcm7xxx_28nm_ephy_apd_enable(struct phy_device *phydev)
  241. {
  242. int ret;
  243. /* set shadow mode 1 */
  244. ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST,
  245. MII_BRCM_FET_BT_SRE, 0);
  246. if (ret < 0)
  247. return ret;
  248. /* Enable auto-power down */
  249. ret = phy_set_clr_bits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
  250. MII_BRCM_FET_SHDW_AS2_APDE, 0);
  251. if (ret < 0)
  252. return ret;
  253. /* reset shadow mode 1 */
  254. ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST, 0,
  255. MII_BRCM_FET_BT_SRE);
  256. if (ret < 0)
  257. return ret;
  258. return 0;
  259. }
  260. static int bcm7xxx_28nm_ephy_eee_enable(struct phy_device *phydev)
  261. {
  262. int ret;
  263. /* set shadow mode 2 */
  264. ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
  265. MII_BCM7XXX_SHD_MODE_2, 0);
  266. if (ret < 0)
  267. return ret;
  268. /* Advertise supported modes */
  269. ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
  270. MII_BCM7XXX_SHD_3_AN_EEE_ADV);
  271. if (ret < 0)
  272. goto reset_shadow_mode;
  273. ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
  274. MDIO_EEE_100TX);
  275. if (ret < 0)
  276. goto reset_shadow_mode;
  277. /* Restore Defaults */
  278. ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
  279. MII_BCM7XXX_SHD_3_PCS_CTRL_2);
  280. if (ret < 0)
  281. goto reset_shadow_mode;
  282. ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
  283. MII_BCM7XXX_PCS_CTRL_2_DEF);
  284. if (ret < 0)
  285. goto reset_shadow_mode;
  286. ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
  287. MII_BCM7XXX_SHD_3_EEE_THRESH);
  288. if (ret < 0)
  289. goto reset_shadow_mode;
  290. ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
  291. MII_BCM7XXX_EEE_THRESH_DEF);
  292. if (ret < 0)
  293. goto reset_shadow_mode;
  294. /* Enable EEE autonegotiation */
  295. ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
  296. MII_BCM7XXX_SHD_3_AN_STAT);
  297. if (ret < 0)
  298. goto reset_shadow_mode;
  299. ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
  300. (MII_BCM7XXX_AN_NULL_MSG_EN | MII_BCM7XXX_AN_EEE_EN));
  301. if (ret < 0)
  302. goto reset_shadow_mode;
  303. reset_shadow_mode:
  304. /* reset shadow mode 2 */
  305. ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
  306. MII_BCM7XXX_SHD_MODE_2);
  307. if (ret < 0)
  308. return ret;
  309. /* Restart autoneg */
  310. phy_write(phydev, MII_BMCR,
  311. (BMCR_SPEED100 | BMCR_ANENABLE | BMCR_ANRESTART));
  312. return 0;
  313. }
  314. static int bcm7xxx_28nm_ephy_config_init(struct phy_device *phydev)
  315. {
  316. u8 rev = phydev->phy_id & ~phydev->drv->phy_id_mask;
  317. int ret = 0;
  318. pr_info_once("%s: %s PHY revision: 0x%02x\n",
  319. phydev_name(phydev), phydev->drv->name, rev);
  320. /* Dummy read to a register to workaround a possible issue upon reset
  321. * where the internal inverter may not allow the first MDIO transaction
  322. * to pass the MDIO management controller and make us return 0xffff for
  323. * such reads.
  324. */
  325. phy_read(phydev, MII_BMSR);
  326. /* Apply AFE software work-around if necessary */
  327. if (rev == 0x01) {
  328. ret = bcm7xxx_28nm_ephy_01_afe_config_init(phydev);
  329. if (ret)
  330. return ret;
  331. }
  332. ret = bcm7xxx_28nm_ephy_eee_enable(phydev);
  333. if (ret)
  334. return ret;
  335. return bcm7xxx_28nm_ephy_apd_enable(phydev);
  336. }
  337. #define MII_BCM7XXX_REG_INVALID 0xff
  338. static u8 bcm7xxx_28nm_ephy_regnum_to_shd(u16 regnum)
  339. {
  340. switch (regnum) {
  341. case MDIO_CTRL1:
  342. return MII_BCM7XXX_SHD_3_PCS_CTRL;
  343. case MDIO_STAT1:
  344. return MII_BCM7XXX_SHD_3_PCS_STATUS;
  345. case MDIO_PCS_EEE_ABLE:
  346. return MII_BCM7XXX_SHD_3_EEE_CAP;
  347. case MDIO_AN_EEE_ADV:
  348. return MII_BCM7XXX_SHD_3_AN_EEE_ADV;
  349. case MDIO_AN_EEE_LPABLE:
  350. return MII_BCM7XXX_SHD_3_EEE_LP;
  351. case MDIO_PCS_EEE_WK_ERR:
  352. return MII_BCM7XXX_SHD_3_EEE_WK_ERR;
  353. default:
  354. return MII_BCM7XXX_REG_INVALID;
  355. }
  356. }
  357. static bool bcm7xxx_28nm_ephy_dev_valid(int devnum)
  358. {
  359. return devnum == MDIO_MMD_AN || devnum == MDIO_MMD_PCS;
  360. }
  361. static int bcm7xxx_28nm_ephy_read_mmd(struct phy_device *phydev,
  362. int devnum, u16 regnum)
  363. {
  364. u8 shd = bcm7xxx_28nm_ephy_regnum_to_shd(regnum);
  365. int ret;
  366. if (!bcm7xxx_28nm_ephy_dev_valid(devnum) ||
  367. shd == MII_BCM7XXX_REG_INVALID)
  368. return -EOPNOTSUPP;
  369. /* set shadow mode 2 */
  370. ret = __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
  371. MII_BCM7XXX_SHD_MODE_2, 0);
  372. if (ret < 0)
  373. return ret;
  374. /* Access the desired shadow register address */
  375. ret = __phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, shd);
  376. if (ret < 0)
  377. goto reset_shadow_mode;
  378. ret = __phy_read(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT);
  379. reset_shadow_mode:
  380. /* reset shadow mode 2 */
  381. __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
  382. MII_BCM7XXX_SHD_MODE_2);
  383. return ret;
  384. }
  385. static int bcm7xxx_28nm_ephy_write_mmd(struct phy_device *phydev,
  386. int devnum, u16 regnum, u16 val)
  387. {
  388. u8 shd = bcm7xxx_28nm_ephy_regnum_to_shd(regnum);
  389. int ret;
  390. if (!bcm7xxx_28nm_ephy_dev_valid(devnum) ||
  391. shd == MII_BCM7XXX_REG_INVALID)
  392. return -EOPNOTSUPP;
  393. /* set shadow mode 2 */
  394. ret = __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
  395. MII_BCM7XXX_SHD_MODE_2, 0);
  396. if (ret < 0)
  397. return ret;
  398. /* Access the desired shadow register address */
  399. ret = __phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, shd);
  400. if (ret < 0)
  401. goto reset_shadow_mode;
  402. /* Write the desired value in the shadow register */
  403. __phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, val);
  404. reset_shadow_mode:
  405. /* reset shadow mode 2 */
  406. return __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
  407. MII_BCM7XXX_SHD_MODE_2);
  408. }
  409. static int bcm7xxx_28nm_ephy_resume(struct phy_device *phydev)
  410. {
  411. int ret;
  412. /* Re-apply workarounds coming out suspend/resume */
  413. ret = bcm7xxx_28nm_ephy_config_init(phydev);
  414. if (ret)
  415. return ret;
  416. return genphy_config_aneg(phydev);
  417. }
  418. static int bcm7xxx_config_init(struct phy_device *phydev)
  419. {
  420. int ret;
  421. /* Enable 64 clock MDIO */
  422. phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XXX_64CLK_MDIO);
  423. phy_read(phydev, MII_BCM7XXX_AUX_MODE);
  424. /* set shadow mode 2 */
  425. ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
  426. MII_BCM7XXX_SHD_MODE_2, MII_BCM7XXX_SHD_MODE_2);
  427. if (ret < 0)
  428. return ret;
  429. /* set iddq_clkbias */
  430. phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00);
  431. udelay(10);
  432. /* reset iddq_clkbias */
  433. phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00);
  434. phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555);
  435. /* reset shadow mode 2 */
  436. ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, MII_BCM7XXX_SHD_MODE_2);
  437. if (ret < 0)
  438. return ret;
  439. return 0;
  440. }
  441. /* Workaround for putting the PHY in IDDQ mode, required
  442. * for all BCM7XXX 40nm and 65nm PHYs
  443. */
  444. static int bcm7xxx_suspend(struct phy_device *phydev)
  445. {
  446. int ret;
  447. static const struct bcm7xxx_regs {
  448. int reg;
  449. u16 value;
  450. } bcm7xxx_suspend_cfg[] = {
  451. { MII_BCM7XXX_TEST, 0x008b },
  452. { MII_BCM7XXX_100TX_AUX_CTL, 0x01c0 },
  453. { MII_BCM7XXX_100TX_DISC, 0x7000 },
  454. { MII_BCM7XXX_TEST, 0x000f },
  455. { MII_BCM7XXX_100TX_AUX_CTL, 0x20d0 },
  456. { MII_BCM7XXX_TEST, 0x000b },
  457. };
  458. unsigned int i;
  459. for (i = 0; i < ARRAY_SIZE(bcm7xxx_suspend_cfg); i++) {
  460. ret = phy_write(phydev,
  461. bcm7xxx_suspend_cfg[i].reg,
  462. bcm7xxx_suspend_cfg[i].value);
  463. if (ret)
  464. return ret;
  465. }
  466. return 0;
  467. }
  468. static int bcm7xxx_28nm_get_tunable(struct phy_device *phydev,
  469. struct ethtool_tunable *tuna,
  470. void *data)
  471. {
  472. switch (tuna->id) {
  473. case ETHTOOL_PHY_DOWNSHIFT:
  474. return bcm_phy_downshift_get(phydev, (u8 *)data);
  475. default:
  476. return -EOPNOTSUPP;
  477. }
  478. }
  479. static int bcm7xxx_28nm_set_tunable(struct phy_device *phydev,
  480. struct ethtool_tunable *tuna,
  481. const void *data)
  482. {
  483. u8 count = *(u8 *)data;
  484. int ret;
  485. switch (tuna->id) {
  486. case ETHTOOL_PHY_DOWNSHIFT:
  487. ret = bcm_phy_downshift_set(phydev, count);
  488. break;
  489. default:
  490. return -EOPNOTSUPP;
  491. }
  492. if (ret)
  493. return ret;
  494. /* Disable EEE advertisement since this prevents the PHY
  495. * from successfully linking up, trigger auto-negotiation restart
  496. * to let the MAC decide what to do.
  497. */
  498. ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE);
  499. if (ret)
  500. return ret;
  501. return genphy_restart_aneg(phydev);
  502. }
  503. static void bcm7xxx_28nm_get_phy_stats(struct phy_device *phydev,
  504. struct ethtool_stats *stats, u64 *data)
  505. {
  506. struct bcm7xxx_phy_priv *priv = phydev->priv;
  507. bcm_phy_get_stats(phydev, priv->stats, stats, data);
  508. }
  509. static int bcm7xxx_28nm_probe(struct phy_device *phydev)
  510. {
  511. struct bcm7xxx_phy_priv *priv;
  512. int ret = 0;
  513. priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
  514. if (!priv)
  515. return -ENOMEM;
  516. phydev->priv = priv;
  517. priv->stats = devm_kcalloc(&phydev->mdio.dev,
  518. bcm_phy_get_sset_count(phydev), sizeof(u64),
  519. GFP_KERNEL);
  520. if (!priv->stats)
  521. return -ENOMEM;
  522. priv->clk = devm_clk_get_optional(&phydev->mdio.dev, NULL);
  523. if (IS_ERR(priv->clk))
  524. return PTR_ERR(priv->clk);
  525. ret = clk_prepare_enable(priv->clk);
  526. if (ret)
  527. return ret;
  528. /* Dummy read to a register to workaround an issue upon reset where the
  529. * internal inverter may not allow the first MDIO transaction to pass
  530. * the MDIO management controller and make us return 0xffff for such
  531. * reads. This is needed to ensure that any subsequent reads to the
  532. * PHY will succeed.
  533. */
  534. phy_read(phydev, MII_BMSR);
  535. return ret;
  536. }
  537. static void bcm7xxx_28nm_remove(struct phy_device *phydev)
  538. {
  539. struct bcm7xxx_phy_priv *priv = phydev->priv;
  540. clk_disable_unprepare(priv->clk);
  541. }
  542. #define BCM7XXX_28NM_GPHY(_oui, _name) \
  543. { \
  544. .phy_id = (_oui), \
  545. .phy_id_mask = 0xfffffff0, \
  546. .name = _name, \
  547. /* PHY_GBIT_FEATURES */ \
  548. .flags = PHY_IS_INTERNAL, \
  549. .config_init = bcm7xxx_28nm_config_init, \
  550. .resume = bcm7xxx_28nm_resume, \
  551. .get_tunable = bcm7xxx_28nm_get_tunable, \
  552. .set_tunable = bcm7xxx_28nm_set_tunable, \
  553. .get_sset_count = bcm_phy_get_sset_count, \
  554. .get_strings = bcm_phy_get_strings, \
  555. .get_stats = bcm7xxx_28nm_get_phy_stats, \
  556. .probe = bcm7xxx_28nm_probe, \
  557. .remove = bcm7xxx_28nm_remove, \
  558. }
  559. #define BCM7XXX_28NM_EPHY(_oui, _name) \
  560. { \
  561. .phy_id = (_oui), \
  562. .phy_id_mask = 0xfffffff0, \
  563. .name = _name, \
  564. /* PHY_BASIC_FEATURES */ \
  565. .flags = PHY_IS_INTERNAL, \
  566. .config_init = bcm7xxx_28nm_ephy_config_init, \
  567. .resume = bcm7xxx_28nm_ephy_resume, \
  568. .get_sset_count = bcm_phy_get_sset_count, \
  569. .get_strings = bcm_phy_get_strings, \
  570. .get_stats = bcm7xxx_28nm_get_phy_stats, \
  571. .probe = bcm7xxx_28nm_probe, \
  572. .remove = bcm7xxx_28nm_remove, \
  573. .read_mmd = bcm7xxx_28nm_ephy_read_mmd, \
  574. .write_mmd = bcm7xxx_28nm_ephy_write_mmd, \
  575. }
  576. #define BCM7XXX_40NM_EPHY(_oui, _name) \
  577. { \
  578. .phy_id = (_oui), \
  579. .phy_id_mask = 0xfffffff0, \
  580. .name = _name, \
  581. /* PHY_BASIC_FEATURES */ \
  582. .flags = PHY_IS_INTERNAL, \
  583. .soft_reset = genphy_soft_reset, \
  584. .config_init = bcm7xxx_config_init, \
  585. .suspend = bcm7xxx_suspend, \
  586. .resume = bcm7xxx_config_init, \
  587. }
  588. static struct phy_driver bcm7xxx_driver[] = {
  589. BCM7XXX_28NM_EPHY(PHY_ID_BCM72113, "Broadcom BCM72113"),
  590. BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
  591. BCM7XXX_28NM_EPHY(PHY_ID_BCM7255, "Broadcom BCM7255"),
  592. BCM7XXX_28NM_EPHY(PHY_ID_BCM7260, "Broadcom BCM7260"),
  593. BCM7XXX_28NM_EPHY(PHY_ID_BCM7268, "Broadcom BCM7268"),
  594. BCM7XXX_28NM_EPHY(PHY_ID_BCM7271, "Broadcom BCM7271"),
  595. BCM7XXX_28NM_GPHY(PHY_ID_BCM7278, "Broadcom BCM7278"),
  596. BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"),
  597. BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"),
  598. BCM7XXX_28NM_GPHY(PHY_ID_BCM74371, "Broadcom BCM74371"),
  599. BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"),
  600. BCM7XXX_28NM_GPHY(PHY_ID_BCM7439_2, "Broadcom BCM7439 (2)"),
  601. BCM7XXX_28NM_GPHY(PHY_ID_BCM7445, "Broadcom BCM7445"),
  602. BCM7XXX_40NM_EPHY(PHY_ID_BCM7346, "Broadcom BCM7346"),
  603. BCM7XXX_40NM_EPHY(PHY_ID_BCM7362, "Broadcom BCM7362"),
  604. BCM7XXX_40NM_EPHY(PHY_ID_BCM7425, "Broadcom BCM7425"),
  605. BCM7XXX_40NM_EPHY(PHY_ID_BCM7429, "Broadcom BCM7429"),
  606. BCM7XXX_40NM_EPHY(PHY_ID_BCM7435, "Broadcom BCM7435"),
  607. };
  608. static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
  609. { PHY_ID_BCM72113, 0xfffffff0 },
  610. { PHY_ID_BCM7250, 0xfffffff0, },
  611. { PHY_ID_BCM7255, 0xfffffff0, },
  612. { PHY_ID_BCM7260, 0xfffffff0, },
  613. { PHY_ID_BCM7268, 0xfffffff0, },
  614. { PHY_ID_BCM7271, 0xfffffff0, },
  615. { PHY_ID_BCM7278, 0xfffffff0, },
  616. { PHY_ID_BCM7364, 0xfffffff0, },
  617. { PHY_ID_BCM7366, 0xfffffff0, },
  618. { PHY_ID_BCM7346, 0xfffffff0, },
  619. { PHY_ID_BCM7362, 0xfffffff0, },
  620. { PHY_ID_BCM7425, 0xfffffff0, },
  621. { PHY_ID_BCM7429, 0xfffffff0, },
  622. { PHY_ID_BCM74371, 0xfffffff0, },
  623. { PHY_ID_BCM7439, 0xfffffff0, },
  624. { PHY_ID_BCM7435, 0xfffffff0, },
  625. { PHY_ID_BCM7445, 0xfffffff0, },
  626. { }
  627. };
  628. module_phy_driver(bcm7xxx_driver);
  629. MODULE_DEVICE_TABLE(mdio, bcm7xxx_tbl);
  630. MODULE_DESCRIPTION("Broadcom BCM7xxx internal PHY driver");
  631. MODULE_LICENSE("GPL");
  632. MODULE_AUTHOR("Broadcom Corporation");