bcm54140.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /* Broadcom BCM54140 Quad SGMII/QSGMII Copper/Fiber Gigabit PHY
  3. *
  4. * Copyright (c) 2020 Michael Walle <michael@walle.cc>
  5. */
  6. #include <linux/bitfield.h>
  7. #include <linux/brcmphy.h>
  8. #include <linux/hwmon.h>
  9. #include <linux/module.h>
  10. #include <linux/phy.h>
  11. #include "bcm-phy-lib.h"
  12. /* RDB per-port registers
  13. */
  14. #define BCM54140_RDB_ISR 0x00a /* interrupt status */
  15. #define BCM54140_RDB_IMR 0x00b /* interrupt mask */
  16. #define BCM54140_RDB_INT_LINK BIT(1) /* link status changed */
  17. #define BCM54140_RDB_INT_SPEED BIT(2) /* link speed change */
  18. #define BCM54140_RDB_INT_DUPLEX BIT(3) /* duplex mode changed */
  19. #define BCM54140_RDB_SPARE1 0x012 /* spare control 1 */
  20. #define BCM54140_RDB_SPARE1_LSLM BIT(2) /* link speed LED mode */
  21. #define BCM54140_RDB_SPARE2 0x014 /* spare control 2 */
  22. #define BCM54140_RDB_SPARE2_WS_RTRY_DIS BIT(8) /* wirespeed retry disable */
  23. #define BCM54140_RDB_SPARE2_WS_RTRY_LIMIT GENMASK(4, 2) /* retry limit */
  24. #define BCM54140_RDB_SPARE3 0x015 /* spare control 3 */
  25. #define BCM54140_RDB_SPARE3_BIT0 BIT(0)
  26. #define BCM54140_RDB_LED_CTRL 0x019 /* LED control */
  27. #define BCM54140_RDB_LED_CTRL_ACTLINK0 BIT(4)
  28. #define BCM54140_RDB_LED_CTRL_ACTLINK1 BIT(8)
  29. #define BCM54140_RDB_C_APWR 0x01a /* auto power down control */
  30. #define BCM54140_RDB_C_APWR_SINGLE_PULSE BIT(8) /* single pulse */
  31. #define BCM54140_RDB_C_APWR_APD_MODE_DIS 0 /* ADP disable */
  32. #define BCM54140_RDB_C_APWR_APD_MODE_EN 1 /* ADP enable */
  33. #define BCM54140_RDB_C_APWR_APD_MODE_DIS2 2 /* ADP disable */
  34. #define BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG 3 /* ADP enable w/ aneg */
  35. #define BCM54140_RDB_C_APWR_APD_MODE_MASK GENMASK(6, 5)
  36. #define BCM54140_RDB_C_APWR_SLP_TIM_MASK BIT(4)/* sleep timer */
  37. #define BCM54140_RDB_C_APWR_SLP_TIM_2_7 0 /* 2.7s */
  38. #define BCM54140_RDB_C_APWR_SLP_TIM_5_4 1 /* 5.4s */
  39. #define BCM54140_RDB_C_PWR 0x02a /* copper power control */
  40. #define BCM54140_RDB_C_PWR_ISOLATE BIT(5) /* super isolate mode */
  41. #define BCM54140_RDB_C_MISC_CTRL 0x02f /* misc copper control */
  42. #define BCM54140_RDB_C_MISC_CTRL_WS_EN BIT(4) /* wirespeed enable */
  43. /* RDB global registers
  44. */
  45. #define BCM54140_RDB_TOP_IMR 0x82d /* interrupt mask */
  46. #define BCM54140_RDB_TOP_IMR_PORT0 BIT(4)
  47. #define BCM54140_RDB_TOP_IMR_PORT1 BIT(5)
  48. #define BCM54140_RDB_TOP_IMR_PORT2 BIT(6)
  49. #define BCM54140_RDB_TOP_IMR_PORT3 BIT(7)
  50. #define BCM54140_RDB_MON_CTRL 0x831 /* monitor control */
  51. #define BCM54140_RDB_MON_CTRL_V_MODE BIT(3) /* voltage mode */
  52. #define BCM54140_RDB_MON_CTRL_SEL_MASK GENMASK(2, 1)
  53. #define BCM54140_RDB_MON_CTRL_SEL_TEMP 0 /* meassure temperature */
  54. #define BCM54140_RDB_MON_CTRL_SEL_1V0 1 /* meassure AVDDL 1.0V */
  55. #define BCM54140_RDB_MON_CTRL_SEL_3V3 2 /* meassure AVDDH 3.3V */
  56. #define BCM54140_RDB_MON_CTRL_SEL_RR 3 /* meassure all round-robin */
  57. #define BCM54140_RDB_MON_CTRL_PWR_DOWN BIT(0) /* power-down monitor */
  58. #define BCM54140_RDB_MON_TEMP_VAL 0x832 /* temperature value */
  59. #define BCM54140_RDB_MON_TEMP_MAX 0x833 /* temperature high thresh */
  60. #define BCM54140_RDB_MON_TEMP_MIN 0x834 /* temperature low thresh */
  61. #define BCM54140_RDB_MON_TEMP_DATA_MASK GENMASK(9, 0)
  62. #define BCM54140_RDB_MON_1V0_VAL 0x835 /* AVDDL 1.0V value */
  63. #define BCM54140_RDB_MON_1V0_MAX 0x836 /* AVDDL 1.0V high thresh */
  64. #define BCM54140_RDB_MON_1V0_MIN 0x837 /* AVDDL 1.0V low thresh */
  65. #define BCM54140_RDB_MON_1V0_DATA_MASK GENMASK(10, 0)
  66. #define BCM54140_RDB_MON_3V3_VAL 0x838 /* AVDDH 3.3V value */
  67. #define BCM54140_RDB_MON_3V3_MAX 0x839 /* AVDDH 3.3V high thresh */
  68. #define BCM54140_RDB_MON_3V3_MIN 0x83a /* AVDDH 3.3V low thresh */
  69. #define BCM54140_RDB_MON_3V3_DATA_MASK GENMASK(11, 0)
  70. #define BCM54140_RDB_MON_ISR 0x83b /* interrupt status */
  71. #define BCM54140_RDB_MON_ISR_3V3 BIT(2) /* AVDDH 3.3V alarm */
  72. #define BCM54140_RDB_MON_ISR_1V0 BIT(1) /* AVDDL 1.0V alarm */
  73. #define BCM54140_RDB_MON_ISR_TEMP BIT(0) /* temperature alarm */
  74. /* According to the datasheet the formula is:
  75. * T = 413.35 - (0.49055 * bits[9:0])
  76. */
  77. #define BCM54140_HWMON_TO_TEMP(v) (413350L - (v) * 491)
  78. #define BCM54140_HWMON_FROM_TEMP(v) DIV_ROUND_CLOSEST_ULL(413350L - (v), 491)
  79. /* According to the datasheet the formula is:
  80. * U = bits[11:0] / 1024 * 220 / 0.2
  81. *
  82. * Normalized:
  83. * U = bits[11:0] / 4096 * 2514
  84. */
  85. #define BCM54140_HWMON_TO_IN_1V0(v) ((v) * 2514 >> 11)
  86. #define BCM54140_HWMON_FROM_IN_1V0(v) DIV_ROUND_CLOSEST_ULL(((v) << 11), 2514)
  87. /* According to the datasheet the formula is:
  88. * U = bits[10:0] / 1024 * 880 / 0.7
  89. *
  90. * Normalized:
  91. * U = bits[10:0] / 2048 * 4400
  92. */
  93. #define BCM54140_HWMON_TO_IN_3V3(v) ((v) * 4400 >> 12)
  94. #define BCM54140_HWMON_FROM_IN_3V3(v) DIV_ROUND_CLOSEST_ULL(((v) << 12), 4400)
  95. #define BCM54140_HWMON_TO_IN(ch, v) ((ch) ? BCM54140_HWMON_TO_IN_3V3(v) \
  96. : BCM54140_HWMON_TO_IN_1V0(v))
  97. #define BCM54140_HWMON_FROM_IN(ch, v) ((ch) ? BCM54140_HWMON_FROM_IN_3V3(v) \
  98. : BCM54140_HWMON_FROM_IN_1V0(v))
  99. #define BCM54140_HWMON_IN_MASK(ch) ((ch) ? BCM54140_RDB_MON_3V3_DATA_MASK \
  100. : BCM54140_RDB_MON_1V0_DATA_MASK)
  101. #define BCM54140_HWMON_IN_VAL_REG(ch) ((ch) ? BCM54140_RDB_MON_3V3_VAL \
  102. : BCM54140_RDB_MON_1V0_VAL)
  103. #define BCM54140_HWMON_IN_MIN_REG(ch) ((ch) ? BCM54140_RDB_MON_3V3_MIN \
  104. : BCM54140_RDB_MON_1V0_MIN)
  105. #define BCM54140_HWMON_IN_MAX_REG(ch) ((ch) ? BCM54140_RDB_MON_3V3_MAX \
  106. : BCM54140_RDB_MON_1V0_MAX)
  107. #define BCM54140_HWMON_IN_ALARM_BIT(ch) ((ch) ? BCM54140_RDB_MON_ISR_3V3 \
  108. : BCM54140_RDB_MON_ISR_1V0)
  109. /* This PHY has two different PHY IDs depening on its MODE_SEL pin. This
  110. * pin choses between 4x SGMII and QSGMII mode:
  111. * AE02_5009 4x SGMII
  112. * AE02_5019 QSGMII
  113. */
  114. #define BCM54140_PHY_ID_MASK 0xffffffe8
  115. #define BCM54140_PHY_ID_REV(phy_id) ((phy_id) & 0x7)
  116. #define BCM54140_REV_B0 1
  117. #define BCM54140_DEFAULT_DOWNSHIFT 5
  118. #define BCM54140_MAX_DOWNSHIFT 9
  119. struct bcm54140_priv {
  120. int port;
  121. int base_addr;
  122. #if IS_ENABLED(CONFIG_HWMON)
  123. /* protect the alarm bits */
  124. struct mutex alarm_lock;
  125. u16 alarm;
  126. #endif
  127. };
  128. #if IS_ENABLED(CONFIG_HWMON)
  129. static umode_t bcm54140_hwmon_is_visible(const void *data,
  130. enum hwmon_sensor_types type,
  131. u32 attr, int channel)
  132. {
  133. switch (type) {
  134. case hwmon_in:
  135. switch (attr) {
  136. case hwmon_in_min:
  137. case hwmon_in_max:
  138. return 0644;
  139. case hwmon_in_label:
  140. case hwmon_in_input:
  141. case hwmon_in_alarm:
  142. return 0444;
  143. default:
  144. return 0;
  145. }
  146. case hwmon_temp:
  147. switch (attr) {
  148. case hwmon_temp_min:
  149. case hwmon_temp_max:
  150. return 0644;
  151. case hwmon_temp_input:
  152. case hwmon_temp_alarm:
  153. return 0444;
  154. default:
  155. return 0;
  156. }
  157. default:
  158. return 0;
  159. }
  160. }
  161. static int bcm54140_hwmon_read_alarm(struct device *dev, unsigned int bit,
  162. long *val)
  163. {
  164. struct phy_device *phydev = dev_get_drvdata(dev);
  165. struct bcm54140_priv *priv = phydev->priv;
  166. int tmp, ret = 0;
  167. mutex_lock(&priv->alarm_lock);
  168. /* latch any alarm bits */
  169. tmp = bcm_phy_read_rdb(phydev, BCM54140_RDB_MON_ISR);
  170. if (tmp < 0) {
  171. ret = tmp;
  172. goto out;
  173. }
  174. priv->alarm |= tmp;
  175. *val = !!(priv->alarm & bit);
  176. priv->alarm &= ~bit;
  177. out:
  178. mutex_unlock(&priv->alarm_lock);
  179. return ret;
  180. }
  181. static int bcm54140_hwmon_read_temp(struct device *dev, u32 attr, long *val)
  182. {
  183. struct phy_device *phydev = dev_get_drvdata(dev);
  184. u16 reg;
  185. int tmp;
  186. switch (attr) {
  187. case hwmon_temp_input:
  188. reg = BCM54140_RDB_MON_TEMP_VAL;
  189. break;
  190. case hwmon_temp_min:
  191. reg = BCM54140_RDB_MON_TEMP_MIN;
  192. break;
  193. case hwmon_temp_max:
  194. reg = BCM54140_RDB_MON_TEMP_MAX;
  195. break;
  196. case hwmon_temp_alarm:
  197. return bcm54140_hwmon_read_alarm(dev,
  198. BCM54140_RDB_MON_ISR_TEMP,
  199. val);
  200. default:
  201. return -EOPNOTSUPP;
  202. }
  203. tmp = bcm_phy_read_rdb(phydev, reg);
  204. if (tmp < 0)
  205. return tmp;
  206. *val = BCM54140_HWMON_TO_TEMP(tmp & BCM54140_RDB_MON_TEMP_DATA_MASK);
  207. return 0;
  208. }
  209. static int bcm54140_hwmon_read_in(struct device *dev, u32 attr,
  210. int channel, long *val)
  211. {
  212. struct phy_device *phydev = dev_get_drvdata(dev);
  213. u16 bit, reg;
  214. int tmp;
  215. switch (attr) {
  216. case hwmon_in_input:
  217. reg = BCM54140_HWMON_IN_VAL_REG(channel);
  218. break;
  219. case hwmon_in_min:
  220. reg = BCM54140_HWMON_IN_MIN_REG(channel);
  221. break;
  222. case hwmon_in_max:
  223. reg = BCM54140_HWMON_IN_MAX_REG(channel);
  224. break;
  225. case hwmon_in_alarm:
  226. bit = BCM54140_HWMON_IN_ALARM_BIT(channel);
  227. return bcm54140_hwmon_read_alarm(dev, bit, val);
  228. default:
  229. return -EOPNOTSUPP;
  230. }
  231. tmp = bcm_phy_read_rdb(phydev, reg);
  232. if (tmp < 0)
  233. return tmp;
  234. tmp &= BCM54140_HWMON_IN_MASK(channel);
  235. *val = BCM54140_HWMON_TO_IN(channel, tmp);
  236. return 0;
  237. }
  238. static int bcm54140_hwmon_read(struct device *dev,
  239. enum hwmon_sensor_types type, u32 attr,
  240. int channel, long *val)
  241. {
  242. switch (type) {
  243. case hwmon_temp:
  244. return bcm54140_hwmon_read_temp(dev, attr, val);
  245. case hwmon_in:
  246. return bcm54140_hwmon_read_in(dev, attr, channel, val);
  247. default:
  248. return -EOPNOTSUPP;
  249. }
  250. }
  251. static const char *const bcm54140_hwmon_in_labels[] = {
  252. "AVDDL",
  253. "AVDDH",
  254. };
  255. static int bcm54140_hwmon_read_string(struct device *dev,
  256. enum hwmon_sensor_types type, u32 attr,
  257. int channel, const char **str)
  258. {
  259. switch (type) {
  260. case hwmon_in:
  261. switch (attr) {
  262. case hwmon_in_label:
  263. *str = bcm54140_hwmon_in_labels[channel];
  264. return 0;
  265. default:
  266. return -EOPNOTSUPP;
  267. }
  268. default:
  269. return -EOPNOTSUPP;
  270. }
  271. }
  272. static int bcm54140_hwmon_write_temp(struct device *dev, u32 attr,
  273. int channel, long val)
  274. {
  275. struct phy_device *phydev = dev_get_drvdata(dev);
  276. u16 mask = BCM54140_RDB_MON_TEMP_DATA_MASK;
  277. u16 reg;
  278. val = clamp_val(val, BCM54140_HWMON_TO_TEMP(mask),
  279. BCM54140_HWMON_TO_TEMP(0));
  280. switch (attr) {
  281. case hwmon_temp_min:
  282. reg = BCM54140_RDB_MON_TEMP_MIN;
  283. break;
  284. case hwmon_temp_max:
  285. reg = BCM54140_RDB_MON_TEMP_MAX;
  286. break;
  287. default:
  288. return -EOPNOTSUPP;
  289. }
  290. return bcm_phy_modify_rdb(phydev, reg, mask,
  291. BCM54140_HWMON_FROM_TEMP(val));
  292. }
  293. static int bcm54140_hwmon_write_in(struct device *dev, u32 attr,
  294. int channel, long val)
  295. {
  296. struct phy_device *phydev = dev_get_drvdata(dev);
  297. u16 mask = BCM54140_HWMON_IN_MASK(channel);
  298. u16 reg;
  299. val = clamp_val(val, 0, BCM54140_HWMON_TO_IN(channel, mask));
  300. switch (attr) {
  301. case hwmon_in_min:
  302. reg = BCM54140_HWMON_IN_MIN_REG(channel);
  303. break;
  304. case hwmon_in_max:
  305. reg = BCM54140_HWMON_IN_MAX_REG(channel);
  306. break;
  307. default:
  308. return -EOPNOTSUPP;
  309. }
  310. return bcm_phy_modify_rdb(phydev, reg, mask,
  311. BCM54140_HWMON_FROM_IN(channel, val));
  312. }
  313. static int bcm54140_hwmon_write(struct device *dev,
  314. enum hwmon_sensor_types type, u32 attr,
  315. int channel, long val)
  316. {
  317. switch (type) {
  318. case hwmon_temp:
  319. return bcm54140_hwmon_write_temp(dev, attr, channel, val);
  320. case hwmon_in:
  321. return bcm54140_hwmon_write_in(dev, attr, channel, val);
  322. default:
  323. return -EOPNOTSUPP;
  324. }
  325. }
  326. static const struct hwmon_channel_info *bcm54140_hwmon_info[] = {
  327. HWMON_CHANNEL_INFO(temp,
  328. HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
  329. HWMON_T_ALARM),
  330. HWMON_CHANNEL_INFO(in,
  331. HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
  332. HWMON_I_ALARM | HWMON_I_LABEL,
  333. HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
  334. HWMON_I_ALARM | HWMON_I_LABEL),
  335. NULL
  336. };
  337. static const struct hwmon_ops bcm54140_hwmon_ops = {
  338. .is_visible = bcm54140_hwmon_is_visible,
  339. .read = bcm54140_hwmon_read,
  340. .read_string = bcm54140_hwmon_read_string,
  341. .write = bcm54140_hwmon_write,
  342. };
  343. static const struct hwmon_chip_info bcm54140_chip_info = {
  344. .ops = &bcm54140_hwmon_ops,
  345. .info = bcm54140_hwmon_info,
  346. };
  347. static int bcm54140_enable_monitoring(struct phy_device *phydev)
  348. {
  349. u16 mask, set;
  350. /* 3.3V voltage mode */
  351. set = BCM54140_RDB_MON_CTRL_V_MODE;
  352. /* select round-robin */
  353. mask = BCM54140_RDB_MON_CTRL_SEL_MASK;
  354. set |= FIELD_PREP(BCM54140_RDB_MON_CTRL_SEL_MASK,
  355. BCM54140_RDB_MON_CTRL_SEL_RR);
  356. /* remove power-down bit */
  357. mask |= BCM54140_RDB_MON_CTRL_PWR_DOWN;
  358. return bcm_phy_modify_rdb(phydev, BCM54140_RDB_MON_CTRL, mask, set);
  359. }
  360. static int bcm54140_probe_once(struct phy_device *phydev)
  361. {
  362. struct device *hwmon;
  363. int ret;
  364. /* enable hardware monitoring */
  365. ret = bcm54140_enable_monitoring(phydev);
  366. if (ret)
  367. return ret;
  368. hwmon = devm_hwmon_device_register_with_info(&phydev->mdio.dev,
  369. "BCM54140", phydev,
  370. &bcm54140_chip_info,
  371. NULL);
  372. return PTR_ERR_OR_ZERO(hwmon);
  373. }
  374. #endif
  375. static int bcm54140_base_read_rdb(struct phy_device *phydev, u16 rdb)
  376. {
  377. int ret;
  378. phy_lock_mdio_bus(phydev);
  379. ret = __phy_package_write(phydev, MII_BCM54XX_RDB_ADDR, rdb);
  380. if (ret < 0)
  381. goto out;
  382. ret = __phy_package_read(phydev, MII_BCM54XX_RDB_DATA);
  383. out:
  384. phy_unlock_mdio_bus(phydev);
  385. return ret;
  386. }
  387. static int bcm54140_base_write_rdb(struct phy_device *phydev,
  388. u16 rdb, u16 val)
  389. {
  390. int ret;
  391. phy_lock_mdio_bus(phydev);
  392. ret = __phy_package_write(phydev, MII_BCM54XX_RDB_ADDR, rdb);
  393. if (ret < 0)
  394. goto out;
  395. ret = __phy_package_write(phydev, MII_BCM54XX_RDB_DATA, val);
  396. out:
  397. phy_unlock_mdio_bus(phydev);
  398. return ret;
  399. }
  400. /* Under some circumstances a core PLL may not lock, this will then prevent
  401. * a successful link establishment. Restart the PLL after the voltages are
  402. * stable to workaround this issue.
  403. */
  404. static int bcm54140_b0_workaround(struct phy_device *phydev)
  405. {
  406. int spare3;
  407. int ret;
  408. spare3 = bcm_phy_read_rdb(phydev, BCM54140_RDB_SPARE3);
  409. if (spare3 < 0)
  410. return spare3;
  411. spare3 &= ~BCM54140_RDB_SPARE3_BIT0;
  412. ret = bcm_phy_write_rdb(phydev, BCM54140_RDB_SPARE3, spare3);
  413. if (ret)
  414. return ret;
  415. ret = phy_modify(phydev, MII_BMCR, 0, BMCR_PDOWN);
  416. if (ret)
  417. return ret;
  418. ret = phy_modify(phydev, MII_BMCR, BMCR_PDOWN, 0);
  419. if (ret)
  420. return ret;
  421. spare3 |= BCM54140_RDB_SPARE3_BIT0;
  422. return bcm_phy_write_rdb(phydev, BCM54140_RDB_SPARE3, spare3);
  423. }
  424. /* The BCM54140 is a quad PHY where only the first port has access to the
  425. * global register. Thus we need to find out its PHY address.
  426. *
  427. */
  428. static int bcm54140_get_base_addr_and_port(struct phy_device *phydev)
  429. {
  430. struct bcm54140_priv *priv = phydev->priv;
  431. struct mii_bus *bus = phydev->mdio.bus;
  432. int addr, min_addr, max_addr;
  433. int step = 1;
  434. u32 phy_id;
  435. int tmp;
  436. min_addr = phydev->mdio.addr;
  437. max_addr = phydev->mdio.addr;
  438. addr = phydev->mdio.addr;
  439. /* We scan forward and backwards and look for PHYs which have the
  440. * same phy_id like we do. Step 1 will scan forward, step 2
  441. * backwards. Once we are finished, we have a min_addr and
  442. * max_addr which resembles the range of PHY addresses of the same
  443. * type of PHY. There is one caveat; there may be many PHYs of
  444. * the same type, but we know that each PHY takes exactly 4
  445. * consecutive addresses. Therefore we can deduce our offset
  446. * to the base address of this quad PHY.
  447. */
  448. while (1) {
  449. if (step == 3) {
  450. break;
  451. } else if (step == 1) {
  452. max_addr = addr;
  453. addr++;
  454. } else {
  455. min_addr = addr;
  456. addr--;
  457. }
  458. if (addr < 0 || addr >= PHY_MAX_ADDR) {
  459. addr = phydev->mdio.addr;
  460. step++;
  461. continue;
  462. }
  463. /* read the PHY id */
  464. tmp = mdiobus_read(bus, addr, MII_PHYSID1);
  465. if (tmp < 0)
  466. return tmp;
  467. phy_id = tmp << 16;
  468. tmp = mdiobus_read(bus, addr, MII_PHYSID2);
  469. if (tmp < 0)
  470. return tmp;
  471. phy_id |= tmp;
  472. /* see if it is still the same PHY */
  473. if ((phy_id & phydev->drv->phy_id_mask) !=
  474. (phydev->drv->phy_id & phydev->drv->phy_id_mask)) {
  475. addr = phydev->mdio.addr;
  476. step++;
  477. }
  478. }
  479. /* The range we get should be a multiple of four. Please note that both
  480. * the min_addr and max_addr are inclusive. So we have to add one if we
  481. * subtract them.
  482. */
  483. if ((max_addr - min_addr + 1) % 4) {
  484. dev_err(&phydev->mdio.dev,
  485. "Detected Quad PHY IDs %d..%d doesn't make sense.\n",
  486. min_addr, max_addr);
  487. return -EINVAL;
  488. }
  489. priv->port = (phydev->mdio.addr - min_addr) % 4;
  490. priv->base_addr = phydev->mdio.addr - priv->port;
  491. return 0;
  492. }
  493. static int bcm54140_probe(struct phy_device *phydev)
  494. {
  495. struct bcm54140_priv *priv;
  496. int ret;
  497. priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
  498. if (!priv)
  499. return -ENOMEM;
  500. phydev->priv = priv;
  501. ret = bcm54140_get_base_addr_and_port(phydev);
  502. if (ret)
  503. return ret;
  504. devm_phy_package_join(&phydev->mdio.dev, phydev, priv->base_addr, 0);
  505. #if IS_ENABLED(CONFIG_HWMON)
  506. mutex_init(&priv->alarm_lock);
  507. if (phy_package_init_once(phydev)) {
  508. ret = bcm54140_probe_once(phydev);
  509. if (ret)
  510. return ret;
  511. }
  512. #endif
  513. phydev_dbg(phydev, "probed (port %d, base PHY address %d)\n",
  514. priv->port, priv->base_addr);
  515. return 0;
  516. }
  517. static int bcm54140_config_init(struct phy_device *phydev)
  518. {
  519. u16 reg = 0xffff;
  520. int ret;
  521. /* Apply hardware errata */
  522. if (BCM54140_PHY_ID_REV(phydev->phy_id) == BCM54140_REV_B0) {
  523. ret = bcm54140_b0_workaround(phydev);
  524. if (ret)
  525. return ret;
  526. }
  527. /* Unmask events we are interested in. */
  528. reg &= ~(BCM54140_RDB_INT_DUPLEX |
  529. BCM54140_RDB_INT_SPEED |
  530. BCM54140_RDB_INT_LINK);
  531. ret = bcm_phy_write_rdb(phydev, BCM54140_RDB_IMR, reg);
  532. if (ret)
  533. return ret;
  534. /* LED1=LINKSPD[1], LED2=LINKSPD[2], LED3=LINK/ACTIVITY */
  535. ret = bcm_phy_modify_rdb(phydev, BCM54140_RDB_SPARE1,
  536. 0, BCM54140_RDB_SPARE1_LSLM);
  537. if (ret)
  538. return ret;
  539. ret = bcm_phy_modify_rdb(phydev, BCM54140_RDB_LED_CTRL,
  540. 0, BCM54140_RDB_LED_CTRL_ACTLINK0);
  541. if (ret)
  542. return ret;
  543. /* disable super isolate mode */
  544. return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_PWR,
  545. BCM54140_RDB_C_PWR_ISOLATE, 0);
  546. }
  547. static int bcm54140_did_interrupt(struct phy_device *phydev)
  548. {
  549. int ret;
  550. ret = bcm_phy_read_rdb(phydev, BCM54140_RDB_ISR);
  551. return (ret < 0) ? 0 : ret;
  552. }
  553. static int bcm54140_ack_intr(struct phy_device *phydev)
  554. {
  555. int reg;
  556. /* clear pending interrupts */
  557. reg = bcm_phy_read_rdb(phydev, BCM54140_RDB_ISR);
  558. if (reg < 0)
  559. return reg;
  560. return 0;
  561. }
  562. static int bcm54140_config_intr(struct phy_device *phydev)
  563. {
  564. struct bcm54140_priv *priv = phydev->priv;
  565. static const u16 port_to_imr_bit[] = {
  566. BCM54140_RDB_TOP_IMR_PORT0, BCM54140_RDB_TOP_IMR_PORT1,
  567. BCM54140_RDB_TOP_IMR_PORT2, BCM54140_RDB_TOP_IMR_PORT3,
  568. };
  569. int reg;
  570. if (priv->port >= ARRAY_SIZE(port_to_imr_bit))
  571. return -EINVAL;
  572. reg = bcm54140_base_read_rdb(phydev, BCM54140_RDB_TOP_IMR);
  573. if (reg < 0)
  574. return reg;
  575. if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
  576. reg &= ~port_to_imr_bit[priv->port];
  577. else
  578. reg |= port_to_imr_bit[priv->port];
  579. return bcm54140_base_write_rdb(phydev, BCM54140_RDB_TOP_IMR, reg);
  580. }
  581. static int bcm54140_get_downshift(struct phy_device *phydev, u8 *data)
  582. {
  583. int val;
  584. val = bcm_phy_read_rdb(phydev, BCM54140_RDB_C_MISC_CTRL);
  585. if (val < 0)
  586. return val;
  587. if (!(val & BCM54140_RDB_C_MISC_CTRL_WS_EN)) {
  588. *data = DOWNSHIFT_DEV_DISABLE;
  589. return 0;
  590. }
  591. val = bcm_phy_read_rdb(phydev, BCM54140_RDB_SPARE2);
  592. if (val < 0)
  593. return val;
  594. if (val & BCM54140_RDB_SPARE2_WS_RTRY_DIS)
  595. *data = 1;
  596. else
  597. *data = FIELD_GET(BCM54140_RDB_SPARE2_WS_RTRY_LIMIT, val) + 2;
  598. return 0;
  599. }
  600. static int bcm54140_set_downshift(struct phy_device *phydev, u8 cnt)
  601. {
  602. u16 mask, set;
  603. int ret;
  604. if (cnt > BCM54140_MAX_DOWNSHIFT && cnt != DOWNSHIFT_DEV_DEFAULT_COUNT)
  605. return -EINVAL;
  606. if (!cnt)
  607. return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_MISC_CTRL,
  608. BCM54140_RDB_C_MISC_CTRL_WS_EN, 0);
  609. if (cnt == DOWNSHIFT_DEV_DEFAULT_COUNT)
  610. cnt = BCM54140_DEFAULT_DOWNSHIFT;
  611. if (cnt == 1) {
  612. mask = 0;
  613. set = BCM54140_RDB_SPARE2_WS_RTRY_DIS;
  614. } else {
  615. mask = BCM54140_RDB_SPARE2_WS_RTRY_DIS;
  616. mask |= BCM54140_RDB_SPARE2_WS_RTRY_LIMIT;
  617. set = FIELD_PREP(BCM54140_RDB_SPARE2_WS_RTRY_LIMIT, cnt - 2);
  618. }
  619. ret = bcm_phy_modify_rdb(phydev, BCM54140_RDB_SPARE2,
  620. mask, set);
  621. if (ret)
  622. return ret;
  623. return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_MISC_CTRL,
  624. 0, BCM54140_RDB_C_MISC_CTRL_WS_EN);
  625. }
  626. static int bcm54140_get_edpd(struct phy_device *phydev, u16 *tx_interval)
  627. {
  628. int val;
  629. val = bcm_phy_read_rdb(phydev, BCM54140_RDB_C_APWR);
  630. if (val < 0)
  631. return val;
  632. switch (FIELD_GET(BCM54140_RDB_C_APWR_APD_MODE_MASK, val)) {
  633. case BCM54140_RDB_C_APWR_APD_MODE_DIS:
  634. case BCM54140_RDB_C_APWR_APD_MODE_DIS2:
  635. *tx_interval = ETHTOOL_PHY_EDPD_DISABLE;
  636. break;
  637. case BCM54140_RDB_C_APWR_APD_MODE_EN:
  638. case BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG:
  639. switch (FIELD_GET(BCM54140_RDB_C_APWR_SLP_TIM_MASK, val)) {
  640. case BCM54140_RDB_C_APWR_SLP_TIM_2_7:
  641. *tx_interval = 2700;
  642. break;
  643. case BCM54140_RDB_C_APWR_SLP_TIM_5_4:
  644. *tx_interval = 5400;
  645. break;
  646. }
  647. }
  648. return 0;
  649. }
  650. static int bcm54140_set_edpd(struct phy_device *phydev, u16 tx_interval)
  651. {
  652. u16 mask, set;
  653. mask = BCM54140_RDB_C_APWR_APD_MODE_MASK;
  654. if (tx_interval == ETHTOOL_PHY_EDPD_DISABLE)
  655. set = FIELD_PREP(BCM54140_RDB_C_APWR_APD_MODE_MASK,
  656. BCM54140_RDB_C_APWR_APD_MODE_DIS);
  657. else
  658. set = FIELD_PREP(BCM54140_RDB_C_APWR_APD_MODE_MASK,
  659. BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG);
  660. /* enable single pulse mode */
  661. set |= BCM54140_RDB_C_APWR_SINGLE_PULSE;
  662. /* set sleep timer */
  663. mask |= BCM54140_RDB_C_APWR_SLP_TIM_MASK;
  664. switch (tx_interval) {
  665. case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS:
  666. case ETHTOOL_PHY_EDPD_DISABLE:
  667. case 2700:
  668. set |= BCM54140_RDB_C_APWR_SLP_TIM_2_7;
  669. break;
  670. case 5400:
  671. set |= BCM54140_RDB_C_APWR_SLP_TIM_5_4;
  672. break;
  673. default:
  674. return -EINVAL;
  675. }
  676. return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_APWR, mask, set);
  677. }
  678. static int bcm54140_get_tunable(struct phy_device *phydev,
  679. struct ethtool_tunable *tuna, void *data)
  680. {
  681. switch (tuna->id) {
  682. case ETHTOOL_PHY_DOWNSHIFT:
  683. return bcm54140_get_downshift(phydev, data);
  684. case ETHTOOL_PHY_EDPD:
  685. return bcm54140_get_edpd(phydev, data);
  686. default:
  687. return -EOPNOTSUPP;
  688. }
  689. }
  690. static int bcm54140_set_tunable(struct phy_device *phydev,
  691. struct ethtool_tunable *tuna, const void *data)
  692. {
  693. switch (tuna->id) {
  694. case ETHTOOL_PHY_DOWNSHIFT:
  695. return bcm54140_set_downshift(phydev, *(const u8 *)data);
  696. case ETHTOOL_PHY_EDPD:
  697. return bcm54140_set_edpd(phydev, *(const u16 *)data);
  698. default:
  699. return -EOPNOTSUPP;
  700. }
  701. }
  702. static struct phy_driver bcm54140_drivers[] = {
  703. {
  704. .phy_id = PHY_ID_BCM54140,
  705. .phy_id_mask = BCM54140_PHY_ID_MASK,
  706. .name = "Broadcom BCM54140",
  707. .flags = PHY_POLL_CABLE_TEST,
  708. .features = PHY_GBIT_FEATURES,
  709. .config_init = bcm54140_config_init,
  710. .did_interrupt = bcm54140_did_interrupt,
  711. .ack_interrupt = bcm54140_ack_intr,
  712. .config_intr = bcm54140_config_intr,
  713. .probe = bcm54140_probe,
  714. .suspend = genphy_suspend,
  715. .resume = genphy_resume,
  716. .soft_reset = genphy_soft_reset,
  717. .get_tunable = bcm54140_get_tunable,
  718. .set_tunable = bcm54140_set_tunable,
  719. .cable_test_start = bcm_phy_cable_test_start_rdb,
  720. .cable_test_get_status = bcm_phy_cable_test_get_status_rdb,
  721. },
  722. };
  723. module_phy_driver(bcm54140_drivers);
  724. static struct mdio_device_id __maybe_unused bcm54140_tbl[] = {
  725. { PHY_ID_BCM54140, BCM54140_PHY_ID_MASK },
  726. { }
  727. };
  728. MODULE_AUTHOR("Michael Walle");
  729. MODULE_DESCRIPTION("Broadcom BCM54140 PHY driver");
  730. MODULE_DEVICE_TABLE(mdio, bcm54140_tbl);
  731. MODULE_LICENSE("GPL");