at803x.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * drivers/net/phy/at803x.c
  4. *
  5. * Driver for Qualcomm Atheros AR803x PHY
  6. *
  7. * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
  8. */
  9. #include <linux/phy.h>
  10. #include <linux/module.h>
  11. #include <linux/string.h>
  12. #include <linux/netdevice.h>
  13. #include <linux/etherdevice.h>
  14. #include <linux/ethtool_netlink.h>
  15. #include <linux/of_gpio.h>
  16. #include <linux/bitfield.h>
  17. #include <linux/gpio/consumer.h>
  18. #include <linux/regulator/of_regulator.h>
  19. #include <linux/regulator/driver.h>
  20. #include <linux/regulator/consumer.h>
  21. #include <dt-bindings/net/qca-ar803x.h>
  22. #define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10
  23. #define AT803X_SFC_ASSERT_CRS BIT(11)
  24. #define AT803X_SFC_FORCE_LINK BIT(10)
  25. #define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5)
  26. #define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3
  27. #define AT803X_SFC_MANUAL_MDIX 0x1
  28. #define AT803X_SFC_MANUAL_MDI 0x0
  29. #define AT803X_SFC_SQE_TEST BIT(2)
  30. #define AT803X_SFC_POLARITY_REVERSAL BIT(1)
  31. #define AT803X_SFC_DISABLE_JABBER BIT(0)
  32. #define AT803X_SPECIFIC_STATUS 0x11
  33. #define AT803X_SS_SPEED_MASK (3 << 14)
  34. #define AT803X_SS_SPEED_1000 (2 << 14)
  35. #define AT803X_SS_SPEED_100 (1 << 14)
  36. #define AT803X_SS_SPEED_10 (0 << 14)
  37. #define AT803X_SS_DUPLEX BIT(13)
  38. #define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11)
  39. #define AT803X_SS_MDIX BIT(6)
  40. #define AT803X_INTR_ENABLE 0x12
  41. #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15)
  42. #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14)
  43. #define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13)
  44. #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12)
  45. #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11)
  46. #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10)
  47. #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5)
  48. #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1)
  49. #define AT803X_INTR_ENABLE_WOL BIT(0)
  50. #define AT803X_INTR_STATUS 0x13
  51. #define AT803X_SMART_SPEED 0x14
  52. #define AT803X_SMART_SPEED_ENABLE BIT(5)
  53. #define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2)
  54. #define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1)
  55. #define AT803X_CDT 0x16
  56. #define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8)
  57. #define AT803X_CDT_ENABLE_TEST BIT(0)
  58. #define AT803X_CDT_STATUS 0x1c
  59. #define AT803X_CDT_STATUS_STAT_NORMAL 0
  60. #define AT803X_CDT_STATUS_STAT_SHORT 1
  61. #define AT803X_CDT_STATUS_STAT_OPEN 2
  62. #define AT803X_CDT_STATUS_STAT_FAIL 3
  63. #define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8)
  64. #define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0)
  65. #define AT803X_LED_CONTROL 0x18
  66. #define AT803X_DEVICE_ADDR 0x03
  67. #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C
  68. #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B
  69. #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A
  70. #define AT803X_REG_CHIP_CONFIG 0x1f
  71. #define AT803X_BT_BX_REG_SEL 0x8000
  72. #define AT803X_DEBUG_ADDR 0x1D
  73. #define AT803X_DEBUG_DATA 0x1E
  74. #define AT803X_MODE_CFG_MASK 0x0F
  75. #define AT803X_MODE_CFG_SGMII 0x01
  76. #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
  77. #define AT803X_PSSR_MR_AN_COMPLETE 0x0200
  78. #define AT803X_DEBUG_REG_0 0x00
  79. #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15)
  80. #define AT803X_DEBUG_REG_5 0x05
  81. #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
  82. #define AT803X_DEBUG_REG_1F 0x1F
  83. #define AT803X_DEBUG_PLL_ON BIT(2)
  84. #define AT803X_DEBUG_RGMII_1V8 BIT(3)
  85. /* AT803x supports either the XTAL input pad, an internal PLL or the
  86. * DSP as clock reference for the clock output pad. The XTAL reference
  87. * is only used for 25 MHz output, all other frequencies need the PLL.
  88. * The DSP as a clock reference is used in synchronous ethernet
  89. * applications.
  90. *
  91. * By default the PLL is only enabled if there is a link. Otherwise
  92. * the PHY will go into low power state and disabled the PLL. You can
  93. * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
  94. * enabled.
  95. */
  96. #define AT803X_MMD7_CLK25M 0x8016
  97. #define AT803X_CLK_OUT_MASK GENMASK(4, 2)
  98. #define AT803X_CLK_OUT_25MHZ_XTAL 0
  99. #define AT803X_CLK_OUT_25MHZ_DSP 1
  100. #define AT803X_CLK_OUT_50MHZ_PLL 2
  101. #define AT803X_CLK_OUT_50MHZ_DSP 3
  102. #define AT803X_CLK_OUT_62_5MHZ_PLL 4
  103. #define AT803X_CLK_OUT_62_5MHZ_DSP 5
  104. #define AT803X_CLK_OUT_125MHZ_PLL 6
  105. #define AT803X_CLK_OUT_125MHZ_DSP 7
  106. /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask
  107. * but doesn't support choosing between XTAL/PLL and DSP.
  108. */
  109. #define AT8035_CLK_OUT_MASK GENMASK(4, 3)
  110. #define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7)
  111. #define AT803X_CLK_OUT_STRENGTH_FULL 0
  112. #define AT803X_CLK_OUT_STRENGTH_HALF 1
  113. #define AT803X_CLK_OUT_STRENGTH_QUARTER 2
  114. #define AT803X_DEFAULT_DOWNSHIFT 5
  115. #define AT803X_MIN_DOWNSHIFT 2
  116. #define AT803X_MAX_DOWNSHIFT 9
  117. #define ATH9331_PHY_ID 0x004dd041
  118. #define ATH8030_PHY_ID 0x004dd076
  119. #define ATH8031_PHY_ID 0x004dd074
  120. #define ATH8032_PHY_ID 0x004dd023
  121. #define ATH8035_PHY_ID 0x004dd072
  122. #define AT8030_PHY_ID_MASK 0xffffffef
  123. MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver");
  124. MODULE_AUTHOR("Matus Ujhelyi");
  125. MODULE_LICENSE("GPL");
  126. struct at803x_priv {
  127. int flags;
  128. #define AT803X_KEEP_PLL_ENABLED BIT(0) /* don't turn off internal PLL */
  129. u16 clk_25m_reg;
  130. u16 clk_25m_mask;
  131. struct regulator_dev *vddio_rdev;
  132. struct regulator_dev *vddh_rdev;
  133. struct regulator *vddio;
  134. };
  135. struct at803x_context {
  136. u16 bmcr;
  137. u16 advertise;
  138. u16 control1000;
  139. u16 int_enable;
  140. u16 smart_speed;
  141. u16 led_control;
  142. };
  143. static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
  144. {
  145. int ret;
  146. ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
  147. if (ret < 0)
  148. return ret;
  149. return phy_read(phydev, AT803X_DEBUG_DATA);
  150. }
  151. static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
  152. u16 clear, u16 set)
  153. {
  154. u16 val;
  155. int ret;
  156. ret = at803x_debug_reg_read(phydev, reg);
  157. if (ret < 0)
  158. return ret;
  159. val = ret & 0xffff;
  160. val &= ~clear;
  161. val |= set;
  162. return phy_write(phydev, AT803X_DEBUG_DATA, val);
  163. }
  164. static int at803x_enable_rx_delay(struct phy_device *phydev)
  165. {
  166. return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,
  167. AT803X_DEBUG_RX_CLK_DLY_EN);
  168. }
  169. static int at803x_enable_tx_delay(struct phy_device *phydev)
  170. {
  171. return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,
  172. AT803X_DEBUG_TX_CLK_DLY_EN);
  173. }
  174. static int at803x_disable_rx_delay(struct phy_device *phydev)
  175. {
  176. return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,
  177. AT803X_DEBUG_RX_CLK_DLY_EN, 0);
  178. }
  179. static int at803x_disable_tx_delay(struct phy_device *phydev)
  180. {
  181. return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5,
  182. AT803X_DEBUG_TX_CLK_DLY_EN, 0);
  183. }
  184. /* save relevant PHY registers to private copy */
  185. static void at803x_context_save(struct phy_device *phydev,
  186. struct at803x_context *context)
  187. {
  188. context->bmcr = phy_read(phydev, MII_BMCR);
  189. context->advertise = phy_read(phydev, MII_ADVERTISE);
  190. context->control1000 = phy_read(phydev, MII_CTRL1000);
  191. context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
  192. context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
  193. context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
  194. }
  195. /* restore relevant PHY registers from private copy */
  196. static void at803x_context_restore(struct phy_device *phydev,
  197. const struct at803x_context *context)
  198. {
  199. phy_write(phydev, MII_BMCR, context->bmcr);
  200. phy_write(phydev, MII_ADVERTISE, context->advertise);
  201. phy_write(phydev, MII_CTRL1000, context->control1000);
  202. phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
  203. phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
  204. phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
  205. }
  206. static int at803x_set_wol(struct phy_device *phydev,
  207. struct ethtool_wolinfo *wol)
  208. {
  209. struct net_device *ndev = phydev->attached_dev;
  210. const u8 *mac;
  211. int ret;
  212. u32 value;
  213. unsigned int i, offsets[] = {
  214. AT803X_LOC_MAC_ADDR_32_47_OFFSET,
  215. AT803X_LOC_MAC_ADDR_16_31_OFFSET,
  216. AT803X_LOC_MAC_ADDR_0_15_OFFSET,
  217. };
  218. if (!ndev)
  219. return -ENODEV;
  220. if (wol->wolopts & WAKE_MAGIC) {
  221. mac = (const u8 *) ndev->dev_addr;
  222. if (!is_valid_ether_addr(mac))
  223. return -EINVAL;
  224. for (i = 0; i < 3; i++)
  225. phy_write_mmd(phydev, AT803X_DEVICE_ADDR, offsets[i],
  226. mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
  227. value = phy_read(phydev, AT803X_INTR_ENABLE);
  228. value |= AT803X_INTR_ENABLE_WOL;
  229. ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
  230. if (ret)
  231. return ret;
  232. value = phy_read(phydev, AT803X_INTR_STATUS);
  233. } else {
  234. value = phy_read(phydev, AT803X_INTR_ENABLE);
  235. value &= (~AT803X_INTR_ENABLE_WOL);
  236. ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
  237. if (ret)
  238. return ret;
  239. value = phy_read(phydev, AT803X_INTR_STATUS);
  240. }
  241. return ret;
  242. }
  243. static void at803x_get_wol(struct phy_device *phydev,
  244. struct ethtool_wolinfo *wol)
  245. {
  246. u32 value;
  247. wol->supported = WAKE_MAGIC;
  248. wol->wolopts = 0;
  249. value = phy_read(phydev, AT803X_INTR_ENABLE);
  250. if (value & AT803X_INTR_ENABLE_WOL)
  251. wol->wolopts |= WAKE_MAGIC;
  252. }
  253. static int at803x_suspend(struct phy_device *phydev)
  254. {
  255. int value;
  256. int wol_enabled;
  257. value = phy_read(phydev, AT803X_INTR_ENABLE);
  258. wol_enabled = value & AT803X_INTR_ENABLE_WOL;
  259. if (wol_enabled)
  260. value = BMCR_ISOLATE;
  261. else
  262. value = BMCR_PDOWN;
  263. phy_modify(phydev, MII_BMCR, 0, value);
  264. return 0;
  265. }
  266. static int at803x_resume(struct phy_device *phydev)
  267. {
  268. return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0);
  269. }
  270. static int at803x_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev,
  271. unsigned int selector)
  272. {
  273. struct phy_device *phydev = rdev_get_drvdata(rdev);
  274. if (selector)
  275. return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
  276. 0, AT803X_DEBUG_RGMII_1V8);
  277. else
  278. return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
  279. AT803X_DEBUG_RGMII_1V8, 0);
  280. }
  281. static int at803x_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev)
  282. {
  283. struct phy_device *phydev = rdev_get_drvdata(rdev);
  284. int val;
  285. val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F);
  286. if (val < 0)
  287. return val;
  288. return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0;
  289. }
  290. static const struct regulator_ops vddio_regulator_ops = {
  291. .list_voltage = regulator_list_voltage_table,
  292. .set_voltage_sel = at803x_rgmii_reg_set_voltage_sel,
  293. .get_voltage_sel = at803x_rgmii_reg_get_voltage_sel,
  294. };
  295. static const unsigned int vddio_voltage_table[] = {
  296. 1500000,
  297. 1800000,
  298. };
  299. static const struct regulator_desc vddio_desc = {
  300. .name = "vddio",
  301. .of_match = of_match_ptr("vddio-regulator"),
  302. .n_voltages = ARRAY_SIZE(vddio_voltage_table),
  303. .volt_table = vddio_voltage_table,
  304. .ops = &vddio_regulator_ops,
  305. .type = REGULATOR_VOLTAGE,
  306. .owner = THIS_MODULE,
  307. };
  308. static const struct regulator_ops vddh_regulator_ops = {
  309. };
  310. static const struct regulator_desc vddh_desc = {
  311. .name = "vddh",
  312. .of_match = of_match_ptr("vddh-regulator"),
  313. .n_voltages = 1,
  314. .fixed_uV = 2500000,
  315. .ops = &vddh_regulator_ops,
  316. .type = REGULATOR_VOLTAGE,
  317. .owner = THIS_MODULE,
  318. };
  319. static int at8031_register_regulators(struct phy_device *phydev)
  320. {
  321. struct at803x_priv *priv = phydev->priv;
  322. struct device *dev = &phydev->mdio.dev;
  323. struct regulator_config config = { };
  324. config.dev = dev;
  325. config.driver_data = phydev;
  326. priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config);
  327. if (IS_ERR(priv->vddio_rdev)) {
  328. phydev_err(phydev, "failed to register VDDIO regulator\n");
  329. return PTR_ERR(priv->vddio_rdev);
  330. }
  331. priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config);
  332. if (IS_ERR(priv->vddh_rdev)) {
  333. phydev_err(phydev, "failed to register VDDH regulator\n");
  334. return PTR_ERR(priv->vddh_rdev);
  335. }
  336. return 0;
  337. }
  338. static bool at803x_match_phy_id(struct phy_device *phydev, u32 phy_id)
  339. {
  340. return (phydev->phy_id & phydev->drv->phy_id_mask)
  341. == (phy_id & phydev->drv->phy_id_mask);
  342. }
  343. static int at803x_parse_dt(struct phy_device *phydev)
  344. {
  345. struct device_node *node = phydev->mdio.dev.of_node;
  346. struct at803x_priv *priv = phydev->priv;
  347. u32 freq, strength;
  348. unsigned int sel;
  349. int ret;
  350. if (!IS_ENABLED(CONFIG_OF_MDIO))
  351. return 0;
  352. ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq);
  353. if (!ret) {
  354. switch (freq) {
  355. case 25000000:
  356. sel = AT803X_CLK_OUT_25MHZ_XTAL;
  357. break;
  358. case 50000000:
  359. sel = AT803X_CLK_OUT_50MHZ_PLL;
  360. break;
  361. case 62500000:
  362. sel = AT803X_CLK_OUT_62_5MHZ_PLL;
  363. break;
  364. case 125000000:
  365. sel = AT803X_CLK_OUT_125MHZ_PLL;
  366. break;
  367. default:
  368. phydev_err(phydev, "invalid qca,clk-out-frequency\n");
  369. return -EINVAL;
  370. }
  371. priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel);
  372. priv->clk_25m_mask |= AT803X_CLK_OUT_MASK;
  373. /* Fixup for the AR8030/AR8035. This chip has another mask and
  374. * doesn't support the DSP reference. Eg. the lowest bit of the
  375. * mask. The upper two bits select the same frequencies. Mask
  376. * the lowest bit here.
  377. *
  378. * Warning:
  379. * There was no datasheet for the AR8030 available so this is
  380. * just a guess. But the AR8035 is listed as pin compatible
  381. * to the AR8030 so there might be a good chance it works on
  382. * the AR8030 too.
  383. */
  384. if (at803x_match_phy_id(phydev, ATH8030_PHY_ID) ||
  385. at803x_match_phy_id(phydev, ATH8035_PHY_ID)) {
  386. priv->clk_25m_reg &= AT8035_CLK_OUT_MASK;
  387. priv->clk_25m_mask &= AT8035_CLK_OUT_MASK;
  388. }
  389. }
  390. ret = of_property_read_u32(node, "qca,clk-out-strength", &strength);
  391. if (!ret) {
  392. priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK;
  393. switch (strength) {
  394. case AR803X_STRENGTH_FULL:
  395. priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL;
  396. break;
  397. case AR803X_STRENGTH_HALF:
  398. priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF;
  399. break;
  400. case AR803X_STRENGTH_QUARTER:
  401. priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER;
  402. break;
  403. default:
  404. phydev_err(phydev, "invalid qca,clk-out-strength\n");
  405. return -EINVAL;
  406. }
  407. }
  408. /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping
  409. * options.
  410. */
  411. if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) {
  412. if (of_property_read_bool(node, "qca,keep-pll-enabled"))
  413. priv->flags |= AT803X_KEEP_PLL_ENABLED;
  414. ret = at8031_register_regulators(phydev);
  415. if (ret < 0)
  416. return ret;
  417. priv->vddio = devm_regulator_get_optional(&phydev->mdio.dev,
  418. "vddio");
  419. if (IS_ERR(priv->vddio)) {
  420. phydev_err(phydev, "failed to get VDDIO regulator\n");
  421. return PTR_ERR(priv->vddio);
  422. }
  423. ret = regulator_enable(priv->vddio);
  424. if (ret < 0)
  425. return ret;
  426. }
  427. return 0;
  428. }
  429. static int at803x_probe(struct phy_device *phydev)
  430. {
  431. struct device *dev = &phydev->mdio.dev;
  432. struct at803x_priv *priv;
  433. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  434. if (!priv)
  435. return -ENOMEM;
  436. phydev->priv = priv;
  437. return at803x_parse_dt(phydev);
  438. }
  439. static void at803x_remove(struct phy_device *phydev)
  440. {
  441. struct at803x_priv *priv = phydev->priv;
  442. if (priv->vddio)
  443. regulator_disable(priv->vddio);
  444. }
  445. static int at803x_clk_out_config(struct phy_device *phydev)
  446. {
  447. struct at803x_priv *priv = phydev->priv;
  448. int val;
  449. if (!priv->clk_25m_mask)
  450. return 0;
  451. val = phy_read_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M);
  452. if (val < 0)
  453. return val;
  454. val &= ~priv->clk_25m_mask;
  455. val |= priv->clk_25m_reg;
  456. return phy_write_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M, val);
  457. }
  458. static int at8031_pll_config(struct phy_device *phydev)
  459. {
  460. struct at803x_priv *priv = phydev->priv;
  461. /* The default after hardware reset is PLL OFF. After a soft reset, the
  462. * values are retained.
  463. */
  464. if (priv->flags & AT803X_KEEP_PLL_ENABLED)
  465. return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
  466. 0, AT803X_DEBUG_PLL_ON);
  467. else
  468. return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
  469. AT803X_DEBUG_PLL_ON, 0);
  470. }
  471. static int at803x_config_init(struct phy_device *phydev)
  472. {
  473. int ret;
  474. /* The RX and TX delay default is:
  475. * after HW reset: RX delay enabled and TX delay disabled
  476. * after SW reset: RX delay enabled, while TX delay retains the
  477. * value before reset.
  478. */
  479. if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
  480. phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
  481. ret = at803x_enable_rx_delay(phydev);
  482. else
  483. ret = at803x_disable_rx_delay(phydev);
  484. if (ret < 0)
  485. return ret;
  486. if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
  487. phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
  488. ret = at803x_enable_tx_delay(phydev);
  489. else
  490. ret = at803x_disable_tx_delay(phydev);
  491. if (ret < 0)
  492. return ret;
  493. ret = at803x_clk_out_config(phydev);
  494. if (ret < 0)
  495. return ret;
  496. if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) {
  497. ret = at8031_pll_config(phydev);
  498. if (ret < 0)
  499. return ret;
  500. }
  501. return 0;
  502. }
  503. static int at803x_ack_interrupt(struct phy_device *phydev)
  504. {
  505. int err;
  506. err = phy_read(phydev, AT803X_INTR_STATUS);
  507. return (err < 0) ? err : 0;
  508. }
  509. static int at803x_config_intr(struct phy_device *phydev)
  510. {
  511. int err;
  512. int value;
  513. value = phy_read(phydev, AT803X_INTR_ENABLE);
  514. if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
  515. value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
  516. value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
  517. value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
  518. value |= AT803X_INTR_ENABLE_LINK_FAIL;
  519. value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
  520. err = phy_write(phydev, AT803X_INTR_ENABLE, value);
  521. }
  522. else
  523. err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
  524. return err;
  525. }
  526. static void at803x_link_change_notify(struct phy_device *phydev)
  527. {
  528. /*
  529. * Conduct a hardware reset for AT8030 every time a link loss is
  530. * signalled. This is necessary to circumvent a hardware bug that
  531. * occurs when the cable is unplugged while TX packets are pending
  532. * in the FIFO. In such cases, the FIFO enters an error mode it
  533. * cannot recover from by software.
  534. */
  535. if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) {
  536. struct at803x_context context;
  537. at803x_context_save(phydev, &context);
  538. phy_device_reset(phydev, 1);
  539. msleep(1);
  540. phy_device_reset(phydev, 0);
  541. msleep(1);
  542. at803x_context_restore(phydev, &context);
  543. phydev_dbg(phydev, "%s(): phy was reset\n", __func__);
  544. }
  545. }
  546. static int at803x_aneg_done(struct phy_device *phydev)
  547. {
  548. int ccr;
  549. int aneg_done = genphy_aneg_done(phydev);
  550. if (aneg_done != BMSR_ANEGCOMPLETE)
  551. return aneg_done;
  552. /*
  553. * in SGMII mode, if copper side autoneg is successful,
  554. * also check SGMII side autoneg result
  555. */
  556. ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
  557. if ((ccr & AT803X_MODE_CFG_MASK) != AT803X_MODE_CFG_SGMII)
  558. return aneg_done;
  559. /* switch to SGMII/fiber page */
  560. phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr & ~AT803X_BT_BX_REG_SEL);
  561. /* check if the SGMII link is OK. */
  562. if (!(phy_read(phydev, AT803X_PSSR) & AT803X_PSSR_MR_AN_COMPLETE)) {
  563. phydev_warn(phydev, "803x_aneg_done: SGMII link is not ok\n");
  564. aneg_done = 0;
  565. }
  566. /* switch back to copper page */
  567. phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr | AT803X_BT_BX_REG_SEL);
  568. return aneg_done;
  569. }
  570. static int at803x_read_status(struct phy_device *phydev)
  571. {
  572. int ss, err, old_link = phydev->link;
  573. /* Update the link, but return if there was an error */
  574. err = genphy_update_link(phydev);
  575. if (err)
  576. return err;
  577. /* why bother the PHY if nothing can have changed */
  578. if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
  579. return 0;
  580. phydev->speed = SPEED_UNKNOWN;
  581. phydev->duplex = DUPLEX_UNKNOWN;
  582. phydev->pause = 0;
  583. phydev->asym_pause = 0;
  584. err = genphy_read_lpa(phydev);
  585. if (err < 0)
  586. return err;
  587. /* Read the AT8035 PHY-Specific Status register, which indicates the
  588. * speed and duplex that the PHY is actually using, irrespective of
  589. * whether we are in autoneg mode or not.
  590. */
  591. ss = phy_read(phydev, AT803X_SPECIFIC_STATUS);
  592. if (ss < 0)
  593. return ss;
  594. if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) {
  595. int sfc;
  596. sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL);
  597. if (sfc < 0)
  598. return sfc;
  599. switch (ss & AT803X_SS_SPEED_MASK) {
  600. case AT803X_SS_SPEED_10:
  601. phydev->speed = SPEED_10;
  602. break;
  603. case AT803X_SS_SPEED_100:
  604. phydev->speed = SPEED_100;
  605. break;
  606. case AT803X_SS_SPEED_1000:
  607. phydev->speed = SPEED_1000;
  608. break;
  609. }
  610. if (ss & AT803X_SS_DUPLEX)
  611. phydev->duplex = DUPLEX_FULL;
  612. else
  613. phydev->duplex = DUPLEX_HALF;
  614. if (ss & AT803X_SS_MDIX)
  615. phydev->mdix = ETH_TP_MDI_X;
  616. else
  617. phydev->mdix = ETH_TP_MDI;
  618. switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) {
  619. case AT803X_SFC_MANUAL_MDI:
  620. phydev->mdix_ctrl = ETH_TP_MDI;
  621. break;
  622. case AT803X_SFC_MANUAL_MDIX:
  623. phydev->mdix_ctrl = ETH_TP_MDI_X;
  624. break;
  625. case AT803X_SFC_AUTOMATIC_CROSSOVER:
  626. phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
  627. break;
  628. }
  629. }
  630. if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
  631. phy_resolve_aneg_pause(phydev);
  632. return 0;
  633. }
  634. static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl)
  635. {
  636. u16 val;
  637. switch (ctrl) {
  638. case ETH_TP_MDI:
  639. val = AT803X_SFC_MANUAL_MDI;
  640. break;
  641. case ETH_TP_MDI_X:
  642. val = AT803X_SFC_MANUAL_MDIX;
  643. break;
  644. case ETH_TP_MDI_AUTO:
  645. val = AT803X_SFC_AUTOMATIC_CROSSOVER;
  646. break;
  647. default:
  648. return 0;
  649. }
  650. return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL,
  651. AT803X_SFC_MDI_CROSSOVER_MODE_M,
  652. FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val));
  653. }
  654. static int at803x_config_aneg(struct phy_device *phydev)
  655. {
  656. int ret;
  657. ret = at803x_config_mdix(phydev, phydev->mdix_ctrl);
  658. if (ret < 0)
  659. return ret;
  660. /* Changes of the midx bits are disruptive to the normal operation;
  661. * therefore any changes to these registers must be followed by a
  662. * software reset to take effect.
  663. */
  664. if (ret == 1) {
  665. ret = genphy_soft_reset(phydev);
  666. if (ret < 0)
  667. return ret;
  668. }
  669. return genphy_config_aneg(phydev);
  670. }
  671. static int at803x_get_downshift(struct phy_device *phydev, u8 *d)
  672. {
  673. int val;
  674. val = phy_read(phydev, AT803X_SMART_SPEED);
  675. if (val < 0)
  676. return val;
  677. if (val & AT803X_SMART_SPEED_ENABLE)
  678. *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2;
  679. else
  680. *d = DOWNSHIFT_DEV_DISABLE;
  681. return 0;
  682. }
  683. static int at803x_set_downshift(struct phy_device *phydev, u8 cnt)
  684. {
  685. u16 mask, set;
  686. int ret;
  687. switch (cnt) {
  688. case DOWNSHIFT_DEV_DEFAULT_COUNT:
  689. cnt = AT803X_DEFAULT_DOWNSHIFT;
  690. fallthrough;
  691. case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT:
  692. set = AT803X_SMART_SPEED_ENABLE |
  693. AT803X_SMART_SPEED_BYPASS_TIMER |
  694. FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2);
  695. mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK;
  696. break;
  697. case DOWNSHIFT_DEV_DISABLE:
  698. set = 0;
  699. mask = AT803X_SMART_SPEED_ENABLE |
  700. AT803X_SMART_SPEED_BYPASS_TIMER;
  701. break;
  702. default:
  703. return -EINVAL;
  704. }
  705. ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set);
  706. /* After changing the smart speed settings, we need to perform a
  707. * software reset, use phy_init_hw() to make sure we set the
  708. * reapply any values which might got lost during software reset.
  709. */
  710. if (ret == 1)
  711. ret = phy_init_hw(phydev);
  712. return ret;
  713. }
  714. static int at803x_get_tunable(struct phy_device *phydev,
  715. struct ethtool_tunable *tuna, void *data)
  716. {
  717. switch (tuna->id) {
  718. case ETHTOOL_PHY_DOWNSHIFT:
  719. return at803x_get_downshift(phydev, data);
  720. default:
  721. return -EOPNOTSUPP;
  722. }
  723. }
  724. static int at803x_set_tunable(struct phy_device *phydev,
  725. struct ethtool_tunable *tuna, const void *data)
  726. {
  727. switch (tuna->id) {
  728. case ETHTOOL_PHY_DOWNSHIFT:
  729. return at803x_set_downshift(phydev, *(const u8 *)data);
  730. default:
  731. return -EOPNOTSUPP;
  732. }
  733. }
  734. static int at803x_cable_test_result_trans(u16 status)
  735. {
  736. switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
  737. case AT803X_CDT_STATUS_STAT_NORMAL:
  738. return ETHTOOL_A_CABLE_RESULT_CODE_OK;
  739. case AT803X_CDT_STATUS_STAT_SHORT:
  740. return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
  741. case AT803X_CDT_STATUS_STAT_OPEN:
  742. return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
  743. case AT803X_CDT_STATUS_STAT_FAIL:
  744. default:
  745. return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
  746. }
  747. }
  748. static bool at803x_cdt_test_failed(u16 status)
  749. {
  750. return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) ==
  751. AT803X_CDT_STATUS_STAT_FAIL;
  752. }
  753. static bool at803x_cdt_fault_length_valid(u16 status)
  754. {
  755. switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
  756. case AT803X_CDT_STATUS_STAT_OPEN:
  757. case AT803X_CDT_STATUS_STAT_SHORT:
  758. return true;
  759. }
  760. return false;
  761. }
  762. static int at803x_cdt_fault_length(u16 status)
  763. {
  764. int dt;
  765. /* According to the datasheet the distance to the fault is
  766. * DELTA_TIME * 0.824 meters.
  767. *
  768. * The author suspect the correct formula is:
  769. *
  770. * fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2
  771. *
  772. * where c is the speed of light, VF is the velocity factor of
  773. * the twisted pair cable, 125MHz the counter frequency and
  774. * we need to divide by 2 because the hardware will measure the
  775. * round trip time to the fault and back to the PHY.
  776. *
  777. * With a VF of 0.69 we get the factor 0.824 mentioned in the
  778. * datasheet.
  779. */
  780. dt = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, status);
  781. return (dt * 824) / 10;
  782. }
  783. static int at803x_cdt_start(struct phy_device *phydev, int pair)
  784. {
  785. u16 cdt;
  786. cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) |
  787. AT803X_CDT_ENABLE_TEST;
  788. return phy_write(phydev, AT803X_CDT, cdt);
  789. }
  790. static int at803x_cdt_wait_for_completion(struct phy_device *phydev)
  791. {
  792. int val, ret;
  793. /* One test run takes about 25ms */
  794. ret = phy_read_poll_timeout(phydev, AT803X_CDT, val,
  795. !(val & AT803X_CDT_ENABLE_TEST),
  796. 30000, 100000, true);
  797. return ret < 0 ? ret : 0;
  798. }
  799. static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair)
  800. {
  801. static const int ethtool_pair[] = {
  802. ETHTOOL_A_CABLE_PAIR_A,
  803. ETHTOOL_A_CABLE_PAIR_B,
  804. ETHTOOL_A_CABLE_PAIR_C,
  805. ETHTOOL_A_CABLE_PAIR_D,
  806. };
  807. int ret, val;
  808. ret = at803x_cdt_start(phydev, pair);
  809. if (ret)
  810. return ret;
  811. ret = at803x_cdt_wait_for_completion(phydev);
  812. if (ret)
  813. return ret;
  814. val = phy_read(phydev, AT803X_CDT_STATUS);
  815. if (val < 0)
  816. return val;
  817. if (at803x_cdt_test_failed(val))
  818. return 0;
  819. ethnl_cable_test_result(phydev, ethtool_pair[pair],
  820. at803x_cable_test_result_trans(val));
  821. if (at803x_cdt_fault_length_valid(val))
  822. ethnl_cable_test_fault_length(phydev, ethtool_pair[pair],
  823. at803x_cdt_fault_length(val));
  824. return 1;
  825. }
  826. static int at803x_cable_test_get_status(struct phy_device *phydev,
  827. bool *finished)
  828. {
  829. unsigned long pair_mask;
  830. int retries = 20;
  831. int pair, ret;
  832. if (phydev->phy_id == ATH9331_PHY_ID ||
  833. phydev->phy_id == ATH8032_PHY_ID)
  834. pair_mask = 0x3;
  835. else
  836. pair_mask = 0xf;
  837. *finished = false;
  838. /* According to the datasheet the CDT can be performed when
  839. * there is no link partner or when the link partner is
  840. * auto-negotiating. Starting the test will restart the AN
  841. * automatically. It seems that doing this repeatedly we will
  842. * get a slot where our link partner won't disturb our
  843. * measurement.
  844. */
  845. while (pair_mask && retries--) {
  846. for_each_set_bit(pair, &pair_mask, 4) {
  847. ret = at803x_cable_test_one_pair(phydev, pair);
  848. if (ret < 0)
  849. return ret;
  850. if (ret)
  851. clear_bit(pair, &pair_mask);
  852. }
  853. if (pair_mask)
  854. msleep(250);
  855. }
  856. *finished = true;
  857. return 0;
  858. }
  859. static int at803x_cable_test_start(struct phy_device *phydev)
  860. {
  861. /* Enable auto-negotiation, but advertise no capabilities, no link
  862. * will be established. A restart of the auto-negotiation is not
  863. * required, because the cable test will automatically break the link.
  864. */
  865. phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
  866. phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);
  867. if (phydev->phy_id != ATH9331_PHY_ID &&
  868. phydev->phy_id != ATH8032_PHY_ID)
  869. phy_write(phydev, MII_CTRL1000, 0);
  870. /* we do all the (time consuming) work later */
  871. return 0;
  872. }
  873. static struct phy_driver at803x_driver[] = {
  874. {
  875. /* Qualcomm Atheros AR8035 */
  876. PHY_ID_MATCH_EXACT(ATH8035_PHY_ID),
  877. .name = "Qualcomm Atheros AR8035",
  878. .flags = PHY_POLL_CABLE_TEST,
  879. .probe = at803x_probe,
  880. .remove = at803x_remove,
  881. .config_aneg = at803x_config_aneg,
  882. .config_init = at803x_config_init,
  883. .soft_reset = genphy_soft_reset,
  884. .set_wol = at803x_set_wol,
  885. .get_wol = at803x_get_wol,
  886. .suspend = at803x_suspend,
  887. .resume = at803x_resume,
  888. /* PHY_GBIT_FEATURES */
  889. .read_status = at803x_read_status,
  890. .ack_interrupt = at803x_ack_interrupt,
  891. .config_intr = at803x_config_intr,
  892. .get_tunable = at803x_get_tunable,
  893. .set_tunable = at803x_set_tunable,
  894. .cable_test_start = at803x_cable_test_start,
  895. .cable_test_get_status = at803x_cable_test_get_status,
  896. }, {
  897. /* Qualcomm Atheros AR8030 */
  898. .phy_id = ATH8030_PHY_ID,
  899. .name = "Qualcomm Atheros AR8030",
  900. .phy_id_mask = AT8030_PHY_ID_MASK,
  901. .probe = at803x_probe,
  902. .remove = at803x_remove,
  903. .config_init = at803x_config_init,
  904. .link_change_notify = at803x_link_change_notify,
  905. .set_wol = at803x_set_wol,
  906. .get_wol = at803x_get_wol,
  907. .suspend = at803x_suspend,
  908. .resume = at803x_resume,
  909. /* PHY_BASIC_FEATURES */
  910. .ack_interrupt = at803x_ack_interrupt,
  911. .config_intr = at803x_config_intr,
  912. }, {
  913. /* Qualcomm Atheros AR8031/AR8033 */
  914. PHY_ID_MATCH_EXACT(ATH8031_PHY_ID),
  915. .name = "Qualcomm Atheros AR8031/AR8033",
  916. .flags = PHY_POLL_CABLE_TEST,
  917. .probe = at803x_probe,
  918. .remove = at803x_remove,
  919. .config_init = at803x_config_init,
  920. .soft_reset = genphy_soft_reset,
  921. .set_wol = at803x_set_wol,
  922. .get_wol = at803x_get_wol,
  923. .suspend = at803x_suspend,
  924. .resume = at803x_resume,
  925. /* PHY_GBIT_FEATURES */
  926. .read_status = at803x_read_status,
  927. .aneg_done = at803x_aneg_done,
  928. .ack_interrupt = &at803x_ack_interrupt,
  929. .config_intr = &at803x_config_intr,
  930. .get_tunable = at803x_get_tunable,
  931. .set_tunable = at803x_set_tunable,
  932. .cable_test_start = at803x_cable_test_start,
  933. .cable_test_get_status = at803x_cable_test_get_status,
  934. }, {
  935. /* Qualcomm Atheros AR8032 */
  936. PHY_ID_MATCH_EXACT(ATH8032_PHY_ID),
  937. .name = "Qualcomm Atheros AR8032",
  938. .probe = at803x_probe,
  939. .remove = at803x_remove,
  940. .flags = PHY_POLL_CABLE_TEST,
  941. .config_init = at803x_config_init,
  942. .link_change_notify = at803x_link_change_notify,
  943. .set_wol = at803x_set_wol,
  944. .get_wol = at803x_get_wol,
  945. .suspend = at803x_suspend,
  946. .resume = at803x_resume,
  947. /* PHY_BASIC_FEATURES */
  948. .ack_interrupt = at803x_ack_interrupt,
  949. .config_intr = at803x_config_intr,
  950. .cable_test_start = at803x_cable_test_start,
  951. .cable_test_get_status = at803x_cable_test_get_status,
  952. }, {
  953. /* ATHEROS AR9331 */
  954. PHY_ID_MATCH_EXACT(ATH9331_PHY_ID),
  955. .name = "Qualcomm Atheros AR9331 built-in PHY",
  956. .suspend = at803x_suspend,
  957. .resume = at803x_resume,
  958. .flags = PHY_POLL_CABLE_TEST,
  959. /* PHY_BASIC_FEATURES */
  960. .ack_interrupt = &at803x_ack_interrupt,
  961. .config_intr = &at803x_config_intr,
  962. .cable_test_start = at803x_cable_test_start,
  963. .cable_test_get_status = at803x_cable_test_get_status,
  964. .read_status = at803x_read_status,
  965. .soft_reset = genphy_soft_reset,
  966. .config_aneg = at803x_config_aneg,
  967. } };
  968. module_phy_driver(at803x_driver);
  969. static struct mdio_device_id __maybe_unused atheros_tbl[] = {
  970. { ATH8030_PHY_ID, AT8030_PHY_ID_MASK },
  971. { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) },
  972. { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },
  973. { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
  974. { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
  975. { }
  976. };
  977. MODULE_DEVICE_TABLE(mdio, atheros_tbl);