irq-riscv-intc.c 3.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2012 Regents of the University of California
  4. * Copyright (C) 2017-2018 SiFive
  5. * Copyright (C) 2020 Western Digital Corporation or its affiliates.
  6. */
  7. #define pr_fmt(fmt) "riscv-intc: " fmt
  8. #include <linux/atomic.h>
  9. #include <linux/bits.h>
  10. #include <linux/cpu.h>
  11. #include <linux/irq.h>
  12. #include <linux/irqchip.h>
  13. #include <linux/irqdomain.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/module.h>
  16. #include <linux/of.h>
  17. #include <linux/smp.h>
  18. static struct irq_domain *intc_domain;
  19. static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
  20. {
  21. unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;
  22. unsigned long epc = instruction_pointer(regs);
  23. u32 insn;
  24. #define MATCH_LR_W 0x1000202f
  25. #define MASK_LR_W 0xf9f0707f
  26. #define MATCH_DCACHE_CVAL1 0x0240000b
  27. #define MASK_DCACHE_CVAL1 0xfff07fff
  28. pagefault_disable();
  29. if ((epc & 0x7f) != 4)
  30. goto out;
  31. if (__get_user(insn, (u32 *)epc))
  32. goto out;
  33. if ((insn & MASK_LR_W) != MATCH_LR_W)
  34. goto out;
  35. if (__get_user(insn, (u32 *)(epc - 4)))
  36. goto out;
  37. if ((insn & MASK_DCACHE_CVAL1) != MATCH_DCACHE_CVAL1)
  38. goto out;
  39. instruction_pointer_set(regs, epc - 4);
  40. out:
  41. pagefault_enable();
  42. if (unlikely(cause >= BITS_PER_LONG))
  43. panic("unexpected interrupt cause");
  44. switch (cause) {
  45. #ifdef CONFIG_SMP
  46. case RV_IRQ_SOFT:
  47. /*
  48. * We only use software interrupts to pass IPIs, so if a
  49. * non-SMP system gets one, then we don't know what to do.
  50. */
  51. handle_IPI(regs);
  52. break;
  53. #endif
  54. default:
  55. handle_domain_irq(intc_domain, cause, regs);
  56. break;
  57. }
  58. }
  59. /*
  60. * On RISC-V systems local interrupts are masked or unmasked by writing
  61. * the SIE (Supervisor Interrupt Enable) CSR. As CSRs can only be written
  62. * on the local hart, these functions can only be called on the hart that
  63. * corresponds to the IRQ chip.
  64. */
  65. static void riscv_intc_irq_mask(struct irq_data *d)
  66. {
  67. csr_clear(CSR_IE, BIT(d->hwirq));
  68. }
  69. static void riscv_intc_irq_unmask(struct irq_data *d)
  70. {
  71. csr_set(CSR_IE, BIT(d->hwirq));
  72. }
  73. static int riscv_intc_cpu_starting(unsigned int cpu)
  74. {
  75. csr_set(CSR_IE, BIT(RV_IRQ_SOFT));
  76. return 0;
  77. }
  78. static int riscv_intc_cpu_dying(unsigned int cpu)
  79. {
  80. csr_clear(CSR_IE, BIT(RV_IRQ_SOFT));
  81. return 0;
  82. }
  83. static struct irq_chip riscv_intc_chip = {
  84. .name = "RISC-V INTC",
  85. .irq_mask = riscv_intc_irq_mask,
  86. .irq_unmask = riscv_intc_irq_unmask,
  87. };
  88. static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq,
  89. irq_hw_number_t hwirq)
  90. {
  91. irq_set_percpu_devid(irq);
  92. irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data,
  93. handle_percpu_devid_irq, NULL, NULL);
  94. return 0;
  95. }
  96. static const struct irq_domain_ops riscv_intc_domain_ops = {
  97. .map = riscv_intc_domain_map,
  98. .xlate = irq_domain_xlate_onecell,
  99. };
  100. static int __init riscv_intc_init(struct device_node *node,
  101. struct device_node *parent)
  102. {
  103. int rc, hartid;
  104. hartid = riscv_of_parent_hartid(node);
  105. if (hartid < 0) {
  106. pr_warn("unable to find hart id for %pOF\n", node);
  107. return 0;
  108. }
  109. /*
  110. * The DT will have one INTC DT node under each CPU (or HART)
  111. * DT node so riscv_intc_init() function will be called once
  112. * for each INTC DT node. We only need to do INTC initialization
  113. * for the INTC DT node belonging to boot CPU (or boot HART).
  114. */
  115. if (riscv_hartid_to_cpuid(hartid) != smp_processor_id())
  116. return 0;
  117. intc_domain = irq_domain_add_linear(node, BITS_PER_LONG,
  118. &riscv_intc_domain_ops, NULL);
  119. if (!intc_domain) {
  120. pr_err("unable to add IRQ domain\n");
  121. return -ENXIO;
  122. }
  123. rc = set_handle_irq(&riscv_intc_irq);
  124. if (rc) {
  125. pr_err("failed to set irq handler\n");
  126. return rc;
  127. }
  128. cpuhp_setup_state(CPUHP_AP_IRQ_RISCV_STARTING,
  129. "irqchip/riscv/intc:starting",
  130. riscv_intc_cpu_starting,
  131. riscv_intc_cpu_dying);
  132. pr_info("%d local interrupts mapped\n", BITS_PER_LONG);
  133. return 0;
  134. }
  135. IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);