panel-xinpeng-xpp055c272.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Xinpeng xpp055c272 5.5" MIPI-DSI panel driver
  4. * Copyright (C) 2019 Theobroma Systems Design und Consulting GmbH
  5. *
  6. * based on
  7. *
  8. * Rockteck jh057n00900 5.5" MIPI-DSI panel driver
  9. * Copyright (C) Purism SPC 2019
  10. */
  11. #include <drm/drm_mipi_dsi.h>
  12. #include <drm/drm_modes.h>
  13. #include <drm/drm_panel.h>
  14. #include <video/display_timing.h>
  15. #include <video/mipi_display.h>
  16. #include <linux/delay.h>
  17. #include <linux/gpio/consumer.h>
  18. #include <linux/media-bus-format.h>
  19. #include <linux/module.h>
  20. #include <linux/of.h>
  21. #include <linux/regulator/consumer.h>
  22. /* Manufacturer specific Commands send via DSI */
  23. #define XPP055C272_CMD_ALL_PIXEL_OFF 0x22
  24. #define XPP055C272_CMD_ALL_PIXEL_ON 0x23
  25. #define XPP055C272_CMD_SETDISP 0xb2
  26. #define XPP055C272_CMD_SETRGBIF 0xb3
  27. #define XPP055C272_CMD_SETCYC 0xb4
  28. #define XPP055C272_CMD_SETBGP 0xb5
  29. #define XPP055C272_CMD_SETVCOM 0xb6
  30. #define XPP055C272_CMD_SETOTP 0xb7
  31. #define XPP055C272_CMD_SETPOWER_EXT 0xb8
  32. #define XPP055C272_CMD_SETEXTC 0xb9
  33. #define XPP055C272_CMD_SETMIPI 0xbA
  34. #define XPP055C272_CMD_SETVDC 0xbc
  35. #define XPP055C272_CMD_SETPCR 0xbf
  36. #define XPP055C272_CMD_SETSCR 0xc0
  37. #define XPP055C272_CMD_SETPOWER 0xc1
  38. #define XPP055C272_CMD_SETECO 0xc6
  39. #define XPP055C272_CMD_SETPANEL 0xcc
  40. #define XPP055C272_CMD_SETGAMMA 0xe0
  41. #define XPP055C272_CMD_SETEQ 0xe3
  42. #define XPP055C272_CMD_SETGIP1 0xe9
  43. #define XPP055C272_CMD_SETGIP2 0xea
  44. struct xpp055c272 {
  45. struct device *dev;
  46. struct drm_panel panel;
  47. struct gpio_desc *reset_gpio;
  48. struct regulator *vci;
  49. struct regulator *iovcc;
  50. bool prepared;
  51. };
  52. static inline struct xpp055c272 *panel_to_xpp055c272(struct drm_panel *panel)
  53. {
  54. return container_of(panel, struct xpp055c272, panel);
  55. }
  56. #define dsi_generic_write_seq(dsi, cmd, seq...) do { \
  57. static const u8 b[] = { cmd, seq }; \
  58. int ret; \
  59. ret = mipi_dsi_dcs_write_buffer(dsi, b, ARRAY_SIZE(b)); \
  60. if (ret < 0) \
  61. return ret; \
  62. } while (0)
  63. static int xpp055c272_init_sequence(struct xpp055c272 *ctx)
  64. {
  65. struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
  66. struct device *dev = ctx->dev;
  67. /*
  68. * Init sequence was supplied by the panel vendor without much
  69. * documentation.
  70. */
  71. dsi_generic_write_seq(dsi, XPP055C272_CMD_SETEXTC, 0xf1, 0x12, 0x83);
  72. dsi_generic_write_seq(dsi, XPP055C272_CMD_SETMIPI,
  73. 0x33, 0x81, 0x05, 0xf9, 0x0e, 0x0e, 0x00, 0x00,
  74. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x25,
  75. 0x00, 0x91, 0x0a, 0x00, 0x00, 0x02, 0x4f, 0x01,
  76. 0x00, 0x00, 0x37);
  77. dsi_generic_write_seq(dsi, XPP055C272_CMD_SETPOWER_EXT, 0x25);
  78. dsi_generic_write_seq(dsi, XPP055C272_CMD_SETPCR, 0x02, 0x11, 0x00);
  79. dsi_generic_write_seq(dsi, XPP055C272_CMD_SETRGBIF,
  80. 0x0c, 0x10, 0x0a, 0x50, 0x03, 0xff, 0x00, 0x00,
  81. 0x00, 0x00);
  82. dsi_generic_write_seq(dsi, XPP055C272_CMD_SETSCR,
  83. 0x73, 0x73, 0x50, 0x50, 0x00, 0x00, 0x08, 0x70,
  84. 0x00);
  85. dsi_generic_write_seq(dsi, XPP055C272_CMD_SETVDC, 0x46);
  86. dsi_generic_write_seq(dsi, XPP055C272_CMD_SETPANEL, 0x0b);
  87. dsi_generic_write_seq(dsi, XPP055C272_CMD_SETCYC, 0x80);
  88. dsi_generic_write_seq(dsi, XPP055C272_CMD_SETDISP, 0xc8, 0x12, 0x30);
  89. dsi_generic_write_seq(dsi, XPP055C272_CMD_SETEQ,
  90. 0x07, 0x07, 0x0B, 0x0B, 0x03, 0x0B, 0x00, 0x00,
  91. 0x00, 0x00, 0xFF, 0x00, 0xC0, 0x10);
  92. dsi_generic_write_seq(dsi, XPP055C272_CMD_SETPOWER,
  93. 0x53, 0x00, 0x1e, 0x1e, 0x77, 0xe1, 0xcc, 0xdd,
  94. 0x67, 0x77, 0x33, 0x33);
  95. dsi_generic_write_seq(dsi, XPP055C272_CMD_SETECO, 0x00, 0x00, 0xff,
  96. 0xff, 0x01, 0xff);
  97. dsi_generic_write_seq(dsi, XPP055C272_CMD_SETBGP, 0x09, 0x09);
  98. msleep(20);
  99. dsi_generic_write_seq(dsi, XPP055C272_CMD_SETVCOM, 0x87, 0x95);
  100. dsi_generic_write_seq(dsi, XPP055C272_CMD_SETGIP1,
  101. 0xc2, 0x10, 0x05, 0x05, 0x10, 0x05, 0xa0, 0x12,
  102. 0x31, 0x23, 0x3f, 0x81, 0x0a, 0xa0, 0x37, 0x18,
  103. 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80,
  104. 0x01, 0x00, 0x00, 0x00, 0x48, 0xf8, 0x86, 0x42,
  105. 0x08, 0x88, 0x88, 0x80, 0x88, 0x88, 0x88, 0x58,
  106. 0xf8, 0x87, 0x53, 0x18, 0x88, 0x88, 0x81, 0x88,
  107. 0x88, 0x88, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
  108. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
  109. dsi_generic_write_seq(dsi, XPP055C272_CMD_SETGIP2,
  110. 0x00, 0x1a, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
  111. 0x00, 0x00, 0x00, 0x00, 0x1f, 0x88, 0x81, 0x35,
  112. 0x78, 0x88, 0x88, 0x85, 0x88, 0x88, 0x88, 0x0f,
  113. 0x88, 0x80, 0x24, 0x68, 0x88, 0x88, 0x84, 0x88,
  114. 0x88, 0x88, 0x23, 0x10, 0x00, 0x00, 0x1c, 0x00,
  115. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  116. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x05,
  117. 0xa0, 0x00, 0x00, 0x00, 0x00);
  118. dsi_generic_write_seq(dsi, XPP055C272_CMD_SETGAMMA,
  119. 0x00, 0x06, 0x08, 0x2a, 0x31, 0x3f, 0x38, 0x36,
  120. 0x07, 0x0c, 0x0d, 0x11, 0x13, 0x12, 0x13, 0x11,
  121. 0x18, 0x00, 0x06, 0x08, 0x2a, 0x31, 0x3f, 0x38,
  122. 0x36, 0x07, 0x0c, 0x0d, 0x11, 0x13, 0x12, 0x13,
  123. 0x11, 0x18);
  124. msleep(60);
  125. dev_dbg(dev, "Panel init sequence done\n");
  126. return 0;
  127. }
  128. static int xpp055c272_unprepare(struct drm_panel *panel)
  129. {
  130. struct xpp055c272 *ctx = panel_to_xpp055c272(panel);
  131. struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
  132. int ret;
  133. if (!ctx->prepared)
  134. return 0;
  135. ret = mipi_dsi_dcs_set_display_off(dsi);
  136. if (ret < 0)
  137. dev_err(ctx->dev, "failed to set display off: %d\n", ret);
  138. mipi_dsi_dcs_enter_sleep_mode(dsi);
  139. if (ret < 0) {
  140. dev_err(ctx->dev, "failed to enter sleep mode: %d\n", ret);
  141. return ret;
  142. }
  143. regulator_disable(ctx->iovcc);
  144. regulator_disable(ctx->vci);
  145. ctx->prepared = false;
  146. return 0;
  147. }
  148. static int xpp055c272_prepare(struct drm_panel *panel)
  149. {
  150. struct xpp055c272 *ctx = panel_to_xpp055c272(panel);
  151. struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
  152. int ret;
  153. if (ctx->prepared)
  154. return 0;
  155. dev_dbg(ctx->dev, "Resetting the panel\n");
  156. ret = regulator_enable(ctx->vci);
  157. if (ret < 0) {
  158. dev_err(ctx->dev, "Failed to enable vci supply: %d\n", ret);
  159. return ret;
  160. }
  161. ret = regulator_enable(ctx->iovcc);
  162. if (ret < 0) {
  163. dev_err(ctx->dev, "Failed to enable iovcc supply: %d\n", ret);
  164. goto disable_vci;
  165. }
  166. gpiod_set_value_cansleep(ctx->reset_gpio, 1);
  167. /* T6: 10us */
  168. usleep_range(10, 20);
  169. gpiod_set_value_cansleep(ctx->reset_gpio, 0);
  170. /* T8: 20ms */
  171. msleep(20);
  172. ret = xpp055c272_init_sequence(ctx);
  173. if (ret < 0) {
  174. dev_err(ctx->dev, "Panel init sequence failed: %d\n", ret);
  175. goto disable_iovcc;
  176. }
  177. ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
  178. if (ret < 0) {
  179. dev_err(ctx->dev, "Failed to exit sleep mode: %d\n", ret);
  180. goto disable_iovcc;
  181. }
  182. /* T9: 120ms */
  183. msleep(120);
  184. ret = mipi_dsi_dcs_set_display_on(dsi);
  185. if (ret < 0) {
  186. dev_err(ctx->dev, "Failed to set display on: %d\n", ret);
  187. goto disable_iovcc;
  188. }
  189. msleep(50);
  190. ctx->prepared = true;
  191. return 0;
  192. disable_iovcc:
  193. regulator_disable(ctx->iovcc);
  194. disable_vci:
  195. regulator_disable(ctx->vci);
  196. return ret;
  197. }
  198. static const struct drm_display_mode default_mode = {
  199. .hdisplay = 720,
  200. .hsync_start = 720 + 40,
  201. .hsync_end = 720 + 40 + 10,
  202. .htotal = 720 + 40 + 10 + 40,
  203. .vdisplay = 1280,
  204. .vsync_start = 1280 + 22,
  205. .vsync_end = 1280 + 22 + 4,
  206. .vtotal = 1280 + 22 + 4 + 11,
  207. .clock = 64000,
  208. .width_mm = 68,
  209. .height_mm = 121,
  210. };
  211. static int xpp055c272_get_modes(struct drm_panel *panel,
  212. struct drm_connector *connector)
  213. {
  214. struct xpp055c272 *ctx = panel_to_xpp055c272(panel);
  215. struct drm_display_mode *mode;
  216. mode = drm_mode_duplicate(connector->dev, &default_mode);
  217. if (!mode) {
  218. dev_err(ctx->dev, "Failed to add mode %ux%u@%u\n",
  219. default_mode.hdisplay, default_mode.vdisplay,
  220. drm_mode_vrefresh(&default_mode));
  221. return -ENOMEM;
  222. }
  223. drm_mode_set_name(mode);
  224. mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
  225. connector->display_info.width_mm = mode->width_mm;
  226. connector->display_info.height_mm = mode->height_mm;
  227. drm_mode_probed_add(connector, mode);
  228. return 1;
  229. }
  230. static const struct drm_panel_funcs xpp055c272_funcs = {
  231. .unprepare = xpp055c272_unprepare,
  232. .prepare = xpp055c272_prepare,
  233. .get_modes = xpp055c272_get_modes,
  234. };
  235. static int xpp055c272_probe(struct mipi_dsi_device *dsi)
  236. {
  237. struct device *dev = &dsi->dev;
  238. struct xpp055c272 *ctx;
  239. int ret;
  240. ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
  241. if (!ctx)
  242. return -ENOMEM;
  243. ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
  244. if (IS_ERR(ctx->reset_gpio)) {
  245. dev_err(dev, "cannot get reset gpio\n");
  246. return PTR_ERR(ctx->reset_gpio);
  247. }
  248. ctx->vci = devm_regulator_get(dev, "vci");
  249. if (IS_ERR(ctx->vci)) {
  250. ret = PTR_ERR(ctx->vci);
  251. if (ret != -EPROBE_DEFER)
  252. dev_err(dev, "Failed to request vci regulator: %d\n", ret);
  253. return ret;
  254. }
  255. ctx->iovcc = devm_regulator_get(dev, "iovcc");
  256. if (IS_ERR(ctx->iovcc)) {
  257. ret = PTR_ERR(ctx->iovcc);
  258. if (ret != -EPROBE_DEFER)
  259. dev_err(dev, "Failed to request iovcc regulator: %d\n", ret);
  260. return ret;
  261. }
  262. mipi_dsi_set_drvdata(dsi, ctx);
  263. ctx->dev = dev;
  264. dsi->lanes = 4;
  265. dsi->format = MIPI_DSI_FMT_RGB888;
  266. dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
  267. MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET;
  268. drm_panel_init(&ctx->panel, &dsi->dev, &xpp055c272_funcs,
  269. DRM_MODE_CONNECTOR_DSI);
  270. ret = drm_panel_of_backlight(&ctx->panel);
  271. if (ret)
  272. return ret;
  273. drm_panel_add(&ctx->panel);
  274. ret = mipi_dsi_attach(dsi);
  275. if (ret < 0) {
  276. dev_err(dev, "mipi_dsi_attach failed: %d\n", ret);
  277. drm_panel_remove(&ctx->panel);
  278. return ret;
  279. }
  280. return 0;
  281. }
  282. static void xpp055c272_shutdown(struct mipi_dsi_device *dsi)
  283. {
  284. struct xpp055c272 *ctx = mipi_dsi_get_drvdata(dsi);
  285. int ret;
  286. ret = drm_panel_unprepare(&ctx->panel);
  287. if (ret < 0)
  288. dev_err(&dsi->dev, "Failed to unprepare panel: %d\n", ret);
  289. ret = drm_panel_disable(&ctx->panel);
  290. if (ret < 0)
  291. dev_err(&dsi->dev, "Failed to disable panel: %d\n", ret);
  292. }
  293. static int xpp055c272_remove(struct mipi_dsi_device *dsi)
  294. {
  295. struct xpp055c272 *ctx = mipi_dsi_get_drvdata(dsi);
  296. int ret;
  297. xpp055c272_shutdown(dsi);
  298. ret = mipi_dsi_detach(dsi);
  299. if (ret < 0)
  300. dev_err(&dsi->dev, "Failed to detach from DSI host: %d\n", ret);
  301. drm_panel_remove(&ctx->panel);
  302. return 0;
  303. }
  304. static const struct of_device_id xpp055c272_of_match[] = {
  305. { .compatible = "xinpeng,xpp055c272" },
  306. { /* sentinel */ }
  307. };
  308. MODULE_DEVICE_TABLE(of, xpp055c272_of_match);
  309. static struct mipi_dsi_driver xpp055c272_driver = {
  310. .driver = {
  311. .name = "panel-xinpeng-xpp055c272",
  312. .of_match_table = xpp055c272_of_match,
  313. },
  314. .probe = xpp055c272_probe,
  315. .remove = xpp055c272_remove,
  316. .shutdown = xpp055c272_shutdown,
  317. };
  318. module_mipi_dsi_driver(xpp055c272_driver);
  319. MODULE_AUTHOR("Heiko Stuebner <heiko.stuebner@theobroma-systems.com>");
  320. MODULE_DESCRIPTION("DRM driver for Xinpeng xpp055c272 MIPI DSI panel");
  321. MODULE_LICENSE("GPL v2");