panel-tpo-td028ttec1.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Toppoly TD028TTEC1 Panel Driver
  4. *
  5. * Copyright (C) 2019 Texas Instruments Incorporated
  6. *
  7. * Based on the omapdrm-specific panel-tpo-td028ttec1 driver
  8. *
  9. * Copyright (C) 2008 Nokia Corporation
  10. * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
  11. *
  12. * Neo 1973 code (jbt6k74.c):
  13. * Copyright (C) 2006-2007 OpenMoko, Inc.
  14. * Author: Harald Welte <laforge@openmoko.org>
  15. *
  16. * Ported and adapted from Neo 1973 U-Boot by:
  17. * H. Nikolaus Schaller <hns@goldelico.com>
  18. */
  19. #include <linux/delay.h>
  20. #include <linux/module.h>
  21. #include <linux/spi/spi.h>
  22. #include <drm/drm_connector.h>
  23. #include <drm/drm_modes.h>
  24. #include <drm/drm_panel.h>
  25. #define JBT_COMMAND 0x000
  26. #define JBT_DATA 0x100
  27. #define JBT_REG_SLEEP_IN 0x10
  28. #define JBT_REG_SLEEP_OUT 0x11
  29. #define JBT_REG_DISPLAY_OFF 0x28
  30. #define JBT_REG_DISPLAY_ON 0x29
  31. #define JBT_REG_RGB_FORMAT 0x3a
  32. #define JBT_REG_QUAD_RATE 0x3b
  33. #define JBT_REG_POWER_ON_OFF 0xb0
  34. #define JBT_REG_BOOSTER_OP 0xb1
  35. #define JBT_REG_BOOSTER_MODE 0xb2
  36. #define JBT_REG_BOOSTER_FREQ 0xb3
  37. #define JBT_REG_OPAMP_SYSCLK 0xb4
  38. #define JBT_REG_VSC_VOLTAGE 0xb5
  39. #define JBT_REG_VCOM_VOLTAGE 0xb6
  40. #define JBT_REG_EXT_DISPL 0xb7
  41. #define JBT_REG_OUTPUT_CONTROL 0xb8
  42. #define JBT_REG_DCCLK_DCEV 0xb9
  43. #define JBT_REG_DISPLAY_MODE1 0xba
  44. #define JBT_REG_DISPLAY_MODE2 0xbb
  45. #define JBT_REG_DISPLAY_MODE 0xbc
  46. #define JBT_REG_ASW_SLEW 0xbd
  47. #define JBT_REG_DUMMY_DISPLAY 0xbe
  48. #define JBT_REG_DRIVE_SYSTEM 0xbf
  49. #define JBT_REG_SLEEP_OUT_FR_A 0xc0
  50. #define JBT_REG_SLEEP_OUT_FR_B 0xc1
  51. #define JBT_REG_SLEEP_OUT_FR_C 0xc2
  52. #define JBT_REG_SLEEP_IN_LCCNT_D 0xc3
  53. #define JBT_REG_SLEEP_IN_LCCNT_E 0xc4
  54. #define JBT_REG_SLEEP_IN_LCCNT_F 0xc5
  55. #define JBT_REG_SLEEP_IN_LCCNT_G 0xc6
  56. #define JBT_REG_GAMMA1_FINE_1 0xc7
  57. #define JBT_REG_GAMMA1_FINE_2 0xc8
  58. #define JBT_REG_GAMMA1_INCLINATION 0xc9
  59. #define JBT_REG_GAMMA1_BLUE_OFFSET 0xca
  60. #define JBT_REG_BLANK_CONTROL 0xcf
  61. #define JBT_REG_BLANK_TH_TV 0xd0
  62. #define JBT_REG_CKV_ON_OFF 0xd1
  63. #define JBT_REG_CKV_1_2 0xd2
  64. #define JBT_REG_OEV_TIMING 0xd3
  65. #define JBT_REG_ASW_TIMING_1 0xd4
  66. #define JBT_REG_ASW_TIMING_2 0xd5
  67. #define JBT_REG_HCLOCK_VGA 0xec
  68. #define JBT_REG_HCLOCK_QVGA 0xed
  69. struct td028ttec1_panel {
  70. struct drm_panel panel;
  71. struct spi_device *spi;
  72. };
  73. #define to_td028ttec1_device(p) container_of(p, struct td028ttec1_panel, panel)
  74. /*
  75. * noinline_for_stack so we don't get multiple copies of tx_buf
  76. * on the stack in case of gcc-plugin-structleak
  77. */
  78. static int noinline_for_stack
  79. jbt_ret_write_0(struct td028ttec1_panel *lcd, u8 reg, int *err)
  80. {
  81. struct spi_device *spi = lcd->spi;
  82. u16 tx_buf = JBT_COMMAND | reg;
  83. int ret;
  84. if (err && *err)
  85. return *err;
  86. ret = spi_write(spi, (u8 *)&tx_buf, sizeof(tx_buf));
  87. if (ret < 0) {
  88. dev_err(&spi->dev, "%s: SPI write failed: %d\n", __func__, ret);
  89. if (err)
  90. *err = ret;
  91. }
  92. return ret;
  93. }
  94. static int noinline_for_stack
  95. jbt_reg_write_1(struct td028ttec1_panel *lcd,
  96. u8 reg, u8 data, int *err)
  97. {
  98. struct spi_device *spi = lcd->spi;
  99. u16 tx_buf[2];
  100. int ret;
  101. if (err && *err)
  102. return *err;
  103. tx_buf[0] = JBT_COMMAND | reg;
  104. tx_buf[1] = JBT_DATA | data;
  105. ret = spi_write(spi, (u8 *)tx_buf, sizeof(tx_buf));
  106. if (ret < 0) {
  107. dev_err(&spi->dev, "%s: SPI write failed: %d\n", __func__, ret);
  108. if (err)
  109. *err = ret;
  110. }
  111. return ret;
  112. }
  113. static int noinline_for_stack
  114. jbt_reg_write_2(struct td028ttec1_panel *lcd,
  115. u8 reg, u16 data, int *err)
  116. {
  117. struct spi_device *spi = lcd->spi;
  118. u16 tx_buf[3];
  119. int ret;
  120. if (err && *err)
  121. return *err;
  122. tx_buf[0] = JBT_COMMAND | reg;
  123. tx_buf[1] = JBT_DATA | (data >> 8);
  124. tx_buf[2] = JBT_DATA | (data & 0xff);
  125. ret = spi_write(spi, (u8 *)tx_buf, sizeof(tx_buf));
  126. if (ret < 0) {
  127. dev_err(&spi->dev, "%s: SPI write failed: %d\n", __func__, ret);
  128. if (err)
  129. *err = ret;
  130. }
  131. return ret;
  132. }
  133. static int td028ttec1_prepare(struct drm_panel *panel)
  134. {
  135. struct td028ttec1_panel *lcd = to_td028ttec1_device(panel);
  136. unsigned int i;
  137. int ret = 0;
  138. /* Three times command zero */
  139. for (i = 0; i < 3; ++i) {
  140. jbt_ret_write_0(lcd, 0x00, &ret);
  141. usleep_range(1000, 2000);
  142. }
  143. /* deep standby out */
  144. jbt_reg_write_1(lcd, JBT_REG_POWER_ON_OFF, 0x17, &ret);
  145. /* RGB I/F on, RAM write off, QVGA through, SIGCON enable */
  146. jbt_reg_write_1(lcd, JBT_REG_DISPLAY_MODE, 0x80, &ret);
  147. /* Quad mode off */
  148. jbt_reg_write_1(lcd, JBT_REG_QUAD_RATE, 0x00, &ret);
  149. /* AVDD on, XVDD on */
  150. jbt_reg_write_1(lcd, JBT_REG_POWER_ON_OFF, 0x16, &ret);
  151. /* Output control */
  152. jbt_reg_write_2(lcd, JBT_REG_OUTPUT_CONTROL, 0xfff9, &ret);
  153. /* Sleep mode off */
  154. jbt_ret_write_0(lcd, JBT_REG_SLEEP_OUT, &ret);
  155. /* at this point we have like 50% grey */
  156. /* initialize register set */
  157. jbt_reg_write_1(lcd, JBT_REG_DISPLAY_MODE1, 0x01, &ret);
  158. jbt_reg_write_1(lcd, JBT_REG_DISPLAY_MODE2, 0x00, &ret);
  159. jbt_reg_write_1(lcd, JBT_REG_RGB_FORMAT, 0x60, &ret);
  160. jbt_reg_write_1(lcd, JBT_REG_DRIVE_SYSTEM, 0x10, &ret);
  161. jbt_reg_write_1(lcd, JBT_REG_BOOSTER_OP, 0x56, &ret);
  162. jbt_reg_write_1(lcd, JBT_REG_BOOSTER_MODE, 0x33, &ret);
  163. jbt_reg_write_1(lcd, JBT_REG_BOOSTER_FREQ, 0x11, &ret);
  164. jbt_reg_write_1(lcd, JBT_REG_BOOSTER_FREQ, 0x11, &ret);
  165. jbt_reg_write_1(lcd, JBT_REG_OPAMP_SYSCLK, 0x02, &ret);
  166. jbt_reg_write_1(lcd, JBT_REG_VSC_VOLTAGE, 0x2b, &ret);
  167. jbt_reg_write_1(lcd, JBT_REG_VCOM_VOLTAGE, 0x40, &ret);
  168. jbt_reg_write_1(lcd, JBT_REG_EXT_DISPL, 0x03, &ret);
  169. jbt_reg_write_1(lcd, JBT_REG_DCCLK_DCEV, 0x04, &ret);
  170. /*
  171. * default of 0x02 in JBT_REG_ASW_SLEW responsible for 72Hz requirement
  172. * to avoid red / blue flicker
  173. */
  174. jbt_reg_write_1(lcd, JBT_REG_ASW_SLEW, 0x04, &ret);
  175. jbt_reg_write_1(lcd, JBT_REG_DUMMY_DISPLAY, 0x00, &ret);
  176. jbt_reg_write_1(lcd, JBT_REG_SLEEP_OUT_FR_A, 0x11, &ret);
  177. jbt_reg_write_1(lcd, JBT_REG_SLEEP_OUT_FR_B, 0x11, &ret);
  178. jbt_reg_write_1(lcd, JBT_REG_SLEEP_OUT_FR_C, 0x11, &ret);
  179. jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040, &ret);
  180. jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0, &ret);
  181. jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020, &ret);
  182. jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0, &ret);
  183. jbt_reg_write_2(lcd, JBT_REG_GAMMA1_FINE_1, 0x5533, &ret);
  184. jbt_reg_write_1(lcd, JBT_REG_GAMMA1_FINE_2, 0x00, &ret);
  185. jbt_reg_write_1(lcd, JBT_REG_GAMMA1_INCLINATION, 0x00, &ret);
  186. jbt_reg_write_1(lcd, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00, &ret);
  187. jbt_reg_write_2(lcd, JBT_REG_HCLOCK_VGA, 0x1f0, &ret);
  188. jbt_reg_write_1(lcd, JBT_REG_BLANK_CONTROL, 0x02, &ret);
  189. jbt_reg_write_2(lcd, JBT_REG_BLANK_TH_TV, 0x0804, &ret);
  190. jbt_reg_write_1(lcd, JBT_REG_CKV_ON_OFF, 0x01, &ret);
  191. jbt_reg_write_2(lcd, JBT_REG_CKV_1_2, 0x0000, &ret);
  192. jbt_reg_write_2(lcd, JBT_REG_OEV_TIMING, 0x0d0e, &ret);
  193. jbt_reg_write_2(lcd, JBT_REG_ASW_TIMING_1, 0x11a4, &ret);
  194. jbt_reg_write_1(lcd, JBT_REG_ASW_TIMING_2, 0x0e, &ret);
  195. return ret;
  196. }
  197. static int td028ttec1_enable(struct drm_panel *panel)
  198. {
  199. struct td028ttec1_panel *lcd = to_td028ttec1_device(panel);
  200. int ret;
  201. ret = jbt_ret_write_0(lcd, JBT_REG_DISPLAY_ON, NULL);
  202. if (ret)
  203. return ret;
  204. return 0;
  205. }
  206. static int td028ttec1_disable(struct drm_panel *panel)
  207. {
  208. struct td028ttec1_panel *lcd = to_td028ttec1_device(panel);
  209. jbt_ret_write_0(lcd, JBT_REG_DISPLAY_OFF, NULL);
  210. return 0;
  211. }
  212. static int td028ttec1_unprepare(struct drm_panel *panel)
  213. {
  214. struct td028ttec1_panel *lcd = to_td028ttec1_device(panel);
  215. jbt_reg_write_2(lcd, JBT_REG_OUTPUT_CONTROL, 0x8002, NULL);
  216. jbt_ret_write_0(lcd, JBT_REG_SLEEP_IN, NULL);
  217. jbt_reg_write_1(lcd, JBT_REG_POWER_ON_OFF, 0x00, NULL);
  218. return 0;
  219. }
  220. static const struct drm_display_mode td028ttec1_mode = {
  221. .clock = 22153,
  222. .hdisplay = 480,
  223. .hsync_start = 480 + 24,
  224. .hsync_end = 480 + 24 + 8,
  225. .htotal = 480 + 24 + 8 + 8,
  226. .vdisplay = 640,
  227. .vsync_start = 640 + 4,
  228. .vsync_end = 640 + 4 + 2,
  229. .vtotal = 640 + 4 + 2 + 2,
  230. .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
  231. .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
  232. .width_mm = 43,
  233. .height_mm = 58,
  234. };
  235. static int td028ttec1_get_modes(struct drm_panel *panel,
  236. struct drm_connector *connector)
  237. {
  238. struct drm_display_mode *mode;
  239. mode = drm_mode_duplicate(connector->dev, &td028ttec1_mode);
  240. if (!mode)
  241. return -ENOMEM;
  242. drm_mode_set_name(mode);
  243. drm_mode_probed_add(connector, mode);
  244. connector->display_info.width_mm = td028ttec1_mode.width_mm;
  245. connector->display_info.height_mm = td028ttec1_mode.height_mm;
  246. /*
  247. * FIXME: According to the datasheet sync signals are sampled on the
  248. * rising edge of the clock, but the code running on the OpenMoko Neo
  249. * FreeRunner and Neo 1973 indicates sampling on the falling edge. This
  250. * should be tested on a real device.
  251. */
  252. connector->display_info.bus_flags = DRM_BUS_FLAG_DE_HIGH
  253. | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE
  254. | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE;
  255. return 1;
  256. }
  257. static const struct drm_panel_funcs td028ttec1_funcs = {
  258. .prepare = td028ttec1_prepare,
  259. .enable = td028ttec1_enable,
  260. .disable = td028ttec1_disable,
  261. .unprepare = td028ttec1_unprepare,
  262. .get_modes = td028ttec1_get_modes,
  263. };
  264. static int td028ttec1_probe(struct spi_device *spi)
  265. {
  266. struct td028ttec1_panel *lcd;
  267. int ret;
  268. lcd = devm_kzalloc(&spi->dev, sizeof(*lcd), GFP_KERNEL);
  269. if (!lcd)
  270. return -ENOMEM;
  271. spi_set_drvdata(spi, lcd);
  272. lcd->spi = spi;
  273. spi->mode = SPI_MODE_3;
  274. spi->bits_per_word = 9;
  275. ret = spi_setup(spi);
  276. if (ret < 0) {
  277. dev_err(&spi->dev, "failed to setup SPI: %d\n", ret);
  278. return ret;
  279. }
  280. drm_panel_init(&lcd->panel, &lcd->spi->dev, &td028ttec1_funcs,
  281. DRM_MODE_CONNECTOR_DPI);
  282. ret = drm_panel_of_backlight(&lcd->panel);
  283. if (ret)
  284. return ret;
  285. drm_panel_add(&lcd->panel);
  286. return 0;
  287. }
  288. static int td028ttec1_remove(struct spi_device *spi)
  289. {
  290. struct td028ttec1_panel *lcd = spi_get_drvdata(spi);
  291. drm_panel_remove(&lcd->panel);
  292. drm_panel_disable(&lcd->panel);
  293. drm_panel_unprepare(&lcd->panel);
  294. return 0;
  295. }
  296. static const struct of_device_id td028ttec1_of_match[] = {
  297. { .compatible = "tpo,td028ttec1", },
  298. /* DT backward compatibility. */
  299. { .compatible = "toppoly,td028ttec1", },
  300. { /* sentinel */ },
  301. };
  302. MODULE_DEVICE_TABLE(of, td028ttec1_of_match);
  303. static const struct spi_device_id td028ttec1_ids[] = {
  304. { "td028ttec1", 0 },
  305. { /* sentinel */ }
  306. };
  307. MODULE_DEVICE_TABLE(spi, td028ttec1_ids);
  308. static struct spi_driver td028ttec1_driver = {
  309. .probe = td028ttec1_probe,
  310. .remove = td028ttec1_remove,
  311. .id_table = td028ttec1_ids,
  312. .driver = {
  313. .name = "panel-tpo-td028ttec1",
  314. .of_match_table = td028ttec1_of_match,
  315. },
  316. };
  317. module_spi_driver(td028ttec1_driver);
  318. MODULE_AUTHOR("H. Nikolaus Schaller <hns@goldelico.com>");
  319. MODULE_DESCRIPTION("Toppoly TD028TTEC1 panel driver");
  320. MODULE_LICENSE("GPL");