panel-simple.c 115 KB

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  1. /*
  2. * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sub license,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the
  12. * next paragraph) shall be included in all copies or substantial portions
  13. * of the Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. */
  23. #include <linux/delay.h>
  24. #include <linux/gpio/consumer.h>
  25. #include <linux/iopoll.h>
  26. #include <linux/module.h>
  27. #include <linux/of_platform.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/regulator/consumer.h>
  30. #include <video/display_timing.h>
  31. #include <video/of_display_timing.h>
  32. #include <video/videomode.h>
  33. #include <drm/drm_crtc.h>
  34. #include <drm/drm_device.h>
  35. #include <drm/drm_mipi_dsi.h>
  36. #include <drm/drm_panel.h>
  37. /**
  38. * @modes: Pointer to array of fixed modes appropriate for this panel. If
  39. * only one mode then this can just be the address of this the mode.
  40. * NOTE: cannot be used with "timings" and also if this is specified
  41. * then you cannot override the mode in the device tree.
  42. * @num_modes: Number of elements in modes array.
  43. * @timings: Pointer to array of display timings. NOTE: cannot be used with
  44. * "modes" and also these will be used to validate a device tree
  45. * override if one is present.
  46. * @num_timings: Number of elements in timings array.
  47. * @bpc: Bits per color.
  48. * @size: Structure containing the physical size of this panel.
  49. * @delay: Structure containing various delay values for this panel.
  50. * @bus_format: See MEDIA_BUS_FMT_... defines.
  51. * @bus_flags: See DRM_BUS_FLAG_... defines.
  52. */
  53. struct panel_desc {
  54. const struct drm_display_mode *modes;
  55. unsigned int num_modes;
  56. const struct display_timing *timings;
  57. unsigned int num_timings;
  58. unsigned int bpc;
  59. /**
  60. * @width: width (in millimeters) of the panel's active display area
  61. * @height: height (in millimeters) of the panel's active display area
  62. */
  63. struct {
  64. unsigned int width;
  65. unsigned int height;
  66. } size;
  67. /**
  68. * @prepare: the time (in milliseconds) that it takes for the panel to
  69. * become ready and start receiving video data
  70. * @hpd_absent_delay: Add this to the prepare delay if we know Hot
  71. * Plug Detect isn't used.
  72. * @enable: the time (in milliseconds) that it takes for the panel to
  73. * display the first valid frame after starting to receive
  74. * video data
  75. * @disable: the time (in milliseconds) that it takes for the panel to
  76. * turn the display off (no content is visible)
  77. * @unprepare: the time (in milliseconds) that it takes for the panel
  78. * to power itself down completely
  79. */
  80. struct {
  81. unsigned int prepare;
  82. unsigned int hpd_absent_delay;
  83. unsigned int enable;
  84. unsigned int disable;
  85. unsigned int unprepare;
  86. } delay;
  87. u32 bus_format;
  88. u32 bus_flags;
  89. int connector_type;
  90. };
  91. struct panel_simple {
  92. struct drm_panel base;
  93. bool prepared;
  94. bool enabled;
  95. bool no_hpd;
  96. const struct panel_desc *desc;
  97. struct regulator *supply;
  98. struct i2c_adapter *ddc;
  99. struct gpio_desc *enable_gpio;
  100. struct gpio_desc *hpd_gpio;
  101. struct drm_display_mode override_mode;
  102. enum drm_panel_orientation orientation;
  103. };
  104. static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
  105. {
  106. return container_of(panel, struct panel_simple, base);
  107. }
  108. static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
  109. struct drm_connector *connector)
  110. {
  111. struct drm_display_mode *mode;
  112. unsigned int i, num = 0;
  113. for (i = 0; i < panel->desc->num_timings; i++) {
  114. const struct display_timing *dt = &panel->desc->timings[i];
  115. struct videomode vm;
  116. videomode_from_timing(dt, &vm);
  117. mode = drm_mode_create(connector->dev);
  118. if (!mode) {
  119. dev_err(panel->base.dev, "failed to add mode %ux%u\n",
  120. dt->hactive.typ, dt->vactive.typ);
  121. continue;
  122. }
  123. drm_display_mode_from_videomode(&vm, mode);
  124. mode->type |= DRM_MODE_TYPE_DRIVER;
  125. if (panel->desc->num_timings == 1)
  126. mode->type |= DRM_MODE_TYPE_PREFERRED;
  127. drm_mode_probed_add(connector, mode);
  128. num++;
  129. }
  130. return num;
  131. }
  132. static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
  133. struct drm_connector *connector)
  134. {
  135. struct drm_display_mode *mode;
  136. unsigned int i, num = 0;
  137. for (i = 0; i < panel->desc->num_modes; i++) {
  138. const struct drm_display_mode *m = &panel->desc->modes[i];
  139. mode = drm_mode_duplicate(connector->dev, m);
  140. if (!mode) {
  141. dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
  142. m->hdisplay, m->vdisplay,
  143. drm_mode_vrefresh(m));
  144. continue;
  145. }
  146. mode->type |= DRM_MODE_TYPE_DRIVER;
  147. if (panel->desc->num_modes == 1)
  148. mode->type |= DRM_MODE_TYPE_PREFERRED;
  149. drm_mode_set_name(mode);
  150. drm_mode_probed_add(connector, mode);
  151. num++;
  152. }
  153. return num;
  154. }
  155. static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
  156. struct drm_connector *connector)
  157. {
  158. struct drm_display_mode *mode;
  159. bool has_override = panel->override_mode.type;
  160. unsigned int num = 0;
  161. if (!panel->desc)
  162. return 0;
  163. if (has_override) {
  164. mode = drm_mode_duplicate(connector->dev,
  165. &panel->override_mode);
  166. if (mode) {
  167. drm_mode_probed_add(connector, mode);
  168. num = 1;
  169. } else {
  170. dev_err(panel->base.dev, "failed to add override mode\n");
  171. }
  172. }
  173. /* Only add timings if override was not there or failed to validate */
  174. if (num == 0 && panel->desc->num_timings)
  175. num = panel_simple_get_timings_modes(panel, connector);
  176. /*
  177. * Only add fixed modes if timings/override added no mode.
  178. *
  179. * We should only ever have either the display timings specified
  180. * or a fixed mode. Anything else is rather bogus.
  181. */
  182. WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
  183. if (num == 0)
  184. num = panel_simple_get_display_modes(panel, connector);
  185. connector->display_info.bpc = panel->desc->bpc;
  186. connector->display_info.width_mm = panel->desc->size.width;
  187. connector->display_info.height_mm = panel->desc->size.height;
  188. if (panel->desc->bus_format)
  189. drm_display_info_set_bus_formats(&connector->display_info,
  190. &panel->desc->bus_format, 1);
  191. connector->display_info.bus_flags = panel->desc->bus_flags;
  192. return num;
  193. }
  194. static int panel_simple_disable(struct drm_panel *panel)
  195. {
  196. struct panel_simple *p = to_panel_simple(panel);
  197. if (!p->enabled)
  198. return 0;
  199. if (p->desc->delay.disable)
  200. msleep(p->desc->delay.disable);
  201. p->enabled = false;
  202. return 0;
  203. }
  204. static int panel_simple_unprepare(struct drm_panel *panel)
  205. {
  206. struct panel_simple *p = to_panel_simple(panel);
  207. if (!p->prepared)
  208. return 0;
  209. gpiod_set_value_cansleep(p->enable_gpio, 0);
  210. regulator_disable(p->supply);
  211. if (p->desc->delay.unprepare)
  212. msleep(p->desc->delay.unprepare);
  213. p->prepared = false;
  214. return 0;
  215. }
  216. static int panel_simple_get_hpd_gpio(struct device *dev,
  217. struct panel_simple *p, bool from_probe)
  218. {
  219. int err;
  220. p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
  221. if (IS_ERR(p->hpd_gpio)) {
  222. err = PTR_ERR(p->hpd_gpio);
  223. /*
  224. * If we're called from probe we won't consider '-EPROBE_DEFER'
  225. * to be an error--we'll leave the error code in "hpd_gpio".
  226. * When we try to use it we'll try again. This allows for
  227. * circular dependencies where the component providing the
  228. * hpd gpio needs the panel to init before probing.
  229. */
  230. if (err != -EPROBE_DEFER || !from_probe) {
  231. dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err);
  232. return err;
  233. }
  234. }
  235. return 0;
  236. }
  237. static int panel_simple_prepare(struct drm_panel *panel)
  238. {
  239. struct panel_simple *p = to_panel_simple(panel);
  240. unsigned int delay;
  241. int err;
  242. int hpd_asserted;
  243. if (p->prepared)
  244. return 0;
  245. err = regulator_enable(p->supply);
  246. if (err < 0) {
  247. dev_err(panel->dev, "failed to enable supply: %d\n", err);
  248. return err;
  249. }
  250. gpiod_set_value_cansleep(p->enable_gpio, 1);
  251. delay = p->desc->delay.prepare;
  252. if (p->no_hpd)
  253. delay += p->desc->delay.hpd_absent_delay;
  254. if (delay)
  255. msleep(delay);
  256. if (p->hpd_gpio) {
  257. if (IS_ERR(p->hpd_gpio)) {
  258. err = panel_simple_get_hpd_gpio(panel->dev, p, false);
  259. if (err)
  260. return err;
  261. }
  262. err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio,
  263. hpd_asserted, hpd_asserted,
  264. 1000, 2000000);
  265. if (hpd_asserted < 0)
  266. err = hpd_asserted;
  267. if (err) {
  268. dev_err(panel->dev,
  269. "error waiting for hpd GPIO: %d\n", err);
  270. return err;
  271. }
  272. }
  273. p->prepared = true;
  274. return 0;
  275. }
  276. static int panel_simple_enable(struct drm_panel *panel)
  277. {
  278. struct panel_simple *p = to_panel_simple(panel);
  279. if (p->enabled)
  280. return 0;
  281. if (p->desc->delay.enable)
  282. msleep(p->desc->delay.enable);
  283. p->enabled = true;
  284. return 0;
  285. }
  286. static int panel_simple_get_modes(struct drm_panel *panel,
  287. struct drm_connector *connector)
  288. {
  289. struct panel_simple *p = to_panel_simple(panel);
  290. int num = 0;
  291. /* probe EDID if a DDC bus is available */
  292. if (p->ddc) {
  293. struct edid *edid = drm_get_edid(connector, p->ddc);
  294. drm_connector_update_edid_property(connector, edid);
  295. if (edid) {
  296. num += drm_add_edid_modes(connector, edid);
  297. kfree(edid);
  298. }
  299. }
  300. /* add hard-coded panel modes */
  301. num += panel_simple_get_non_edid_modes(p, connector);
  302. /* set up connector's "panel orientation" property */
  303. drm_connector_set_panel_orientation(connector, p->orientation);
  304. return num;
  305. }
  306. static int panel_simple_get_timings(struct drm_panel *panel,
  307. unsigned int num_timings,
  308. struct display_timing *timings)
  309. {
  310. struct panel_simple *p = to_panel_simple(panel);
  311. unsigned int i;
  312. if (p->desc->num_timings < num_timings)
  313. num_timings = p->desc->num_timings;
  314. if (timings)
  315. for (i = 0; i < num_timings; i++)
  316. timings[i] = p->desc->timings[i];
  317. return p->desc->num_timings;
  318. }
  319. static const struct drm_panel_funcs panel_simple_funcs = {
  320. .disable = panel_simple_disable,
  321. .unprepare = panel_simple_unprepare,
  322. .prepare = panel_simple_prepare,
  323. .enable = panel_simple_enable,
  324. .get_modes = panel_simple_get_modes,
  325. .get_timings = panel_simple_get_timings,
  326. };
  327. static struct panel_desc panel_dpi;
  328. static int panel_dpi_probe(struct device *dev,
  329. struct panel_simple *panel)
  330. {
  331. struct display_timing *timing;
  332. const struct device_node *np;
  333. struct panel_desc *desc;
  334. unsigned int bus_flags;
  335. struct videomode vm;
  336. int ret;
  337. np = dev->of_node;
  338. desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
  339. if (!desc)
  340. return -ENOMEM;
  341. timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
  342. if (!timing)
  343. return -ENOMEM;
  344. ret = of_get_display_timing(np, "panel-timing", timing);
  345. if (ret < 0) {
  346. dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
  347. np);
  348. return ret;
  349. }
  350. desc->timings = timing;
  351. desc->num_timings = 1;
  352. of_property_read_u32(np, "width-mm", &desc->size.width);
  353. of_property_read_u32(np, "height-mm", &desc->size.height);
  354. /* Extract bus_flags from display_timing */
  355. bus_flags = 0;
  356. vm.flags = timing->flags;
  357. drm_bus_flags_from_videomode(&vm, &bus_flags);
  358. desc->bus_flags = bus_flags;
  359. /* We do not know the connector for the DT node, so guess it */
  360. desc->connector_type = DRM_MODE_CONNECTOR_DPI;
  361. panel->desc = desc;
  362. return 0;
  363. }
  364. #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
  365. (to_check->field.typ >= bounds->field.min && \
  366. to_check->field.typ <= bounds->field.max)
  367. static void panel_simple_parse_panel_timing_node(struct device *dev,
  368. struct panel_simple *panel,
  369. const struct display_timing *ot)
  370. {
  371. const struct panel_desc *desc = panel->desc;
  372. struct videomode vm;
  373. unsigned int i;
  374. if (WARN_ON(desc->num_modes)) {
  375. dev_err(dev, "Reject override mode: panel has a fixed mode\n");
  376. return;
  377. }
  378. if (WARN_ON(!desc->num_timings)) {
  379. dev_err(dev, "Reject override mode: no timings specified\n");
  380. return;
  381. }
  382. for (i = 0; i < panel->desc->num_timings; i++) {
  383. const struct display_timing *dt = &panel->desc->timings[i];
  384. if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
  385. !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
  386. !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
  387. !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
  388. !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
  389. !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
  390. !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
  391. !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
  392. continue;
  393. if (ot->flags != dt->flags)
  394. continue;
  395. videomode_from_timing(ot, &vm);
  396. drm_display_mode_from_videomode(&vm, &panel->override_mode);
  397. panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
  398. DRM_MODE_TYPE_PREFERRED;
  399. break;
  400. }
  401. if (WARN_ON(!panel->override_mode.type))
  402. dev_err(dev, "Reject override mode: No display_timing found\n");
  403. }
  404. static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
  405. {
  406. struct panel_simple *panel;
  407. struct display_timing dt;
  408. struct device_node *ddc;
  409. int connector_type;
  410. u32 bus_flags;
  411. int err;
  412. panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
  413. if (!panel)
  414. return -ENOMEM;
  415. panel->enabled = false;
  416. panel->prepared = false;
  417. panel->desc = desc;
  418. panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
  419. if (!panel->no_hpd) {
  420. err = panel_simple_get_hpd_gpio(dev, panel, true);
  421. if (err)
  422. return err;
  423. }
  424. panel->supply = devm_regulator_get(dev, "power");
  425. if (IS_ERR(panel->supply))
  426. return PTR_ERR(panel->supply);
  427. panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
  428. GPIOD_OUT_LOW);
  429. if (IS_ERR(panel->enable_gpio)) {
  430. err = PTR_ERR(panel->enable_gpio);
  431. if (err != -EPROBE_DEFER)
  432. dev_err(dev, "failed to request GPIO: %d\n", err);
  433. return err;
  434. }
  435. err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
  436. if (err) {
  437. dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
  438. return err;
  439. }
  440. ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
  441. if (ddc) {
  442. panel->ddc = of_find_i2c_adapter_by_node(ddc);
  443. of_node_put(ddc);
  444. if (!panel->ddc)
  445. return -EPROBE_DEFER;
  446. }
  447. if (desc == &panel_dpi) {
  448. /* Handle the generic panel-dpi binding */
  449. err = panel_dpi_probe(dev, panel);
  450. if (err)
  451. goto free_ddc;
  452. desc = panel->desc;
  453. } else {
  454. if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
  455. panel_simple_parse_panel_timing_node(dev, panel, &dt);
  456. }
  457. connector_type = desc->connector_type;
  458. /* Catch common mistakes for panels. */
  459. switch (connector_type) {
  460. case 0:
  461. dev_warn(dev, "Specify missing connector_type\n");
  462. connector_type = DRM_MODE_CONNECTOR_DPI;
  463. break;
  464. case DRM_MODE_CONNECTOR_LVDS:
  465. WARN_ON(desc->bus_flags &
  466. ~(DRM_BUS_FLAG_DE_LOW |
  467. DRM_BUS_FLAG_DE_HIGH |
  468. DRM_BUS_FLAG_DATA_MSB_TO_LSB |
  469. DRM_BUS_FLAG_DATA_LSB_TO_MSB));
  470. WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
  471. desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
  472. desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
  473. WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
  474. desc->bpc != 6);
  475. WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
  476. desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
  477. desc->bpc != 8);
  478. break;
  479. case DRM_MODE_CONNECTOR_eDP:
  480. if (desc->bus_format == 0)
  481. dev_warn(dev, "Specify missing bus_format\n");
  482. if (desc->bpc != 6 && desc->bpc != 8)
  483. dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
  484. break;
  485. case DRM_MODE_CONNECTOR_DSI:
  486. if (desc->bpc != 6 && desc->bpc != 8)
  487. dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
  488. break;
  489. case DRM_MODE_CONNECTOR_DPI:
  490. bus_flags = DRM_BUS_FLAG_DE_LOW |
  491. DRM_BUS_FLAG_DE_HIGH |
  492. DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
  493. DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
  494. DRM_BUS_FLAG_DATA_MSB_TO_LSB |
  495. DRM_BUS_FLAG_DATA_LSB_TO_MSB |
  496. DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
  497. DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
  498. if (desc->bus_flags & ~bus_flags)
  499. dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
  500. if (!(desc->bus_flags & bus_flags))
  501. dev_warn(dev, "Specify missing bus_flags\n");
  502. if (desc->bus_format == 0)
  503. dev_warn(dev, "Specify missing bus_format\n");
  504. if (desc->bpc != 6 && desc->bpc != 8)
  505. dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
  506. break;
  507. default:
  508. dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
  509. connector_type = DRM_MODE_CONNECTOR_DPI;
  510. break;
  511. }
  512. drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
  513. err = drm_panel_of_backlight(&panel->base);
  514. if (err)
  515. goto free_ddc;
  516. drm_panel_add(&panel->base);
  517. dev_set_drvdata(dev, panel);
  518. return 0;
  519. free_ddc:
  520. if (panel->ddc)
  521. put_device(&panel->ddc->dev);
  522. return err;
  523. }
  524. static int panel_simple_remove(struct device *dev)
  525. {
  526. struct panel_simple *panel = dev_get_drvdata(dev);
  527. drm_panel_remove(&panel->base);
  528. drm_panel_disable(&panel->base);
  529. drm_panel_unprepare(&panel->base);
  530. if (panel->ddc)
  531. put_device(&panel->ddc->dev);
  532. return 0;
  533. }
  534. static void panel_simple_shutdown(struct device *dev)
  535. {
  536. struct panel_simple *panel = dev_get_drvdata(dev);
  537. drm_panel_disable(&panel->base);
  538. drm_panel_unprepare(&panel->base);
  539. }
  540. static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
  541. .clock = 71100,
  542. .hdisplay = 1280,
  543. .hsync_start = 1280 + 40,
  544. .hsync_end = 1280 + 40 + 80,
  545. .htotal = 1280 + 40 + 80 + 40,
  546. .vdisplay = 800,
  547. .vsync_start = 800 + 3,
  548. .vsync_end = 800 + 3 + 10,
  549. .vtotal = 800 + 3 + 10 + 10,
  550. .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
  551. };
  552. static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
  553. .modes = &ampire_am_1280800n3tzqw_t00h_mode,
  554. .num_modes = 1,
  555. .bpc = 6,
  556. .size = {
  557. .width = 217,
  558. .height = 136,
  559. },
  560. .bus_flags = DRM_BUS_FLAG_DE_HIGH,
  561. .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
  562. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  563. };
  564. static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
  565. .clock = 9000,
  566. .hdisplay = 480,
  567. .hsync_start = 480 + 2,
  568. .hsync_end = 480 + 2 + 41,
  569. .htotal = 480 + 2 + 41 + 2,
  570. .vdisplay = 272,
  571. .vsync_start = 272 + 2,
  572. .vsync_end = 272 + 2 + 10,
  573. .vtotal = 272 + 2 + 10 + 2,
  574. .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
  575. };
  576. static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
  577. .modes = &ampire_am_480272h3tmqw_t01h_mode,
  578. .num_modes = 1,
  579. .bpc = 8,
  580. .size = {
  581. .width = 105,
  582. .height = 67,
  583. },
  584. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  585. };
  586. static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
  587. .clock = 33333,
  588. .hdisplay = 800,
  589. .hsync_start = 800 + 0,
  590. .hsync_end = 800 + 0 + 255,
  591. .htotal = 800 + 0 + 255 + 0,
  592. .vdisplay = 480,
  593. .vsync_start = 480 + 2,
  594. .vsync_end = 480 + 2 + 45,
  595. .vtotal = 480 + 2 + 45 + 0,
  596. .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
  597. };
  598. static const struct panel_desc ampire_am800480r3tmqwa1h = {
  599. .modes = &ampire_am800480r3tmqwa1h_mode,
  600. .num_modes = 1,
  601. .bpc = 6,
  602. .size = {
  603. .width = 152,
  604. .height = 91,
  605. },
  606. .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
  607. };
  608. static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
  609. .pixelclock = { 26400000, 33300000, 46800000 },
  610. .hactive = { 800, 800, 800 },
  611. .hfront_porch = { 16, 210, 354 },
  612. .hback_porch = { 45, 36, 6 },
  613. .hsync_len = { 1, 10, 40 },
  614. .vactive = { 480, 480, 480 },
  615. .vfront_porch = { 7, 22, 147 },
  616. .vback_porch = { 22, 13, 3 },
  617. .vsync_len = { 1, 10, 20 },
  618. .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
  619. DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
  620. };
  621. static const struct panel_desc armadeus_st0700_adapt = {
  622. .timings = &santek_st0700i5y_rbslw_f_timing,
  623. .num_timings = 1,
  624. .bpc = 6,
  625. .size = {
  626. .width = 154,
  627. .height = 86,
  628. },
  629. .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
  630. .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
  631. };
  632. static const struct drm_display_mode auo_b101aw03_mode = {
  633. .clock = 51450,
  634. .hdisplay = 1024,
  635. .hsync_start = 1024 + 156,
  636. .hsync_end = 1024 + 156 + 8,
  637. .htotal = 1024 + 156 + 8 + 156,
  638. .vdisplay = 600,
  639. .vsync_start = 600 + 16,
  640. .vsync_end = 600 + 16 + 6,
  641. .vtotal = 600 + 16 + 6 + 16,
  642. };
  643. static const struct panel_desc auo_b101aw03 = {
  644. .modes = &auo_b101aw03_mode,
  645. .num_modes = 1,
  646. .bpc = 6,
  647. .size = {
  648. .width = 223,
  649. .height = 125,
  650. },
  651. .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
  652. .bus_flags = DRM_BUS_FLAG_DE_HIGH,
  653. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  654. };
  655. static const struct display_timing auo_b101ean01_timing = {
  656. .pixelclock = { 65300000, 72500000, 75000000 },
  657. .hactive = { 1280, 1280, 1280 },
  658. .hfront_porch = { 18, 119, 119 },
  659. .hback_porch = { 21, 21, 21 },
  660. .hsync_len = { 32, 32, 32 },
  661. .vactive = { 800, 800, 800 },
  662. .vfront_porch = { 4, 4, 4 },
  663. .vback_porch = { 8, 8, 8 },
  664. .vsync_len = { 18, 20, 20 },
  665. };
  666. static const struct panel_desc auo_b101ean01 = {
  667. .timings = &auo_b101ean01_timing,
  668. .num_timings = 1,
  669. .bpc = 6,
  670. .size = {
  671. .width = 217,
  672. .height = 136,
  673. },
  674. };
  675. static const struct drm_display_mode auo_b101xtn01_mode = {
  676. .clock = 72000,
  677. .hdisplay = 1366,
  678. .hsync_start = 1366 + 20,
  679. .hsync_end = 1366 + 20 + 70,
  680. .htotal = 1366 + 20 + 70,
  681. .vdisplay = 768,
  682. .vsync_start = 768 + 14,
  683. .vsync_end = 768 + 14 + 42,
  684. .vtotal = 768 + 14 + 42,
  685. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  686. };
  687. static const struct panel_desc auo_b101xtn01 = {
  688. .modes = &auo_b101xtn01_mode,
  689. .num_modes = 1,
  690. .bpc = 6,
  691. .size = {
  692. .width = 223,
  693. .height = 125,
  694. },
  695. };
  696. static const struct drm_display_mode auo_b116xak01_mode = {
  697. .clock = 69300,
  698. .hdisplay = 1366,
  699. .hsync_start = 1366 + 48,
  700. .hsync_end = 1366 + 48 + 32,
  701. .htotal = 1366 + 48 + 32 + 10,
  702. .vdisplay = 768,
  703. .vsync_start = 768 + 4,
  704. .vsync_end = 768 + 4 + 6,
  705. .vtotal = 768 + 4 + 6 + 15,
  706. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  707. };
  708. static const struct panel_desc auo_b116xak01 = {
  709. .modes = &auo_b116xak01_mode,
  710. .num_modes = 1,
  711. .bpc = 6,
  712. .size = {
  713. .width = 256,
  714. .height = 144,
  715. },
  716. .delay = {
  717. .hpd_absent_delay = 200,
  718. },
  719. .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
  720. .connector_type = DRM_MODE_CONNECTOR_eDP,
  721. };
  722. static const struct drm_display_mode auo_b116xw03_mode = {
  723. .clock = 70589,
  724. .hdisplay = 1366,
  725. .hsync_start = 1366 + 40,
  726. .hsync_end = 1366 + 40 + 40,
  727. .htotal = 1366 + 40 + 40 + 32,
  728. .vdisplay = 768,
  729. .vsync_start = 768 + 10,
  730. .vsync_end = 768 + 10 + 12,
  731. .vtotal = 768 + 10 + 12 + 6,
  732. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  733. };
  734. static const struct panel_desc auo_b116xw03 = {
  735. .modes = &auo_b116xw03_mode,
  736. .num_modes = 1,
  737. .bpc = 6,
  738. .size = {
  739. .width = 256,
  740. .height = 144,
  741. },
  742. .delay = {
  743. .enable = 400,
  744. },
  745. .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
  746. .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
  747. .connector_type = DRM_MODE_CONNECTOR_eDP,
  748. };
  749. static const struct drm_display_mode auo_b133xtn01_mode = {
  750. .clock = 69500,
  751. .hdisplay = 1366,
  752. .hsync_start = 1366 + 48,
  753. .hsync_end = 1366 + 48 + 32,
  754. .htotal = 1366 + 48 + 32 + 20,
  755. .vdisplay = 768,
  756. .vsync_start = 768 + 3,
  757. .vsync_end = 768 + 3 + 6,
  758. .vtotal = 768 + 3 + 6 + 13,
  759. };
  760. static const struct panel_desc auo_b133xtn01 = {
  761. .modes = &auo_b133xtn01_mode,
  762. .num_modes = 1,
  763. .bpc = 6,
  764. .size = {
  765. .width = 293,
  766. .height = 165,
  767. },
  768. };
  769. static const struct drm_display_mode auo_b133htn01_mode = {
  770. .clock = 150660,
  771. .hdisplay = 1920,
  772. .hsync_start = 1920 + 172,
  773. .hsync_end = 1920 + 172 + 80,
  774. .htotal = 1920 + 172 + 80 + 60,
  775. .vdisplay = 1080,
  776. .vsync_start = 1080 + 25,
  777. .vsync_end = 1080 + 25 + 10,
  778. .vtotal = 1080 + 25 + 10 + 10,
  779. };
  780. static const struct panel_desc auo_b133htn01 = {
  781. .modes = &auo_b133htn01_mode,
  782. .num_modes = 1,
  783. .bpc = 6,
  784. .size = {
  785. .width = 293,
  786. .height = 165,
  787. },
  788. .delay = {
  789. .prepare = 105,
  790. .enable = 20,
  791. .unprepare = 50,
  792. },
  793. };
  794. static const struct display_timing auo_g070vvn01_timings = {
  795. .pixelclock = { 33300000, 34209000, 45000000 },
  796. .hactive = { 800, 800, 800 },
  797. .hfront_porch = { 20, 40, 200 },
  798. .hback_porch = { 87, 40, 1 },
  799. .hsync_len = { 1, 48, 87 },
  800. .vactive = { 480, 480, 480 },
  801. .vfront_porch = { 5, 13, 200 },
  802. .vback_porch = { 31, 31, 29 },
  803. .vsync_len = { 1, 1, 3 },
  804. };
  805. static const struct panel_desc auo_g070vvn01 = {
  806. .timings = &auo_g070vvn01_timings,
  807. .num_timings = 1,
  808. .bpc = 8,
  809. .size = {
  810. .width = 152,
  811. .height = 91,
  812. },
  813. .delay = {
  814. .prepare = 200,
  815. .enable = 50,
  816. .disable = 50,
  817. .unprepare = 1000,
  818. },
  819. };
  820. static const struct drm_display_mode auo_g101evn010_mode = {
  821. .clock = 68930,
  822. .hdisplay = 1280,
  823. .hsync_start = 1280 + 82,
  824. .hsync_end = 1280 + 82 + 2,
  825. .htotal = 1280 + 82 + 2 + 84,
  826. .vdisplay = 800,
  827. .vsync_start = 800 + 8,
  828. .vsync_end = 800 + 8 + 2,
  829. .vtotal = 800 + 8 + 2 + 6,
  830. };
  831. static const struct panel_desc auo_g101evn010 = {
  832. .modes = &auo_g101evn010_mode,
  833. .num_modes = 1,
  834. .bpc = 6,
  835. .size = {
  836. .width = 216,
  837. .height = 135,
  838. },
  839. .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
  840. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  841. };
  842. static const struct drm_display_mode auo_g104sn02_mode = {
  843. .clock = 40000,
  844. .hdisplay = 800,
  845. .hsync_start = 800 + 40,
  846. .hsync_end = 800 + 40 + 216,
  847. .htotal = 800 + 40 + 216 + 128,
  848. .vdisplay = 600,
  849. .vsync_start = 600 + 10,
  850. .vsync_end = 600 + 10 + 35,
  851. .vtotal = 600 + 10 + 35 + 2,
  852. };
  853. static const struct panel_desc auo_g104sn02 = {
  854. .modes = &auo_g104sn02_mode,
  855. .num_modes = 1,
  856. .bpc = 8,
  857. .size = {
  858. .width = 211,
  859. .height = 158,
  860. },
  861. };
  862. static const struct drm_display_mode auo_g121ean01_mode = {
  863. .clock = 66700,
  864. .hdisplay = 1280,
  865. .hsync_start = 1280 + 58,
  866. .hsync_end = 1280 + 58 + 8,
  867. .htotal = 1280 + 58 + 8 + 70,
  868. .vdisplay = 800,
  869. .vsync_start = 800 + 6,
  870. .vsync_end = 800 + 6 + 4,
  871. .vtotal = 800 + 6 + 4 + 10,
  872. };
  873. static const struct panel_desc auo_g121ean01 = {
  874. .modes = &auo_g121ean01_mode,
  875. .num_modes = 1,
  876. .bpc = 8,
  877. .size = {
  878. .width = 261,
  879. .height = 163,
  880. },
  881. .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
  882. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  883. };
  884. static const struct display_timing auo_g133han01_timings = {
  885. .pixelclock = { 134000000, 141200000, 149000000 },
  886. .hactive = { 1920, 1920, 1920 },
  887. .hfront_porch = { 39, 58, 77 },
  888. .hback_porch = { 59, 88, 117 },
  889. .hsync_len = { 28, 42, 56 },
  890. .vactive = { 1080, 1080, 1080 },
  891. .vfront_porch = { 3, 8, 11 },
  892. .vback_porch = { 5, 14, 19 },
  893. .vsync_len = { 4, 14, 19 },
  894. };
  895. static const struct panel_desc auo_g133han01 = {
  896. .timings = &auo_g133han01_timings,
  897. .num_timings = 1,
  898. .bpc = 8,
  899. .size = {
  900. .width = 293,
  901. .height = 165,
  902. },
  903. .delay = {
  904. .prepare = 200,
  905. .enable = 50,
  906. .disable = 50,
  907. .unprepare = 1000,
  908. },
  909. .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
  910. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  911. };
  912. static const struct drm_display_mode auo_g156xtn01_mode = {
  913. .clock = 76000,
  914. .hdisplay = 1366,
  915. .hsync_start = 1366 + 33,
  916. .hsync_end = 1366 + 33 + 67,
  917. .htotal = 1560,
  918. .vdisplay = 768,
  919. .vsync_start = 768 + 4,
  920. .vsync_end = 768 + 4 + 4,
  921. .vtotal = 806,
  922. };
  923. static const struct panel_desc auo_g156xtn01 = {
  924. .modes = &auo_g156xtn01_mode,
  925. .num_modes = 1,
  926. .bpc = 8,
  927. .size = {
  928. .width = 344,
  929. .height = 194,
  930. },
  931. .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
  932. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  933. };
  934. static const struct display_timing auo_g185han01_timings = {
  935. .pixelclock = { 120000000, 144000000, 175000000 },
  936. .hactive = { 1920, 1920, 1920 },
  937. .hfront_porch = { 36, 120, 148 },
  938. .hback_porch = { 24, 88, 108 },
  939. .hsync_len = { 20, 48, 64 },
  940. .vactive = { 1080, 1080, 1080 },
  941. .vfront_porch = { 6, 10, 40 },
  942. .vback_porch = { 2, 5, 20 },
  943. .vsync_len = { 2, 5, 20 },
  944. };
  945. static const struct panel_desc auo_g185han01 = {
  946. .timings = &auo_g185han01_timings,
  947. .num_timings = 1,
  948. .bpc = 8,
  949. .size = {
  950. .width = 409,
  951. .height = 230,
  952. },
  953. .delay = {
  954. .prepare = 50,
  955. .enable = 200,
  956. .disable = 110,
  957. .unprepare = 1000,
  958. },
  959. .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
  960. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  961. };
  962. static const struct display_timing auo_g190ean01_timings = {
  963. .pixelclock = { 90000000, 108000000, 135000000 },
  964. .hactive = { 1280, 1280, 1280 },
  965. .hfront_porch = { 126, 184, 1266 },
  966. .hback_porch = { 84, 122, 844 },
  967. .hsync_len = { 70, 102, 704 },
  968. .vactive = { 1024, 1024, 1024 },
  969. .vfront_porch = { 4, 26, 76 },
  970. .vback_porch = { 2, 8, 25 },
  971. .vsync_len = { 2, 8, 25 },
  972. };
  973. static const struct panel_desc auo_g190ean01 = {
  974. .timings = &auo_g190ean01_timings,
  975. .num_timings = 1,
  976. .bpc = 8,
  977. .size = {
  978. .width = 376,
  979. .height = 301,
  980. },
  981. .delay = {
  982. .prepare = 50,
  983. .enable = 200,
  984. .disable = 110,
  985. .unprepare = 1000,
  986. },
  987. .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
  988. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  989. };
  990. static const struct display_timing auo_p320hvn03_timings = {
  991. .pixelclock = { 106000000, 148500000, 164000000 },
  992. .hactive = { 1920, 1920, 1920 },
  993. .hfront_porch = { 25, 50, 130 },
  994. .hback_porch = { 25, 50, 130 },
  995. .hsync_len = { 20, 40, 105 },
  996. .vactive = { 1080, 1080, 1080 },
  997. .vfront_porch = { 8, 17, 150 },
  998. .vback_porch = { 8, 17, 150 },
  999. .vsync_len = { 4, 11, 100 },
  1000. };
  1001. static const struct panel_desc auo_p320hvn03 = {
  1002. .timings = &auo_p320hvn03_timings,
  1003. .num_timings = 1,
  1004. .bpc = 8,
  1005. .size = {
  1006. .width = 698,
  1007. .height = 393,
  1008. },
  1009. .delay = {
  1010. .prepare = 1,
  1011. .enable = 450,
  1012. .unprepare = 500,
  1013. },
  1014. .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
  1015. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  1016. };
  1017. static const struct drm_display_mode auo_t215hvn01_mode = {
  1018. .clock = 148800,
  1019. .hdisplay = 1920,
  1020. .hsync_start = 1920 + 88,
  1021. .hsync_end = 1920 + 88 + 44,
  1022. .htotal = 1920 + 88 + 44 + 148,
  1023. .vdisplay = 1080,
  1024. .vsync_start = 1080 + 4,
  1025. .vsync_end = 1080 + 4 + 5,
  1026. .vtotal = 1080 + 4 + 5 + 36,
  1027. };
  1028. static const struct panel_desc auo_t215hvn01 = {
  1029. .modes = &auo_t215hvn01_mode,
  1030. .num_modes = 1,
  1031. .bpc = 8,
  1032. .size = {
  1033. .width = 430,
  1034. .height = 270,
  1035. },
  1036. .delay = {
  1037. .disable = 5,
  1038. .unprepare = 1000,
  1039. }
  1040. };
  1041. static const struct drm_display_mode avic_tm070ddh03_mode = {
  1042. .clock = 51200,
  1043. .hdisplay = 1024,
  1044. .hsync_start = 1024 + 160,
  1045. .hsync_end = 1024 + 160 + 4,
  1046. .htotal = 1024 + 160 + 4 + 156,
  1047. .vdisplay = 600,
  1048. .vsync_start = 600 + 17,
  1049. .vsync_end = 600 + 17 + 1,
  1050. .vtotal = 600 + 17 + 1 + 17,
  1051. };
  1052. static const struct panel_desc avic_tm070ddh03 = {
  1053. .modes = &avic_tm070ddh03_mode,
  1054. .num_modes = 1,
  1055. .bpc = 8,
  1056. .size = {
  1057. .width = 154,
  1058. .height = 90,
  1059. },
  1060. .delay = {
  1061. .prepare = 20,
  1062. .enable = 200,
  1063. .disable = 200,
  1064. },
  1065. };
  1066. static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
  1067. .clock = 30000,
  1068. .hdisplay = 800,
  1069. .hsync_start = 800 + 40,
  1070. .hsync_end = 800 + 40 + 48,
  1071. .htotal = 800 + 40 + 48 + 40,
  1072. .vdisplay = 480,
  1073. .vsync_start = 480 + 13,
  1074. .vsync_end = 480 + 13 + 3,
  1075. .vtotal = 480 + 13 + 3 + 29,
  1076. };
  1077. static const struct panel_desc bananapi_s070wv20_ct16 = {
  1078. .modes = &bananapi_s070wv20_ct16_mode,
  1079. .num_modes = 1,
  1080. .bpc = 6,
  1081. .size = {
  1082. .width = 154,
  1083. .height = 86,
  1084. },
  1085. };
  1086. static const struct drm_display_mode boe_hv070wsa_mode = {
  1087. .clock = 42105,
  1088. .hdisplay = 1024,
  1089. .hsync_start = 1024 + 30,
  1090. .hsync_end = 1024 + 30 + 30,
  1091. .htotal = 1024 + 30 + 30 + 30,
  1092. .vdisplay = 600,
  1093. .vsync_start = 600 + 10,
  1094. .vsync_end = 600 + 10 + 10,
  1095. .vtotal = 600 + 10 + 10 + 10,
  1096. };
  1097. static const struct panel_desc boe_hv070wsa = {
  1098. .modes = &boe_hv070wsa_mode,
  1099. .num_modes = 1,
  1100. .bpc = 8,
  1101. .size = {
  1102. .width = 154,
  1103. .height = 90,
  1104. },
  1105. .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
  1106. .bus_flags = DRM_BUS_FLAG_DE_HIGH,
  1107. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  1108. };
  1109. static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
  1110. {
  1111. .clock = 71900,
  1112. .hdisplay = 1280,
  1113. .hsync_start = 1280 + 48,
  1114. .hsync_end = 1280 + 48 + 32,
  1115. .htotal = 1280 + 48 + 32 + 80,
  1116. .vdisplay = 800,
  1117. .vsync_start = 800 + 3,
  1118. .vsync_end = 800 + 3 + 5,
  1119. .vtotal = 800 + 3 + 5 + 24,
  1120. },
  1121. {
  1122. .clock = 57500,
  1123. .hdisplay = 1280,
  1124. .hsync_start = 1280 + 48,
  1125. .hsync_end = 1280 + 48 + 32,
  1126. .htotal = 1280 + 48 + 32 + 80,
  1127. .vdisplay = 800,
  1128. .vsync_start = 800 + 3,
  1129. .vsync_end = 800 + 3 + 5,
  1130. .vtotal = 800 + 3 + 5 + 24,
  1131. },
  1132. };
  1133. static const struct panel_desc boe_nv101wxmn51 = {
  1134. .modes = boe_nv101wxmn51_modes,
  1135. .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
  1136. .bpc = 8,
  1137. .size = {
  1138. .width = 217,
  1139. .height = 136,
  1140. },
  1141. .delay = {
  1142. .prepare = 210,
  1143. .enable = 50,
  1144. .unprepare = 160,
  1145. },
  1146. };
  1147. /* Also used for boe_nv133fhm_n62 */
  1148. static const struct drm_display_mode boe_nv133fhm_n61_modes = {
  1149. .clock = 147840,
  1150. .hdisplay = 1920,
  1151. .hsync_start = 1920 + 48,
  1152. .hsync_end = 1920 + 48 + 32,
  1153. .htotal = 1920 + 48 + 32 + 200,
  1154. .vdisplay = 1080,
  1155. .vsync_start = 1080 + 3,
  1156. .vsync_end = 1080 + 3 + 6,
  1157. .vtotal = 1080 + 3 + 6 + 31,
  1158. .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
  1159. };
  1160. /* Also used for boe_nv133fhm_n62 */
  1161. static const struct panel_desc boe_nv133fhm_n61 = {
  1162. .modes = &boe_nv133fhm_n61_modes,
  1163. .num_modes = 1,
  1164. .bpc = 6,
  1165. .size = {
  1166. .width = 294,
  1167. .height = 165,
  1168. },
  1169. .delay = {
  1170. /*
  1171. * When power is first given to the panel there's a short
  1172. * spike on the HPD line. It was explained that this spike
  1173. * was until the TCON data download was complete. On
  1174. * one system this was measured at 8 ms. We'll put 15 ms
  1175. * in the prepare delay just to be safe and take it away
  1176. * from the hpd_absent_delay (which would otherwise be 200 ms)
  1177. * to handle this. That means:
  1178. * - If HPD isn't hooked up you still have 200 ms delay.
  1179. * - If HPD is hooked up we won't try to look at it for the
  1180. * first 15 ms.
  1181. */
  1182. .prepare = 15,
  1183. .hpd_absent_delay = 185,
  1184. .unprepare = 500,
  1185. },
  1186. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  1187. .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
  1188. .connector_type = DRM_MODE_CONNECTOR_eDP,
  1189. };
  1190. static const struct drm_display_mode boe_nv140fhmn49_modes[] = {
  1191. {
  1192. .clock = 148500,
  1193. .hdisplay = 1920,
  1194. .hsync_start = 1920 + 48,
  1195. .hsync_end = 1920 + 48 + 32,
  1196. .htotal = 2200,
  1197. .vdisplay = 1080,
  1198. .vsync_start = 1080 + 3,
  1199. .vsync_end = 1080 + 3 + 5,
  1200. .vtotal = 1125,
  1201. },
  1202. };
  1203. static const struct panel_desc boe_nv140fhmn49 = {
  1204. .modes = boe_nv140fhmn49_modes,
  1205. .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes),
  1206. .bpc = 6,
  1207. .size = {
  1208. .width = 309,
  1209. .height = 174,
  1210. },
  1211. .delay = {
  1212. .prepare = 210,
  1213. .enable = 50,
  1214. .unprepare = 160,
  1215. },
  1216. .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
  1217. .connector_type = DRM_MODE_CONNECTOR_eDP,
  1218. };
  1219. static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
  1220. .clock = 9000,
  1221. .hdisplay = 480,
  1222. .hsync_start = 480 + 5,
  1223. .hsync_end = 480 + 5 + 5,
  1224. .htotal = 480 + 5 + 5 + 40,
  1225. .vdisplay = 272,
  1226. .vsync_start = 272 + 8,
  1227. .vsync_end = 272 + 8 + 8,
  1228. .vtotal = 272 + 8 + 8 + 8,
  1229. .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
  1230. };
  1231. static const struct panel_desc cdtech_s043wq26h_ct7 = {
  1232. .modes = &cdtech_s043wq26h_ct7_mode,
  1233. .num_modes = 1,
  1234. .bpc = 8,
  1235. .size = {
  1236. .width = 95,
  1237. .height = 54,
  1238. },
  1239. .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
  1240. };
  1241. /* S070PWS19HP-FC21 2017/04/22 */
  1242. static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
  1243. .clock = 51200,
  1244. .hdisplay = 1024,
  1245. .hsync_start = 1024 + 160,
  1246. .hsync_end = 1024 + 160 + 20,
  1247. .htotal = 1024 + 160 + 20 + 140,
  1248. .vdisplay = 600,
  1249. .vsync_start = 600 + 12,
  1250. .vsync_end = 600 + 12 + 3,
  1251. .vtotal = 600 + 12 + 3 + 20,
  1252. .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
  1253. };
  1254. static const struct panel_desc cdtech_s070pws19hp_fc21 = {
  1255. .modes = &cdtech_s070pws19hp_fc21_mode,
  1256. .num_modes = 1,
  1257. .bpc = 6,
  1258. .size = {
  1259. .width = 154,
  1260. .height = 86,
  1261. },
  1262. .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
  1263. .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
  1264. .connector_type = DRM_MODE_CONNECTOR_DPI,
  1265. };
  1266. /* S070SWV29HG-DC44 2017/09/21 */
  1267. static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
  1268. .clock = 33300,
  1269. .hdisplay = 800,
  1270. .hsync_start = 800 + 210,
  1271. .hsync_end = 800 + 210 + 2,
  1272. .htotal = 800 + 210 + 2 + 44,
  1273. .vdisplay = 480,
  1274. .vsync_start = 480 + 22,
  1275. .vsync_end = 480 + 22 + 2,
  1276. .vtotal = 480 + 22 + 2 + 21,
  1277. .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
  1278. };
  1279. static const struct panel_desc cdtech_s070swv29hg_dc44 = {
  1280. .modes = &cdtech_s070swv29hg_dc44_mode,
  1281. .num_modes = 1,
  1282. .bpc = 6,
  1283. .size = {
  1284. .width = 154,
  1285. .height = 86,
  1286. },
  1287. .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
  1288. .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
  1289. .connector_type = DRM_MODE_CONNECTOR_DPI,
  1290. };
  1291. static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
  1292. .clock = 35000,
  1293. .hdisplay = 800,
  1294. .hsync_start = 800 + 40,
  1295. .hsync_end = 800 + 40 + 40,
  1296. .htotal = 800 + 40 + 40 + 48,
  1297. .vdisplay = 480,
  1298. .vsync_start = 480 + 29,
  1299. .vsync_end = 480 + 29 + 13,
  1300. .vtotal = 480 + 29 + 13 + 3,
  1301. .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
  1302. };
  1303. static const struct panel_desc cdtech_s070wv95_ct16 = {
  1304. .modes = &cdtech_s070wv95_ct16_mode,
  1305. .num_modes = 1,
  1306. .bpc = 8,
  1307. .size = {
  1308. .width = 154,
  1309. .height = 85,
  1310. },
  1311. };
  1312. static const struct display_timing chefree_ch101olhlwh_002_timing = {
  1313. .pixelclock = { 68900000, 71100000, 73400000 },
  1314. .hactive = { 1280, 1280, 1280 },
  1315. .hfront_porch = { 65, 80, 95 },
  1316. .hback_porch = { 64, 79, 94 },
  1317. .hsync_len = { 1, 1, 1 },
  1318. .vactive = { 800, 800, 800 },
  1319. .vfront_porch = { 7, 11, 14 },
  1320. .vback_porch = { 7, 11, 14 },
  1321. .vsync_len = { 1, 1, 1 },
  1322. .flags = DISPLAY_FLAGS_DE_HIGH,
  1323. };
  1324. static const struct panel_desc chefree_ch101olhlwh_002 = {
  1325. .timings = &chefree_ch101olhlwh_002_timing,
  1326. .num_timings = 1,
  1327. .bpc = 8,
  1328. .size = {
  1329. .width = 217,
  1330. .height = 135,
  1331. },
  1332. .delay = {
  1333. .enable = 200,
  1334. .disable = 200,
  1335. },
  1336. .bus_flags = DRM_BUS_FLAG_DE_HIGH,
  1337. .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
  1338. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  1339. };
  1340. static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
  1341. .clock = 66770,
  1342. .hdisplay = 800,
  1343. .hsync_start = 800 + 49,
  1344. .hsync_end = 800 + 49 + 33,
  1345. .htotal = 800 + 49 + 33 + 17,
  1346. .vdisplay = 1280,
  1347. .vsync_start = 1280 + 1,
  1348. .vsync_end = 1280 + 1 + 7,
  1349. .vtotal = 1280 + 1 + 7 + 15,
  1350. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  1351. };
  1352. static const struct panel_desc chunghwa_claa070wp03xg = {
  1353. .modes = &chunghwa_claa070wp03xg_mode,
  1354. .num_modes = 1,
  1355. .bpc = 6,
  1356. .size = {
  1357. .width = 94,
  1358. .height = 150,
  1359. },
  1360. .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
  1361. .bus_flags = DRM_BUS_FLAG_DE_HIGH,
  1362. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  1363. };
  1364. static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
  1365. .clock = 72070,
  1366. .hdisplay = 1366,
  1367. .hsync_start = 1366 + 58,
  1368. .hsync_end = 1366 + 58 + 58,
  1369. .htotal = 1366 + 58 + 58 + 58,
  1370. .vdisplay = 768,
  1371. .vsync_start = 768 + 4,
  1372. .vsync_end = 768 + 4 + 4,
  1373. .vtotal = 768 + 4 + 4 + 4,
  1374. };
  1375. static const struct panel_desc chunghwa_claa101wa01a = {
  1376. .modes = &chunghwa_claa101wa01a_mode,
  1377. .num_modes = 1,
  1378. .bpc = 6,
  1379. .size = {
  1380. .width = 220,
  1381. .height = 120,
  1382. },
  1383. .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
  1384. .bus_flags = DRM_BUS_FLAG_DE_HIGH,
  1385. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  1386. };
  1387. static const struct drm_display_mode chunghwa_claa101wb01_mode = {
  1388. .clock = 69300,
  1389. .hdisplay = 1366,
  1390. .hsync_start = 1366 + 48,
  1391. .hsync_end = 1366 + 48 + 32,
  1392. .htotal = 1366 + 48 + 32 + 20,
  1393. .vdisplay = 768,
  1394. .vsync_start = 768 + 16,
  1395. .vsync_end = 768 + 16 + 8,
  1396. .vtotal = 768 + 16 + 8 + 16,
  1397. };
  1398. static const struct panel_desc chunghwa_claa101wb01 = {
  1399. .modes = &chunghwa_claa101wb01_mode,
  1400. .num_modes = 1,
  1401. .bpc = 6,
  1402. .size = {
  1403. .width = 223,
  1404. .height = 125,
  1405. },
  1406. .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
  1407. .bus_flags = DRM_BUS_FLAG_DE_HIGH,
  1408. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  1409. };
  1410. static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
  1411. .clock = 33260,
  1412. .hdisplay = 800,
  1413. .hsync_start = 800 + 40,
  1414. .hsync_end = 800 + 40 + 128,
  1415. .htotal = 800 + 40 + 128 + 88,
  1416. .vdisplay = 480,
  1417. .vsync_start = 480 + 10,
  1418. .vsync_end = 480 + 10 + 2,
  1419. .vtotal = 480 + 10 + 2 + 33,
  1420. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  1421. };
  1422. static const struct panel_desc dataimage_scf0700c48ggu18 = {
  1423. .modes = &dataimage_scf0700c48ggu18_mode,
  1424. .num_modes = 1,
  1425. .bpc = 8,
  1426. .size = {
  1427. .width = 152,
  1428. .height = 91,
  1429. },
  1430. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  1431. .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
  1432. };
  1433. static const struct display_timing dlc_dlc0700yzg_1_timing = {
  1434. .pixelclock = { 45000000, 51200000, 57000000 },
  1435. .hactive = { 1024, 1024, 1024 },
  1436. .hfront_porch = { 100, 106, 113 },
  1437. .hback_porch = { 100, 106, 113 },
  1438. .hsync_len = { 100, 108, 114 },
  1439. .vactive = { 600, 600, 600 },
  1440. .vfront_porch = { 8, 11, 15 },
  1441. .vback_porch = { 8, 11, 15 },
  1442. .vsync_len = { 9, 13, 15 },
  1443. .flags = DISPLAY_FLAGS_DE_HIGH,
  1444. };
  1445. static const struct panel_desc dlc_dlc0700yzg_1 = {
  1446. .timings = &dlc_dlc0700yzg_1_timing,
  1447. .num_timings = 1,
  1448. .bpc = 6,
  1449. .size = {
  1450. .width = 154,
  1451. .height = 86,
  1452. },
  1453. .delay = {
  1454. .prepare = 30,
  1455. .enable = 200,
  1456. .disable = 200,
  1457. },
  1458. .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
  1459. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  1460. };
  1461. static const struct display_timing dlc_dlc1010gig_timing = {
  1462. .pixelclock = { 68900000, 71100000, 73400000 },
  1463. .hactive = { 1280, 1280, 1280 },
  1464. .hfront_porch = { 43, 53, 63 },
  1465. .hback_porch = { 43, 53, 63 },
  1466. .hsync_len = { 44, 54, 64 },
  1467. .vactive = { 800, 800, 800 },
  1468. .vfront_porch = { 5, 8, 11 },
  1469. .vback_porch = { 5, 8, 11 },
  1470. .vsync_len = { 5, 7, 11 },
  1471. .flags = DISPLAY_FLAGS_DE_HIGH,
  1472. };
  1473. static const struct panel_desc dlc_dlc1010gig = {
  1474. .timings = &dlc_dlc1010gig_timing,
  1475. .num_timings = 1,
  1476. .bpc = 8,
  1477. .size = {
  1478. .width = 216,
  1479. .height = 135,
  1480. },
  1481. .delay = {
  1482. .prepare = 60,
  1483. .enable = 150,
  1484. .disable = 100,
  1485. .unprepare = 60,
  1486. },
  1487. .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
  1488. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  1489. };
  1490. static const struct drm_display_mode edt_et035012dm6_mode = {
  1491. .clock = 6500,
  1492. .hdisplay = 320,
  1493. .hsync_start = 320 + 20,
  1494. .hsync_end = 320 + 20 + 30,
  1495. .htotal = 320 + 20 + 68,
  1496. .vdisplay = 240,
  1497. .vsync_start = 240 + 4,
  1498. .vsync_end = 240 + 4 + 4,
  1499. .vtotal = 240 + 4 + 4 + 14,
  1500. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  1501. };
  1502. static const struct panel_desc edt_et035012dm6 = {
  1503. .modes = &edt_et035012dm6_mode,
  1504. .num_modes = 1,
  1505. .bpc = 8,
  1506. .size = {
  1507. .width = 70,
  1508. .height = 52,
  1509. },
  1510. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  1511. .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
  1512. };
  1513. static const struct drm_display_mode edt_etm043080dh6gp_mode = {
  1514. .clock = 10870,
  1515. .hdisplay = 480,
  1516. .hsync_start = 480 + 8,
  1517. .hsync_end = 480 + 8 + 4,
  1518. .htotal = 480 + 8 + 4 + 41,
  1519. /*
  1520. * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
  1521. * fb_align
  1522. */
  1523. .vdisplay = 288,
  1524. .vsync_start = 288 + 2,
  1525. .vsync_end = 288 + 2 + 4,
  1526. .vtotal = 288 + 2 + 4 + 10,
  1527. };
  1528. static const struct panel_desc edt_etm043080dh6gp = {
  1529. .modes = &edt_etm043080dh6gp_mode,
  1530. .num_modes = 1,
  1531. .bpc = 8,
  1532. .size = {
  1533. .width = 100,
  1534. .height = 65,
  1535. },
  1536. .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
  1537. .connector_type = DRM_MODE_CONNECTOR_DPI,
  1538. };
  1539. static const struct drm_display_mode edt_etm0430g0dh6_mode = {
  1540. .clock = 9000,
  1541. .hdisplay = 480,
  1542. .hsync_start = 480 + 2,
  1543. .hsync_end = 480 + 2 + 41,
  1544. .htotal = 480 + 2 + 41 + 2,
  1545. .vdisplay = 272,
  1546. .vsync_start = 272 + 2,
  1547. .vsync_end = 272 + 2 + 10,
  1548. .vtotal = 272 + 2 + 10 + 2,
  1549. .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
  1550. };
  1551. static const struct panel_desc edt_etm0430g0dh6 = {
  1552. .modes = &edt_etm0430g0dh6_mode,
  1553. .num_modes = 1,
  1554. .bpc = 6,
  1555. .size = {
  1556. .width = 95,
  1557. .height = 54,
  1558. },
  1559. };
  1560. static const struct drm_display_mode edt_et057090dhu_mode = {
  1561. .clock = 25175,
  1562. .hdisplay = 640,
  1563. .hsync_start = 640 + 16,
  1564. .hsync_end = 640 + 16 + 30,
  1565. .htotal = 640 + 16 + 30 + 114,
  1566. .vdisplay = 480,
  1567. .vsync_start = 480 + 10,
  1568. .vsync_end = 480 + 10 + 3,
  1569. .vtotal = 480 + 10 + 3 + 32,
  1570. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  1571. };
  1572. static const struct panel_desc edt_et057090dhu = {
  1573. .modes = &edt_et057090dhu_mode,
  1574. .num_modes = 1,
  1575. .bpc = 6,
  1576. .size = {
  1577. .width = 115,
  1578. .height = 86,
  1579. },
  1580. .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
  1581. .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
  1582. .connector_type = DRM_MODE_CONNECTOR_DPI,
  1583. };
  1584. static const struct drm_display_mode edt_etm0700g0dh6_mode = {
  1585. .clock = 33260,
  1586. .hdisplay = 800,
  1587. .hsync_start = 800 + 40,
  1588. .hsync_end = 800 + 40 + 128,
  1589. .htotal = 800 + 40 + 128 + 88,
  1590. .vdisplay = 480,
  1591. .vsync_start = 480 + 10,
  1592. .vsync_end = 480 + 10 + 2,
  1593. .vtotal = 480 + 10 + 2 + 33,
  1594. .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
  1595. };
  1596. static const struct panel_desc edt_etm0700g0dh6 = {
  1597. .modes = &edt_etm0700g0dh6_mode,
  1598. .num_modes = 1,
  1599. .bpc = 6,
  1600. .size = {
  1601. .width = 152,
  1602. .height = 91,
  1603. },
  1604. .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
  1605. .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
  1606. };
  1607. static const struct panel_desc edt_etm0700g0bdh6 = {
  1608. .modes = &edt_etm0700g0dh6_mode,
  1609. .num_modes = 1,
  1610. .bpc = 6,
  1611. .size = {
  1612. .width = 152,
  1613. .height = 91,
  1614. },
  1615. .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
  1616. .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
  1617. };
  1618. static const struct display_timing evervision_vgg804821_timing = {
  1619. .pixelclock = { 27600000, 33300000, 50000000 },
  1620. .hactive = { 800, 800, 800 },
  1621. .hfront_porch = { 40, 66, 70 },
  1622. .hback_porch = { 40, 67, 70 },
  1623. .hsync_len = { 40, 67, 70 },
  1624. .vactive = { 480, 480, 480 },
  1625. .vfront_porch = { 6, 10, 10 },
  1626. .vback_porch = { 7, 11, 11 },
  1627. .vsync_len = { 7, 11, 11 },
  1628. .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
  1629. DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
  1630. DISPLAY_FLAGS_SYNC_NEGEDGE,
  1631. };
  1632. static const struct panel_desc evervision_vgg804821 = {
  1633. .timings = &evervision_vgg804821_timing,
  1634. .num_timings = 1,
  1635. .bpc = 8,
  1636. .size = {
  1637. .width = 108,
  1638. .height = 64,
  1639. },
  1640. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  1641. .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
  1642. };
  1643. static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
  1644. .clock = 32260,
  1645. .hdisplay = 800,
  1646. .hsync_start = 800 + 168,
  1647. .hsync_end = 800 + 168 + 64,
  1648. .htotal = 800 + 168 + 64 + 88,
  1649. .vdisplay = 480,
  1650. .vsync_start = 480 + 37,
  1651. .vsync_end = 480 + 37 + 2,
  1652. .vtotal = 480 + 37 + 2 + 8,
  1653. };
  1654. static const struct panel_desc foxlink_fl500wvr00_a0t = {
  1655. .modes = &foxlink_fl500wvr00_a0t_mode,
  1656. .num_modes = 1,
  1657. .bpc = 8,
  1658. .size = {
  1659. .width = 108,
  1660. .height = 65,
  1661. },
  1662. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  1663. };
  1664. static const struct drm_display_mode frida_frd350h54004_modes[] = {
  1665. { /* 60 Hz */
  1666. .clock = 6000,
  1667. .hdisplay = 320,
  1668. .hsync_start = 320 + 44,
  1669. .hsync_end = 320 + 44 + 16,
  1670. .htotal = 320 + 44 + 16 + 20,
  1671. .vdisplay = 240,
  1672. .vsync_start = 240 + 2,
  1673. .vsync_end = 240 + 2 + 6,
  1674. .vtotal = 240 + 2 + 6 + 2,
  1675. .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
  1676. },
  1677. { /* 50 Hz */
  1678. .clock = 5400,
  1679. .hdisplay = 320,
  1680. .hsync_start = 320 + 56,
  1681. .hsync_end = 320 + 56 + 16,
  1682. .htotal = 320 + 56 + 16 + 40,
  1683. .vdisplay = 240,
  1684. .vsync_start = 240 + 2,
  1685. .vsync_end = 240 + 2 + 6,
  1686. .vtotal = 240 + 2 + 6 + 2,
  1687. .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
  1688. },
  1689. };
  1690. static const struct panel_desc frida_frd350h54004 = {
  1691. .modes = frida_frd350h54004_modes,
  1692. .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
  1693. .bpc = 8,
  1694. .size = {
  1695. .width = 77,
  1696. .height = 64,
  1697. },
  1698. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  1699. .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
  1700. .connector_type = DRM_MODE_CONNECTOR_DPI,
  1701. };
  1702. static const struct drm_display_mode friendlyarm_hd702e_mode = {
  1703. .clock = 67185,
  1704. .hdisplay = 800,
  1705. .hsync_start = 800 + 20,
  1706. .hsync_end = 800 + 20 + 24,
  1707. .htotal = 800 + 20 + 24 + 20,
  1708. .vdisplay = 1280,
  1709. .vsync_start = 1280 + 4,
  1710. .vsync_end = 1280 + 4 + 8,
  1711. .vtotal = 1280 + 4 + 8 + 4,
  1712. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  1713. };
  1714. static const struct panel_desc friendlyarm_hd702e = {
  1715. .modes = &friendlyarm_hd702e_mode,
  1716. .num_modes = 1,
  1717. .size = {
  1718. .width = 94,
  1719. .height = 151,
  1720. },
  1721. };
  1722. static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
  1723. .clock = 9000,
  1724. .hdisplay = 480,
  1725. .hsync_start = 480 + 5,
  1726. .hsync_end = 480 + 5 + 1,
  1727. .htotal = 480 + 5 + 1 + 40,
  1728. .vdisplay = 272,
  1729. .vsync_start = 272 + 8,
  1730. .vsync_end = 272 + 8 + 1,
  1731. .vtotal = 272 + 8 + 1 + 8,
  1732. };
  1733. static const struct panel_desc giantplus_gpg482739qs5 = {
  1734. .modes = &giantplus_gpg482739qs5_mode,
  1735. .num_modes = 1,
  1736. .bpc = 8,
  1737. .size = {
  1738. .width = 95,
  1739. .height = 54,
  1740. },
  1741. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  1742. };
  1743. static const struct display_timing giantplus_gpm940b0_timing = {
  1744. .pixelclock = { 13500000, 27000000, 27500000 },
  1745. .hactive = { 320, 320, 320 },
  1746. .hfront_porch = { 14, 686, 718 },
  1747. .hback_porch = { 50, 70, 255 },
  1748. .hsync_len = { 1, 1, 1 },
  1749. .vactive = { 240, 240, 240 },
  1750. .vfront_porch = { 1, 1, 179 },
  1751. .vback_porch = { 1, 21, 31 },
  1752. .vsync_len = { 1, 1, 6 },
  1753. .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
  1754. };
  1755. static const struct panel_desc giantplus_gpm940b0 = {
  1756. .timings = &giantplus_gpm940b0_timing,
  1757. .num_timings = 1,
  1758. .bpc = 8,
  1759. .size = {
  1760. .width = 60,
  1761. .height = 45,
  1762. },
  1763. .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
  1764. .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
  1765. };
  1766. static const struct display_timing hannstar_hsd070pww1_timing = {
  1767. .pixelclock = { 64300000, 71100000, 82000000 },
  1768. .hactive = { 1280, 1280, 1280 },
  1769. .hfront_porch = { 1, 1, 10 },
  1770. .hback_porch = { 1, 1, 10 },
  1771. /*
  1772. * According to the data sheet, the minimum horizontal blanking interval
  1773. * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
  1774. * minimum working horizontal blanking interval to be 60 clocks.
  1775. */
  1776. .hsync_len = { 58, 158, 661 },
  1777. .vactive = { 800, 800, 800 },
  1778. .vfront_porch = { 1, 1, 10 },
  1779. .vback_porch = { 1, 1, 10 },
  1780. .vsync_len = { 1, 21, 203 },
  1781. .flags = DISPLAY_FLAGS_DE_HIGH,
  1782. };
  1783. static const struct panel_desc hannstar_hsd070pww1 = {
  1784. .timings = &hannstar_hsd070pww1_timing,
  1785. .num_timings = 1,
  1786. .bpc = 6,
  1787. .size = {
  1788. .width = 151,
  1789. .height = 94,
  1790. },
  1791. .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
  1792. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  1793. };
  1794. static const struct display_timing hannstar_hsd100pxn1_timing = {
  1795. .pixelclock = { 55000000, 65000000, 75000000 },
  1796. .hactive = { 1024, 1024, 1024 },
  1797. .hfront_porch = { 40, 40, 40 },
  1798. .hback_porch = { 220, 220, 220 },
  1799. .hsync_len = { 20, 60, 100 },
  1800. .vactive = { 768, 768, 768 },
  1801. .vfront_porch = { 7, 7, 7 },
  1802. .vback_porch = { 21, 21, 21 },
  1803. .vsync_len = { 10, 10, 10 },
  1804. .flags = DISPLAY_FLAGS_DE_HIGH,
  1805. };
  1806. static const struct panel_desc hannstar_hsd100pxn1 = {
  1807. .timings = &hannstar_hsd100pxn1_timing,
  1808. .num_timings = 1,
  1809. .bpc = 6,
  1810. .size = {
  1811. .width = 203,
  1812. .height = 152,
  1813. },
  1814. .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
  1815. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  1816. };
  1817. static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
  1818. .clock = 33333,
  1819. .hdisplay = 800,
  1820. .hsync_start = 800 + 85,
  1821. .hsync_end = 800 + 85 + 86,
  1822. .htotal = 800 + 85 + 86 + 85,
  1823. .vdisplay = 480,
  1824. .vsync_start = 480 + 16,
  1825. .vsync_end = 480 + 16 + 13,
  1826. .vtotal = 480 + 16 + 13 + 16,
  1827. };
  1828. static const struct panel_desc hitachi_tx23d38vm0caa = {
  1829. .modes = &hitachi_tx23d38vm0caa_mode,
  1830. .num_modes = 1,
  1831. .bpc = 6,
  1832. .size = {
  1833. .width = 195,
  1834. .height = 117,
  1835. },
  1836. .delay = {
  1837. .enable = 160,
  1838. .disable = 160,
  1839. },
  1840. };
  1841. static const struct drm_display_mode innolux_at043tn24_mode = {
  1842. .clock = 9000,
  1843. .hdisplay = 480,
  1844. .hsync_start = 480 + 2,
  1845. .hsync_end = 480 + 2 + 41,
  1846. .htotal = 480 + 2 + 41 + 2,
  1847. .vdisplay = 272,
  1848. .vsync_start = 272 + 2,
  1849. .vsync_end = 272 + 2 + 10,
  1850. .vtotal = 272 + 2 + 10 + 2,
  1851. .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
  1852. };
  1853. static const struct panel_desc innolux_at043tn24 = {
  1854. .modes = &innolux_at043tn24_mode,
  1855. .num_modes = 1,
  1856. .bpc = 8,
  1857. .size = {
  1858. .width = 95,
  1859. .height = 54,
  1860. },
  1861. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  1862. .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
  1863. };
  1864. static const struct drm_display_mode innolux_at070tn92_mode = {
  1865. .clock = 33333,
  1866. .hdisplay = 800,
  1867. .hsync_start = 800 + 210,
  1868. .hsync_end = 800 + 210 + 20,
  1869. .htotal = 800 + 210 + 20 + 46,
  1870. .vdisplay = 480,
  1871. .vsync_start = 480 + 22,
  1872. .vsync_end = 480 + 22 + 10,
  1873. .vtotal = 480 + 22 + 23 + 10,
  1874. };
  1875. static const struct panel_desc innolux_at070tn92 = {
  1876. .modes = &innolux_at070tn92_mode,
  1877. .num_modes = 1,
  1878. .size = {
  1879. .width = 154,
  1880. .height = 86,
  1881. },
  1882. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  1883. };
  1884. static const struct display_timing innolux_g070y2_l01_timing = {
  1885. .pixelclock = { 28000000, 29500000, 32000000 },
  1886. .hactive = { 800, 800, 800 },
  1887. .hfront_porch = { 61, 91, 141 },
  1888. .hback_porch = { 60, 90, 140 },
  1889. .hsync_len = { 12, 12, 12 },
  1890. .vactive = { 480, 480, 480 },
  1891. .vfront_porch = { 4, 9, 30 },
  1892. .vback_porch = { 4, 8, 28 },
  1893. .vsync_len = { 2, 2, 2 },
  1894. .flags = DISPLAY_FLAGS_DE_HIGH,
  1895. };
  1896. static const struct panel_desc innolux_g070y2_l01 = {
  1897. .timings = &innolux_g070y2_l01_timing,
  1898. .num_timings = 1,
  1899. .bpc = 8,
  1900. .size = {
  1901. .width = 152,
  1902. .height = 91,
  1903. },
  1904. .delay = {
  1905. .prepare = 10,
  1906. .enable = 100,
  1907. .disable = 100,
  1908. .unprepare = 800,
  1909. },
  1910. .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
  1911. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  1912. };
  1913. static const struct display_timing innolux_g101ice_l01_timing = {
  1914. .pixelclock = { 60400000, 71100000, 74700000 },
  1915. .hactive = { 1280, 1280, 1280 },
  1916. .hfront_porch = { 41, 80, 100 },
  1917. .hback_porch = { 40, 79, 99 },
  1918. .hsync_len = { 1, 1, 1 },
  1919. .vactive = { 800, 800, 800 },
  1920. .vfront_porch = { 5, 11, 14 },
  1921. .vback_porch = { 4, 11, 14 },
  1922. .vsync_len = { 1, 1, 1 },
  1923. .flags = DISPLAY_FLAGS_DE_HIGH,
  1924. };
  1925. static const struct panel_desc innolux_g101ice_l01 = {
  1926. .timings = &innolux_g101ice_l01_timing,
  1927. .num_timings = 1,
  1928. .bpc = 8,
  1929. .size = {
  1930. .width = 217,
  1931. .height = 135,
  1932. },
  1933. .delay = {
  1934. .enable = 200,
  1935. .disable = 200,
  1936. },
  1937. .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
  1938. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  1939. };
  1940. static const struct display_timing innolux_g121i1_l01_timing = {
  1941. .pixelclock = { 67450000, 71000000, 74550000 },
  1942. .hactive = { 1280, 1280, 1280 },
  1943. .hfront_porch = { 40, 80, 160 },
  1944. .hback_porch = { 39, 79, 159 },
  1945. .hsync_len = { 1, 1, 1 },
  1946. .vactive = { 800, 800, 800 },
  1947. .vfront_porch = { 5, 11, 100 },
  1948. .vback_porch = { 4, 11, 99 },
  1949. .vsync_len = { 1, 1, 1 },
  1950. };
  1951. static const struct panel_desc innolux_g121i1_l01 = {
  1952. .timings = &innolux_g121i1_l01_timing,
  1953. .num_timings = 1,
  1954. .bpc = 6,
  1955. .size = {
  1956. .width = 261,
  1957. .height = 163,
  1958. },
  1959. .delay = {
  1960. .enable = 200,
  1961. .disable = 20,
  1962. },
  1963. .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
  1964. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  1965. };
  1966. static const struct drm_display_mode innolux_g121x1_l03_mode = {
  1967. .clock = 65000,
  1968. .hdisplay = 1024,
  1969. .hsync_start = 1024 + 0,
  1970. .hsync_end = 1024 + 1,
  1971. .htotal = 1024 + 0 + 1 + 320,
  1972. .vdisplay = 768,
  1973. .vsync_start = 768 + 38,
  1974. .vsync_end = 768 + 38 + 1,
  1975. .vtotal = 768 + 38 + 1 + 0,
  1976. .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
  1977. };
  1978. static const struct panel_desc innolux_g121x1_l03 = {
  1979. .modes = &innolux_g121x1_l03_mode,
  1980. .num_modes = 1,
  1981. .bpc = 6,
  1982. .size = {
  1983. .width = 246,
  1984. .height = 185,
  1985. },
  1986. .delay = {
  1987. .enable = 200,
  1988. .unprepare = 200,
  1989. .disable = 400,
  1990. },
  1991. };
  1992. /*
  1993. * Datasheet specifies that at 60 Hz refresh rate:
  1994. * - total horizontal time: { 1506, 1592, 1716 }
  1995. * - total vertical time: { 788, 800, 868 }
  1996. *
  1997. * ...but doesn't go into exactly how that should be split into a front
  1998. * porch, back porch, or sync length. For now we'll leave a single setting
  1999. * here which allows a bit of tweaking of the pixel clock at the expense of
  2000. * refresh rate.
  2001. */
  2002. static const struct display_timing innolux_n116bge_timing = {
  2003. .pixelclock = { 72600000, 76420000, 80240000 },
  2004. .hactive = { 1366, 1366, 1366 },
  2005. .hfront_porch = { 136, 136, 136 },
  2006. .hback_porch = { 60, 60, 60 },
  2007. .hsync_len = { 30, 30, 30 },
  2008. .vactive = { 768, 768, 768 },
  2009. .vfront_porch = { 8, 8, 8 },
  2010. .vback_porch = { 12, 12, 12 },
  2011. .vsync_len = { 12, 12, 12 },
  2012. .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
  2013. };
  2014. static const struct panel_desc innolux_n116bge = {
  2015. .timings = &innolux_n116bge_timing,
  2016. .num_timings = 1,
  2017. .bpc = 6,
  2018. .size = {
  2019. .width = 256,
  2020. .height = 144,
  2021. },
  2022. };
  2023. static const struct drm_display_mode innolux_n156bge_l21_mode = {
  2024. .clock = 69300,
  2025. .hdisplay = 1366,
  2026. .hsync_start = 1366 + 16,
  2027. .hsync_end = 1366 + 16 + 34,
  2028. .htotal = 1366 + 16 + 34 + 50,
  2029. .vdisplay = 768,
  2030. .vsync_start = 768 + 2,
  2031. .vsync_end = 768 + 2 + 6,
  2032. .vtotal = 768 + 2 + 6 + 12,
  2033. };
  2034. static const struct panel_desc innolux_n156bge_l21 = {
  2035. .modes = &innolux_n156bge_l21_mode,
  2036. .num_modes = 1,
  2037. .bpc = 6,
  2038. .size = {
  2039. .width = 344,
  2040. .height = 193,
  2041. },
  2042. .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
  2043. .bus_flags = DRM_BUS_FLAG_DE_HIGH,
  2044. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  2045. };
  2046. static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
  2047. .clock = 206016,
  2048. .hdisplay = 2160,
  2049. .hsync_start = 2160 + 48,
  2050. .hsync_end = 2160 + 48 + 32,
  2051. .htotal = 2160 + 48 + 32 + 80,
  2052. .vdisplay = 1440,
  2053. .vsync_start = 1440 + 3,
  2054. .vsync_end = 1440 + 3 + 10,
  2055. .vtotal = 1440 + 3 + 10 + 27,
  2056. .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
  2057. };
  2058. static const struct panel_desc innolux_p120zdg_bf1 = {
  2059. .modes = &innolux_p120zdg_bf1_mode,
  2060. .num_modes = 1,
  2061. .bpc = 8,
  2062. .size = {
  2063. .width = 254,
  2064. .height = 169,
  2065. },
  2066. .delay = {
  2067. .hpd_absent_delay = 200,
  2068. .unprepare = 500,
  2069. },
  2070. };
  2071. static const struct drm_display_mode innolux_zj070na_01p_mode = {
  2072. .clock = 51501,
  2073. .hdisplay = 1024,
  2074. .hsync_start = 1024 + 128,
  2075. .hsync_end = 1024 + 128 + 64,
  2076. .htotal = 1024 + 128 + 64 + 128,
  2077. .vdisplay = 600,
  2078. .vsync_start = 600 + 16,
  2079. .vsync_end = 600 + 16 + 4,
  2080. .vtotal = 600 + 16 + 4 + 16,
  2081. };
  2082. static const struct panel_desc innolux_zj070na_01p = {
  2083. .modes = &innolux_zj070na_01p_mode,
  2084. .num_modes = 1,
  2085. .bpc = 6,
  2086. .size = {
  2087. .width = 154,
  2088. .height = 90,
  2089. },
  2090. };
  2091. static const struct drm_display_mode ivo_m133nwf4_r0_mode = {
  2092. .clock = 138778,
  2093. .hdisplay = 1920,
  2094. .hsync_start = 1920 + 24,
  2095. .hsync_end = 1920 + 24 + 48,
  2096. .htotal = 1920 + 24 + 48 + 88,
  2097. .vdisplay = 1080,
  2098. .vsync_start = 1080 + 3,
  2099. .vsync_end = 1080 + 3 + 12,
  2100. .vtotal = 1080 + 3 + 12 + 17,
  2101. .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
  2102. };
  2103. static const struct panel_desc ivo_m133nwf4_r0 = {
  2104. .modes = &ivo_m133nwf4_r0_mode,
  2105. .num_modes = 1,
  2106. .bpc = 8,
  2107. .size = {
  2108. .width = 294,
  2109. .height = 165,
  2110. },
  2111. .delay = {
  2112. .hpd_absent_delay = 200,
  2113. .unprepare = 500,
  2114. },
  2115. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  2116. .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
  2117. .connector_type = DRM_MODE_CONNECTOR_eDP,
  2118. };
  2119. static const struct drm_display_mode kingdisplay_kd116n21_30nv_a010_mode = {
  2120. .clock = 81000,
  2121. .hdisplay = 1366,
  2122. .hsync_start = 1366 + 40,
  2123. .hsync_end = 1366 + 40 + 32,
  2124. .htotal = 1366 + 40 + 32 + 62,
  2125. .vdisplay = 768,
  2126. .vsync_start = 768 + 5,
  2127. .vsync_end = 768 + 5 + 5,
  2128. .vtotal = 768 + 5 + 5 + 122,
  2129. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  2130. };
  2131. static const struct panel_desc kingdisplay_kd116n21_30nv_a010 = {
  2132. .modes = &kingdisplay_kd116n21_30nv_a010_mode,
  2133. .num_modes = 1,
  2134. .bpc = 6,
  2135. .size = {
  2136. .width = 256,
  2137. .height = 144,
  2138. },
  2139. .delay = {
  2140. .hpd_absent_delay = 200,
  2141. },
  2142. .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
  2143. .connector_type = DRM_MODE_CONNECTOR_eDP,
  2144. };
  2145. static const struct display_timing koe_tx14d24vm1bpa_timing = {
  2146. .pixelclock = { 5580000, 5850000, 6200000 },
  2147. .hactive = { 320, 320, 320 },
  2148. .hfront_porch = { 30, 30, 30 },
  2149. .hback_porch = { 30, 30, 30 },
  2150. .hsync_len = { 1, 5, 17 },
  2151. .vactive = { 240, 240, 240 },
  2152. .vfront_porch = { 6, 6, 6 },
  2153. .vback_porch = { 5, 5, 5 },
  2154. .vsync_len = { 1, 2, 11 },
  2155. .flags = DISPLAY_FLAGS_DE_HIGH,
  2156. };
  2157. static const struct panel_desc koe_tx14d24vm1bpa = {
  2158. .timings = &koe_tx14d24vm1bpa_timing,
  2159. .num_timings = 1,
  2160. .bpc = 6,
  2161. .size = {
  2162. .width = 115,
  2163. .height = 86,
  2164. },
  2165. };
  2166. static const struct display_timing koe_tx26d202vm0bwa_timing = {
  2167. .pixelclock = { 151820000, 156720000, 159780000 },
  2168. .hactive = { 1920, 1920, 1920 },
  2169. .hfront_porch = { 105, 130, 142 },
  2170. .hback_porch = { 45, 70, 82 },
  2171. .hsync_len = { 30, 30, 30 },
  2172. .vactive = { 1200, 1200, 1200},
  2173. .vfront_porch = { 3, 5, 10 },
  2174. .vback_porch = { 2, 5, 10 },
  2175. .vsync_len = { 5, 5, 5 },
  2176. };
  2177. static const struct panel_desc koe_tx26d202vm0bwa = {
  2178. .timings = &koe_tx26d202vm0bwa_timing,
  2179. .num_timings = 1,
  2180. .bpc = 8,
  2181. .size = {
  2182. .width = 217,
  2183. .height = 136,
  2184. },
  2185. .delay = {
  2186. .prepare = 1000,
  2187. .enable = 1000,
  2188. .unprepare = 1000,
  2189. .disable = 1000,
  2190. },
  2191. .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
  2192. .bus_flags = DRM_BUS_FLAG_DE_HIGH,
  2193. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  2194. };
  2195. static const struct display_timing koe_tx31d200vm0baa_timing = {
  2196. .pixelclock = { 39600000, 43200000, 48000000 },
  2197. .hactive = { 1280, 1280, 1280 },
  2198. .hfront_porch = { 16, 36, 56 },
  2199. .hback_porch = { 16, 36, 56 },
  2200. .hsync_len = { 8, 8, 8 },
  2201. .vactive = { 480, 480, 480 },
  2202. .vfront_porch = { 6, 21, 33 },
  2203. .vback_porch = { 6, 21, 33 },
  2204. .vsync_len = { 8, 8, 8 },
  2205. .flags = DISPLAY_FLAGS_DE_HIGH,
  2206. };
  2207. static const struct panel_desc koe_tx31d200vm0baa = {
  2208. .timings = &koe_tx31d200vm0baa_timing,
  2209. .num_timings = 1,
  2210. .bpc = 6,
  2211. .size = {
  2212. .width = 292,
  2213. .height = 109,
  2214. },
  2215. .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
  2216. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  2217. };
  2218. static const struct display_timing kyo_tcg121xglp_timing = {
  2219. .pixelclock = { 52000000, 65000000, 71000000 },
  2220. .hactive = { 1024, 1024, 1024 },
  2221. .hfront_porch = { 2, 2, 2 },
  2222. .hback_porch = { 2, 2, 2 },
  2223. .hsync_len = { 86, 124, 244 },
  2224. .vactive = { 768, 768, 768 },
  2225. .vfront_porch = { 2, 2, 2 },
  2226. .vback_porch = { 2, 2, 2 },
  2227. .vsync_len = { 6, 34, 73 },
  2228. .flags = DISPLAY_FLAGS_DE_HIGH,
  2229. };
  2230. static const struct panel_desc kyo_tcg121xglp = {
  2231. .timings = &kyo_tcg121xglp_timing,
  2232. .num_timings = 1,
  2233. .bpc = 8,
  2234. .size = {
  2235. .width = 246,
  2236. .height = 184,
  2237. },
  2238. .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
  2239. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  2240. };
  2241. static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
  2242. .clock = 7000,
  2243. .hdisplay = 320,
  2244. .hsync_start = 320 + 20,
  2245. .hsync_end = 320 + 20 + 30,
  2246. .htotal = 320 + 20 + 30 + 38,
  2247. .vdisplay = 240,
  2248. .vsync_start = 240 + 4,
  2249. .vsync_end = 240 + 4 + 3,
  2250. .vtotal = 240 + 4 + 3 + 15,
  2251. };
  2252. static const struct panel_desc lemaker_bl035_rgb_002 = {
  2253. .modes = &lemaker_bl035_rgb_002_mode,
  2254. .num_modes = 1,
  2255. .size = {
  2256. .width = 70,
  2257. .height = 52,
  2258. },
  2259. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  2260. .bus_flags = DRM_BUS_FLAG_DE_LOW,
  2261. };
  2262. static const struct drm_display_mode lg_lb070wv8_mode = {
  2263. .clock = 33246,
  2264. .hdisplay = 800,
  2265. .hsync_start = 800 + 88,
  2266. .hsync_end = 800 + 88 + 80,
  2267. .htotal = 800 + 88 + 80 + 88,
  2268. .vdisplay = 480,
  2269. .vsync_start = 480 + 10,
  2270. .vsync_end = 480 + 10 + 25,
  2271. .vtotal = 480 + 10 + 25 + 10,
  2272. };
  2273. static const struct panel_desc lg_lb070wv8 = {
  2274. .modes = &lg_lb070wv8_mode,
  2275. .num_modes = 1,
  2276. .bpc = 8,
  2277. .size = {
  2278. .width = 151,
  2279. .height = 91,
  2280. },
  2281. .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
  2282. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  2283. };
  2284. static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
  2285. .clock = 200000,
  2286. .hdisplay = 1536,
  2287. .hsync_start = 1536 + 12,
  2288. .hsync_end = 1536 + 12 + 16,
  2289. .htotal = 1536 + 12 + 16 + 48,
  2290. .vdisplay = 2048,
  2291. .vsync_start = 2048 + 8,
  2292. .vsync_end = 2048 + 8 + 4,
  2293. .vtotal = 2048 + 8 + 4 + 8,
  2294. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  2295. };
  2296. static const struct panel_desc lg_lp079qx1_sp0v = {
  2297. .modes = &lg_lp079qx1_sp0v_mode,
  2298. .num_modes = 1,
  2299. .size = {
  2300. .width = 129,
  2301. .height = 171,
  2302. },
  2303. };
  2304. static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
  2305. .clock = 205210,
  2306. .hdisplay = 2048,
  2307. .hsync_start = 2048 + 150,
  2308. .hsync_end = 2048 + 150 + 5,
  2309. .htotal = 2048 + 150 + 5 + 5,
  2310. .vdisplay = 1536,
  2311. .vsync_start = 1536 + 3,
  2312. .vsync_end = 1536 + 3 + 1,
  2313. .vtotal = 1536 + 3 + 1 + 9,
  2314. };
  2315. static const struct panel_desc lg_lp097qx1_spa1 = {
  2316. .modes = &lg_lp097qx1_spa1_mode,
  2317. .num_modes = 1,
  2318. .size = {
  2319. .width = 208,
  2320. .height = 147,
  2321. },
  2322. };
  2323. static const struct drm_display_mode lg_lp120up1_mode = {
  2324. .clock = 162300,
  2325. .hdisplay = 1920,
  2326. .hsync_start = 1920 + 40,
  2327. .hsync_end = 1920 + 40 + 40,
  2328. .htotal = 1920 + 40 + 40+ 80,
  2329. .vdisplay = 1280,
  2330. .vsync_start = 1280 + 4,
  2331. .vsync_end = 1280 + 4 + 4,
  2332. .vtotal = 1280 + 4 + 4 + 12,
  2333. };
  2334. static const struct panel_desc lg_lp120up1 = {
  2335. .modes = &lg_lp120up1_mode,
  2336. .num_modes = 1,
  2337. .bpc = 8,
  2338. .size = {
  2339. .width = 267,
  2340. .height = 183,
  2341. },
  2342. .connector_type = DRM_MODE_CONNECTOR_eDP,
  2343. };
  2344. static const struct drm_display_mode lg_lp129qe_mode = {
  2345. .clock = 285250,
  2346. .hdisplay = 2560,
  2347. .hsync_start = 2560 + 48,
  2348. .hsync_end = 2560 + 48 + 32,
  2349. .htotal = 2560 + 48 + 32 + 80,
  2350. .vdisplay = 1700,
  2351. .vsync_start = 1700 + 3,
  2352. .vsync_end = 1700 + 3 + 10,
  2353. .vtotal = 1700 + 3 + 10 + 36,
  2354. };
  2355. static const struct panel_desc lg_lp129qe = {
  2356. .modes = &lg_lp129qe_mode,
  2357. .num_modes = 1,
  2358. .bpc = 8,
  2359. .size = {
  2360. .width = 272,
  2361. .height = 181,
  2362. },
  2363. };
  2364. static const struct display_timing logictechno_lt161010_2nh_timing = {
  2365. .pixelclock = { 26400000, 33300000, 46800000 },
  2366. .hactive = { 800, 800, 800 },
  2367. .hfront_porch = { 16, 210, 354 },
  2368. .hback_porch = { 46, 46, 46 },
  2369. .hsync_len = { 1, 20, 40 },
  2370. .vactive = { 480, 480, 480 },
  2371. .vfront_porch = { 7, 22, 147 },
  2372. .vback_porch = { 23, 23, 23 },
  2373. .vsync_len = { 1, 10, 20 },
  2374. .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
  2375. DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
  2376. DISPLAY_FLAGS_SYNC_POSEDGE,
  2377. };
  2378. static const struct panel_desc logictechno_lt161010_2nh = {
  2379. .timings = &logictechno_lt161010_2nh_timing,
  2380. .num_timings = 1,
  2381. .size = {
  2382. .width = 154,
  2383. .height = 86,
  2384. },
  2385. .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
  2386. .bus_flags = DRM_BUS_FLAG_DE_HIGH |
  2387. DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
  2388. DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
  2389. .connector_type = DRM_MODE_CONNECTOR_DPI,
  2390. };
  2391. static const struct display_timing logictechno_lt170410_2whc_timing = {
  2392. .pixelclock = { 68900000, 71100000, 73400000 },
  2393. .hactive = { 1280, 1280, 1280 },
  2394. .hfront_porch = { 23, 60, 71 },
  2395. .hback_porch = { 23, 60, 71 },
  2396. .hsync_len = { 15, 40, 47 },
  2397. .vactive = { 800, 800, 800 },
  2398. .vfront_porch = { 5, 7, 10 },
  2399. .vback_porch = { 5, 7, 10 },
  2400. .vsync_len = { 6, 9, 12 },
  2401. .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
  2402. DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
  2403. DISPLAY_FLAGS_SYNC_POSEDGE,
  2404. };
  2405. static const struct panel_desc logictechno_lt170410_2whc = {
  2406. .timings = &logictechno_lt170410_2whc_timing,
  2407. .num_timings = 1,
  2408. .size = {
  2409. .width = 217,
  2410. .height = 136,
  2411. },
  2412. .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
  2413. .bus_flags = DRM_BUS_FLAG_DE_HIGH,
  2414. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  2415. };
  2416. static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
  2417. .clock = 30400,
  2418. .hdisplay = 800,
  2419. .hsync_start = 800 + 0,
  2420. .hsync_end = 800 + 1,
  2421. .htotal = 800 + 0 + 1 + 160,
  2422. .vdisplay = 480,
  2423. .vsync_start = 480 + 0,
  2424. .vsync_end = 480 + 48 + 1,
  2425. .vtotal = 480 + 48 + 1 + 0,
  2426. .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
  2427. };
  2428. static const struct drm_display_mode logicpd_type_28_mode = {
  2429. .clock = 9107,
  2430. .hdisplay = 480,
  2431. .hsync_start = 480 + 3,
  2432. .hsync_end = 480 + 3 + 42,
  2433. .htotal = 480 + 3 + 42 + 2,
  2434. .vdisplay = 272,
  2435. .vsync_start = 272 + 2,
  2436. .vsync_end = 272 + 2 + 11,
  2437. .vtotal = 272 + 2 + 11 + 3,
  2438. .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
  2439. };
  2440. static const struct panel_desc logicpd_type_28 = {
  2441. .modes = &logicpd_type_28_mode,
  2442. .num_modes = 1,
  2443. .bpc = 8,
  2444. .size = {
  2445. .width = 105,
  2446. .height = 67,
  2447. },
  2448. .delay = {
  2449. .prepare = 200,
  2450. .enable = 200,
  2451. .unprepare = 200,
  2452. .disable = 200,
  2453. },
  2454. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  2455. .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
  2456. DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
  2457. .connector_type = DRM_MODE_CONNECTOR_DPI,
  2458. };
  2459. static const struct panel_desc mitsubishi_aa070mc01 = {
  2460. .modes = &mitsubishi_aa070mc01_mode,
  2461. .num_modes = 1,
  2462. .bpc = 8,
  2463. .size = {
  2464. .width = 152,
  2465. .height = 91,
  2466. },
  2467. .delay = {
  2468. .enable = 200,
  2469. .unprepare = 200,
  2470. .disable = 400,
  2471. },
  2472. .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
  2473. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  2474. .bus_flags = DRM_BUS_FLAG_DE_HIGH,
  2475. };
  2476. static const struct display_timing nec_nl12880bc20_05_timing = {
  2477. .pixelclock = { 67000000, 71000000, 75000000 },
  2478. .hactive = { 1280, 1280, 1280 },
  2479. .hfront_porch = { 2, 30, 30 },
  2480. .hback_porch = { 6, 100, 100 },
  2481. .hsync_len = { 2, 30, 30 },
  2482. .vactive = { 800, 800, 800 },
  2483. .vfront_porch = { 5, 5, 5 },
  2484. .vback_porch = { 11, 11, 11 },
  2485. .vsync_len = { 7, 7, 7 },
  2486. };
  2487. static const struct panel_desc nec_nl12880bc20_05 = {
  2488. .timings = &nec_nl12880bc20_05_timing,
  2489. .num_timings = 1,
  2490. .bpc = 8,
  2491. .size = {
  2492. .width = 261,
  2493. .height = 163,
  2494. },
  2495. .delay = {
  2496. .enable = 50,
  2497. .disable = 50,
  2498. },
  2499. .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
  2500. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  2501. };
  2502. static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
  2503. .clock = 10870,
  2504. .hdisplay = 480,
  2505. .hsync_start = 480 + 2,
  2506. .hsync_end = 480 + 2 + 41,
  2507. .htotal = 480 + 2 + 41 + 2,
  2508. .vdisplay = 272,
  2509. .vsync_start = 272 + 2,
  2510. .vsync_end = 272 + 2 + 4,
  2511. .vtotal = 272 + 2 + 4 + 2,
  2512. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  2513. };
  2514. static const struct panel_desc nec_nl4827hc19_05b = {
  2515. .modes = &nec_nl4827hc19_05b_mode,
  2516. .num_modes = 1,
  2517. .bpc = 8,
  2518. .size = {
  2519. .width = 95,
  2520. .height = 54,
  2521. },
  2522. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  2523. .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
  2524. };
  2525. static const struct drm_display_mode netron_dy_e231732_mode = {
  2526. .clock = 66000,
  2527. .hdisplay = 1024,
  2528. .hsync_start = 1024 + 160,
  2529. .hsync_end = 1024 + 160 + 70,
  2530. .htotal = 1024 + 160 + 70 + 90,
  2531. .vdisplay = 600,
  2532. .vsync_start = 600 + 127,
  2533. .vsync_end = 600 + 127 + 20,
  2534. .vtotal = 600 + 127 + 20 + 3,
  2535. };
  2536. static const struct panel_desc netron_dy_e231732 = {
  2537. .modes = &netron_dy_e231732_mode,
  2538. .num_modes = 1,
  2539. .size = {
  2540. .width = 154,
  2541. .height = 87,
  2542. },
  2543. .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
  2544. };
  2545. static const struct drm_display_mode neweast_wjfh116008a_modes[] = {
  2546. {
  2547. .clock = 138500,
  2548. .hdisplay = 1920,
  2549. .hsync_start = 1920 + 48,
  2550. .hsync_end = 1920 + 48 + 32,
  2551. .htotal = 1920 + 48 + 32 + 80,
  2552. .vdisplay = 1080,
  2553. .vsync_start = 1080 + 3,
  2554. .vsync_end = 1080 + 3 + 5,
  2555. .vtotal = 1080 + 3 + 5 + 23,
  2556. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  2557. }, {
  2558. .clock = 110920,
  2559. .hdisplay = 1920,
  2560. .hsync_start = 1920 + 48,
  2561. .hsync_end = 1920 + 48 + 32,
  2562. .htotal = 1920 + 48 + 32 + 80,
  2563. .vdisplay = 1080,
  2564. .vsync_start = 1080 + 3,
  2565. .vsync_end = 1080 + 3 + 5,
  2566. .vtotal = 1080 + 3 + 5 + 23,
  2567. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  2568. }
  2569. };
  2570. static const struct panel_desc neweast_wjfh116008a = {
  2571. .modes = neweast_wjfh116008a_modes,
  2572. .num_modes = 2,
  2573. .bpc = 6,
  2574. .size = {
  2575. .width = 260,
  2576. .height = 150,
  2577. },
  2578. .delay = {
  2579. .prepare = 110,
  2580. .enable = 20,
  2581. .unprepare = 500,
  2582. },
  2583. .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
  2584. .connector_type = DRM_MODE_CONNECTOR_eDP,
  2585. };
  2586. static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
  2587. .clock = 9000,
  2588. .hdisplay = 480,
  2589. .hsync_start = 480 + 2,
  2590. .hsync_end = 480 + 2 + 41,
  2591. .htotal = 480 + 2 + 41 + 2,
  2592. .vdisplay = 272,
  2593. .vsync_start = 272 + 2,
  2594. .vsync_end = 272 + 2 + 10,
  2595. .vtotal = 272 + 2 + 10 + 2,
  2596. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  2597. };
  2598. static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
  2599. .modes = &newhaven_nhd_43_480272ef_atxl_mode,
  2600. .num_modes = 1,
  2601. .bpc = 8,
  2602. .size = {
  2603. .width = 95,
  2604. .height = 54,
  2605. },
  2606. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  2607. .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
  2608. DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
  2609. .connector_type = DRM_MODE_CONNECTOR_DPI,
  2610. };
  2611. static const struct display_timing nlt_nl192108ac18_02d_timing = {
  2612. .pixelclock = { 130000000, 148350000, 163000000 },
  2613. .hactive = { 1920, 1920, 1920 },
  2614. .hfront_porch = { 80, 100, 100 },
  2615. .hback_porch = { 100, 120, 120 },
  2616. .hsync_len = { 50, 60, 60 },
  2617. .vactive = { 1080, 1080, 1080 },
  2618. .vfront_porch = { 12, 30, 30 },
  2619. .vback_porch = { 4, 10, 10 },
  2620. .vsync_len = { 4, 5, 5 },
  2621. };
  2622. static const struct panel_desc nlt_nl192108ac18_02d = {
  2623. .timings = &nlt_nl192108ac18_02d_timing,
  2624. .num_timings = 1,
  2625. .bpc = 8,
  2626. .size = {
  2627. .width = 344,
  2628. .height = 194,
  2629. },
  2630. .delay = {
  2631. .unprepare = 500,
  2632. },
  2633. .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
  2634. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  2635. };
  2636. static const struct drm_display_mode nvd_9128_mode = {
  2637. .clock = 29500,
  2638. .hdisplay = 800,
  2639. .hsync_start = 800 + 130,
  2640. .hsync_end = 800 + 130 + 98,
  2641. .htotal = 800 + 0 + 130 + 98,
  2642. .vdisplay = 480,
  2643. .vsync_start = 480 + 10,
  2644. .vsync_end = 480 + 10 + 50,
  2645. .vtotal = 480 + 0 + 10 + 50,
  2646. };
  2647. static const struct panel_desc nvd_9128 = {
  2648. .modes = &nvd_9128_mode,
  2649. .num_modes = 1,
  2650. .bpc = 8,
  2651. .size = {
  2652. .width = 156,
  2653. .height = 88,
  2654. },
  2655. .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
  2656. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  2657. };
  2658. static const struct display_timing okaya_rs800480t_7x0gp_timing = {
  2659. .pixelclock = { 30000000, 30000000, 40000000 },
  2660. .hactive = { 800, 800, 800 },
  2661. .hfront_porch = { 40, 40, 40 },
  2662. .hback_porch = { 40, 40, 40 },
  2663. .hsync_len = { 1, 48, 48 },
  2664. .vactive = { 480, 480, 480 },
  2665. .vfront_porch = { 13, 13, 13 },
  2666. .vback_porch = { 29, 29, 29 },
  2667. .vsync_len = { 3, 3, 3 },
  2668. .flags = DISPLAY_FLAGS_DE_HIGH,
  2669. };
  2670. static const struct panel_desc okaya_rs800480t_7x0gp = {
  2671. .timings = &okaya_rs800480t_7x0gp_timing,
  2672. .num_timings = 1,
  2673. .bpc = 6,
  2674. .size = {
  2675. .width = 154,
  2676. .height = 87,
  2677. },
  2678. .delay = {
  2679. .prepare = 41,
  2680. .enable = 50,
  2681. .unprepare = 41,
  2682. .disable = 50,
  2683. },
  2684. .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
  2685. };
  2686. static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
  2687. .clock = 9000,
  2688. .hdisplay = 480,
  2689. .hsync_start = 480 + 5,
  2690. .hsync_end = 480 + 5 + 30,
  2691. .htotal = 480 + 5 + 30 + 10,
  2692. .vdisplay = 272,
  2693. .vsync_start = 272 + 8,
  2694. .vsync_end = 272 + 8 + 5,
  2695. .vtotal = 272 + 8 + 5 + 3,
  2696. };
  2697. static const struct panel_desc olimex_lcd_olinuxino_43ts = {
  2698. .modes = &olimex_lcd_olinuxino_43ts_mode,
  2699. .num_modes = 1,
  2700. .size = {
  2701. .width = 95,
  2702. .height = 54,
  2703. },
  2704. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  2705. };
  2706. /*
  2707. * 800x480 CVT. The panel appears to be quite accepting, at least as far as
  2708. * pixel clocks, but this is the timing that was being used in the Adafruit
  2709. * installation instructions.
  2710. */
  2711. static const struct drm_display_mode ontat_yx700wv03_mode = {
  2712. .clock = 29500,
  2713. .hdisplay = 800,
  2714. .hsync_start = 824,
  2715. .hsync_end = 896,
  2716. .htotal = 992,
  2717. .vdisplay = 480,
  2718. .vsync_start = 483,
  2719. .vsync_end = 493,
  2720. .vtotal = 500,
  2721. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  2722. };
  2723. /*
  2724. * Specification at:
  2725. * https://www.adafruit.com/images/product-files/2406/c3163.pdf
  2726. */
  2727. static const struct panel_desc ontat_yx700wv03 = {
  2728. .modes = &ontat_yx700wv03_mode,
  2729. .num_modes = 1,
  2730. .bpc = 8,
  2731. .size = {
  2732. .width = 154,
  2733. .height = 83,
  2734. },
  2735. .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
  2736. };
  2737. static const struct drm_display_mode ortustech_com37h3m_mode = {
  2738. .clock = 22230,
  2739. .hdisplay = 480,
  2740. .hsync_start = 480 + 40,
  2741. .hsync_end = 480 + 40 + 10,
  2742. .htotal = 480 + 40 + 10 + 40,
  2743. .vdisplay = 640,
  2744. .vsync_start = 640 + 4,
  2745. .vsync_end = 640 + 4 + 2,
  2746. .vtotal = 640 + 4 + 2 + 4,
  2747. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  2748. };
  2749. static const struct panel_desc ortustech_com37h3m = {
  2750. .modes = &ortustech_com37h3m_mode,
  2751. .num_modes = 1,
  2752. .bpc = 8,
  2753. .size = {
  2754. .width = 56, /* 56.16mm */
  2755. .height = 75, /* 74.88mm */
  2756. },
  2757. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  2758. .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
  2759. DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
  2760. };
  2761. static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
  2762. .clock = 25000,
  2763. .hdisplay = 480,
  2764. .hsync_start = 480 + 10,
  2765. .hsync_end = 480 + 10 + 10,
  2766. .htotal = 480 + 10 + 10 + 15,
  2767. .vdisplay = 800,
  2768. .vsync_start = 800 + 3,
  2769. .vsync_end = 800 + 3 + 3,
  2770. .vtotal = 800 + 3 + 3 + 3,
  2771. };
  2772. static const struct panel_desc ortustech_com43h4m85ulc = {
  2773. .modes = &ortustech_com43h4m85ulc_mode,
  2774. .num_modes = 1,
  2775. .bpc = 6,
  2776. .size = {
  2777. .width = 56,
  2778. .height = 93,
  2779. },
  2780. .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
  2781. .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
  2782. .connector_type = DRM_MODE_CONNECTOR_DPI,
  2783. };
  2784. static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
  2785. .clock = 33000,
  2786. .hdisplay = 800,
  2787. .hsync_start = 800 + 210,
  2788. .hsync_end = 800 + 210 + 30,
  2789. .htotal = 800 + 210 + 30 + 16,
  2790. .vdisplay = 480,
  2791. .vsync_start = 480 + 22,
  2792. .vsync_end = 480 + 22 + 13,
  2793. .vtotal = 480 + 22 + 13 + 10,
  2794. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  2795. };
  2796. static const struct panel_desc osddisplays_osd070t1718_19ts = {
  2797. .modes = &osddisplays_osd070t1718_19ts_mode,
  2798. .num_modes = 1,
  2799. .bpc = 8,
  2800. .size = {
  2801. .width = 152,
  2802. .height = 91,
  2803. },
  2804. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  2805. .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
  2806. DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
  2807. .connector_type = DRM_MODE_CONNECTOR_DPI,
  2808. };
  2809. static const struct drm_display_mode pda_91_00156_a0_mode = {
  2810. .clock = 33300,
  2811. .hdisplay = 800,
  2812. .hsync_start = 800 + 1,
  2813. .hsync_end = 800 + 1 + 64,
  2814. .htotal = 800 + 1 + 64 + 64,
  2815. .vdisplay = 480,
  2816. .vsync_start = 480 + 1,
  2817. .vsync_end = 480 + 1 + 23,
  2818. .vtotal = 480 + 1 + 23 + 22,
  2819. };
  2820. static const struct panel_desc pda_91_00156_a0 = {
  2821. .modes = &pda_91_00156_a0_mode,
  2822. .num_modes = 1,
  2823. .size = {
  2824. .width = 152,
  2825. .height = 91,
  2826. },
  2827. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  2828. };
  2829. static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
  2830. .clock = 24750,
  2831. .hdisplay = 800,
  2832. .hsync_start = 800 + 54,
  2833. .hsync_end = 800 + 54 + 2,
  2834. .htotal = 800 + 54 + 2 + 44,
  2835. .vdisplay = 480,
  2836. .vsync_start = 480 + 49,
  2837. .vsync_end = 480 + 49 + 2,
  2838. .vtotal = 480 + 49 + 2 + 22,
  2839. };
  2840. static const struct panel_desc powertip_ph800480t013_idf02 = {
  2841. .modes = &powertip_ph800480t013_idf02_mode,
  2842. .num_modes = 1,
  2843. .size = {
  2844. .width = 152,
  2845. .height = 91,
  2846. },
  2847. .bus_flags = DRM_BUS_FLAG_DE_HIGH |
  2848. DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
  2849. DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
  2850. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  2851. .connector_type = DRM_MODE_CONNECTOR_DPI,
  2852. };
  2853. static const struct drm_display_mode qd43003c0_40_mode = {
  2854. .clock = 9000,
  2855. .hdisplay = 480,
  2856. .hsync_start = 480 + 8,
  2857. .hsync_end = 480 + 8 + 4,
  2858. .htotal = 480 + 8 + 4 + 39,
  2859. .vdisplay = 272,
  2860. .vsync_start = 272 + 4,
  2861. .vsync_end = 272 + 4 + 10,
  2862. .vtotal = 272 + 4 + 10 + 2,
  2863. };
  2864. static const struct panel_desc qd43003c0_40 = {
  2865. .modes = &qd43003c0_40_mode,
  2866. .num_modes = 1,
  2867. .bpc = 8,
  2868. .size = {
  2869. .width = 95,
  2870. .height = 53,
  2871. },
  2872. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  2873. };
  2874. static const struct display_timing rocktech_rk070er9427_timing = {
  2875. .pixelclock = { 26400000, 33300000, 46800000 },
  2876. .hactive = { 800, 800, 800 },
  2877. .hfront_porch = { 16, 210, 354 },
  2878. .hback_porch = { 46, 46, 46 },
  2879. .hsync_len = { 1, 1, 1 },
  2880. .vactive = { 480, 480, 480 },
  2881. .vfront_porch = { 7, 22, 147 },
  2882. .vback_porch = { 23, 23, 23 },
  2883. .vsync_len = { 1, 1, 1 },
  2884. .flags = DISPLAY_FLAGS_DE_HIGH,
  2885. };
  2886. static const struct panel_desc rocktech_rk070er9427 = {
  2887. .timings = &rocktech_rk070er9427_timing,
  2888. .num_timings = 1,
  2889. .bpc = 6,
  2890. .size = {
  2891. .width = 154,
  2892. .height = 86,
  2893. },
  2894. .delay = {
  2895. .prepare = 41,
  2896. .enable = 50,
  2897. .unprepare = 41,
  2898. .disable = 50,
  2899. },
  2900. .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
  2901. };
  2902. static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
  2903. .clock = 71100,
  2904. .hdisplay = 1280,
  2905. .hsync_start = 1280 + 48,
  2906. .hsync_end = 1280 + 48 + 32,
  2907. .htotal = 1280 + 48 + 32 + 80,
  2908. .vdisplay = 800,
  2909. .vsync_start = 800 + 2,
  2910. .vsync_end = 800 + 2 + 5,
  2911. .vtotal = 800 + 2 + 5 + 16,
  2912. };
  2913. static const struct panel_desc rocktech_rk101ii01d_ct = {
  2914. .modes = &rocktech_rk101ii01d_ct_mode,
  2915. .num_modes = 1,
  2916. .size = {
  2917. .width = 217,
  2918. .height = 136,
  2919. },
  2920. .delay = {
  2921. .prepare = 50,
  2922. .disable = 50,
  2923. },
  2924. .bus_flags = DRM_BUS_FLAG_DE_HIGH,
  2925. .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
  2926. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  2927. };
  2928. static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
  2929. .clock = 271560,
  2930. .hdisplay = 2560,
  2931. .hsync_start = 2560 + 48,
  2932. .hsync_end = 2560 + 48 + 32,
  2933. .htotal = 2560 + 48 + 32 + 80,
  2934. .vdisplay = 1600,
  2935. .vsync_start = 1600 + 2,
  2936. .vsync_end = 1600 + 2 + 5,
  2937. .vtotal = 1600 + 2 + 5 + 57,
  2938. };
  2939. static const struct panel_desc samsung_lsn122dl01_c01 = {
  2940. .modes = &samsung_lsn122dl01_c01_mode,
  2941. .num_modes = 1,
  2942. .size = {
  2943. .width = 263,
  2944. .height = 164,
  2945. },
  2946. };
  2947. static const struct drm_display_mode samsung_ltn101nt05_mode = {
  2948. .clock = 54030,
  2949. .hdisplay = 1024,
  2950. .hsync_start = 1024 + 24,
  2951. .hsync_end = 1024 + 24 + 136,
  2952. .htotal = 1024 + 24 + 136 + 160,
  2953. .vdisplay = 600,
  2954. .vsync_start = 600 + 3,
  2955. .vsync_end = 600 + 3 + 6,
  2956. .vtotal = 600 + 3 + 6 + 61,
  2957. };
  2958. static const struct panel_desc samsung_ltn101nt05 = {
  2959. .modes = &samsung_ltn101nt05_mode,
  2960. .num_modes = 1,
  2961. .bpc = 6,
  2962. .size = {
  2963. .width = 223,
  2964. .height = 125,
  2965. },
  2966. .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
  2967. .bus_flags = DRM_BUS_FLAG_DE_HIGH,
  2968. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  2969. };
  2970. static const struct drm_display_mode samsung_ltn140at29_301_mode = {
  2971. .clock = 76300,
  2972. .hdisplay = 1366,
  2973. .hsync_start = 1366 + 64,
  2974. .hsync_end = 1366 + 64 + 48,
  2975. .htotal = 1366 + 64 + 48 + 128,
  2976. .vdisplay = 768,
  2977. .vsync_start = 768 + 2,
  2978. .vsync_end = 768 + 2 + 5,
  2979. .vtotal = 768 + 2 + 5 + 17,
  2980. };
  2981. static const struct panel_desc samsung_ltn140at29_301 = {
  2982. .modes = &samsung_ltn140at29_301_mode,
  2983. .num_modes = 1,
  2984. .bpc = 6,
  2985. .size = {
  2986. .width = 320,
  2987. .height = 187,
  2988. },
  2989. };
  2990. static const struct display_timing satoz_sat050at40h12r2_timing = {
  2991. .pixelclock = {33300000, 33300000, 50000000},
  2992. .hactive = {800, 800, 800},
  2993. .hfront_porch = {16, 210, 354},
  2994. .hback_porch = {46, 46, 46},
  2995. .hsync_len = {1, 1, 40},
  2996. .vactive = {480, 480, 480},
  2997. .vfront_porch = {7, 22, 147},
  2998. .vback_porch = {23, 23, 23},
  2999. .vsync_len = {1, 1, 20},
  3000. };
  3001. static const struct panel_desc satoz_sat050at40h12r2 = {
  3002. .timings = &satoz_sat050at40h12r2_timing,
  3003. .num_timings = 1,
  3004. .bpc = 8,
  3005. .size = {
  3006. .width = 108,
  3007. .height = 65,
  3008. },
  3009. .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
  3010. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  3011. };
  3012. static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
  3013. .clock = 168480,
  3014. .hdisplay = 1920,
  3015. .hsync_start = 1920 + 48,
  3016. .hsync_end = 1920 + 48 + 32,
  3017. .htotal = 1920 + 48 + 32 + 80,
  3018. .vdisplay = 1280,
  3019. .vsync_start = 1280 + 3,
  3020. .vsync_end = 1280 + 3 + 10,
  3021. .vtotal = 1280 + 3 + 10 + 57,
  3022. .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
  3023. };
  3024. static const struct panel_desc sharp_ld_d5116z01b = {
  3025. .modes = &sharp_ld_d5116z01b_mode,
  3026. .num_modes = 1,
  3027. .bpc = 8,
  3028. .size = {
  3029. .width = 260,
  3030. .height = 120,
  3031. },
  3032. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  3033. .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
  3034. };
  3035. static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
  3036. .clock = 33260,
  3037. .hdisplay = 800,
  3038. .hsync_start = 800 + 64,
  3039. .hsync_end = 800 + 64 + 128,
  3040. .htotal = 800 + 64 + 128 + 64,
  3041. .vdisplay = 480,
  3042. .vsync_start = 480 + 8,
  3043. .vsync_end = 480 + 8 + 2,
  3044. .vtotal = 480 + 8 + 2 + 35,
  3045. .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
  3046. };
  3047. static const struct panel_desc sharp_lq070y3dg3b = {
  3048. .modes = &sharp_lq070y3dg3b_mode,
  3049. .num_modes = 1,
  3050. .bpc = 8,
  3051. .size = {
  3052. .width = 152, /* 152.4mm */
  3053. .height = 91, /* 91.4mm */
  3054. },
  3055. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  3056. .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
  3057. DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
  3058. };
  3059. static const struct drm_display_mode sharp_lq035q7db03_mode = {
  3060. .clock = 5500,
  3061. .hdisplay = 240,
  3062. .hsync_start = 240 + 16,
  3063. .hsync_end = 240 + 16 + 7,
  3064. .htotal = 240 + 16 + 7 + 5,
  3065. .vdisplay = 320,
  3066. .vsync_start = 320 + 9,
  3067. .vsync_end = 320 + 9 + 1,
  3068. .vtotal = 320 + 9 + 1 + 7,
  3069. };
  3070. static const struct panel_desc sharp_lq035q7db03 = {
  3071. .modes = &sharp_lq035q7db03_mode,
  3072. .num_modes = 1,
  3073. .bpc = 6,
  3074. .size = {
  3075. .width = 54,
  3076. .height = 72,
  3077. },
  3078. .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
  3079. };
  3080. static const struct display_timing sharp_lq101k1ly04_timing = {
  3081. .pixelclock = { 60000000, 65000000, 80000000 },
  3082. .hactive = { 1280, 1280, 1280 },
  3083. .hfront_porch = { 20, 20, 20 },
  3084. .hback_porch = { 20, 20, 20 },
  3085. .hsync_len = { 10, 10, 10 },
  3086. .vactive = { 800, 800, 800 },
  3087. .vfront_porch = { 4, 4, 4 },
  3088. .vback_porch = { 4, 4, 4 },
  3089. .vsync_len = { 4, 4, 4 },
  3090. .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
  3091. };
  3092. static const struct panel_desc sharp_lq101k1ly04 = {
  3093. .timings = &sharp_lq101k1ly04_timing,
  3094. .num_timings = 1,
  3095. .bpc = 8,
  3096. .size = {
  3097. .width = 217,
  3098. .height = 136,
  3099. },
  3100. .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
  3101. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  3102. };
  3103. static const struct display_timing sharp_lq123p1jx31_timing = {
  3104. .pixelclock = { 252750000, 252750000, 266604720 },
  3105. .hactive = { 2400, 2400, 2400 },
  3106. .hfront_porch = { 48, 48, 48 },
  3107. .hback_porch = { 80, 80, 84 },
  3108. .hsync_len = { 32, 32, 32 },
  3109. .vactive = { 1600, 1600, 1600 },
  3110. .vfront_porch = { 3, 3, 3 },
  3111. .vback_porch = { 33, 33, 120 },
  3112. .vsync_len = { 10, 10, 10 },
  3113. .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
  3114. };
  3115. static const struct panel_desc sharp_lq123p1jx31 = {
  3116. .timings = &sharp_lq123p1jx31_timing,
  3117. .num_timings = 1,
  3118. .bpc = 8,
  3119. .size = {
  3120. .width = 259,
  3121. .height = 173,
  3122. },
  3123. .delay = {
  3124. .prepare = 110,
  3125. .enable = 50,
  3126. .unprepare = 550,
  3127. },
  3128. };
  3129. static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
  3130. { /* 50 Hz */
  3131. .clock = 3000,
  3132. .hdisplay = 240,
  3133. .hsync_start = 240 + 58,
  3134. .hsync_end = 240 + 58 + 1,
  3135. .htotal = 240 + 58 + 1 + 1,
  3136. .vdisplay = 160,
  3137. .vsync_start = 160 + 24,
  3138. .vsync_end = 160 + 24 + 10,
  3139. .vtotal = 160 + 24 + 10 + 6,
  3140. .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
  3141. },
  3142. { /* 60 Hz */
  3143. .clock = 3000,
  3144. .hdisplay = 240,
  3145. .hsync_start = 240 + 8,
  3146. .hsync_end = 240 + 8 + 1,
  3147. .htotal = 240 + 8 + 1 + 1,
  3148. .vdisplay = 160,
  3149. .vsync_start = 160 + 24,
  3150. .vsync_end = 160 + 24 + 10,
  3151. .vtotal = 160 + 24 + 10 + 6,
  3152. .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
  3153. },
  3154. };
  3155. static const struct panel_desc sharp_ls020b1dd01d = {
  3156. .modes = sharp_ls020b1dd01d_modes,
  3157. .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
  3158. .bpc = 6,
  3159. .size = {
  3160. .width = 42,
  3161. .height = 28,
  3162. },
  3163. .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
  3164. .bus_flags = DRM_BUS_FLAG_DE_HIGH
  3165. | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
  3166. | DRM_BUS_FLAG_SHARP_SIGNALS,
  3167. };
  3168. static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
  3169. .clock = 33300,
  3170. .hdisplay = 800,
  3171. .hsync_start = 800 + 1,
  3172. .hsync_end = 800 + 1 + 64,
  3173. .htotal = 800 + 1 + 64 + 64,
  3174. .vdisplay = 480,
  3175. .vsync_start = 480 + 1,
  3176. .vsync_end = 480 + 1 + 23,
  3177. .vtotal = 480 + 1 + 23 + 22,
  3178. };
  3179. static const struct panel_desc shelly_sca07010_bfn_lnn = {
  3180. .modes = &shelly_sca07010_bfn_lnn_mode,
  3181. .num_modes = 1,
  3182. .size = {
  3183. .width = 152,
  3184. .height = 91,
  3185. },
  3186. .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
  3187. };
  3188. static const struct drm_display_mode starry_kr070pe2t_mode = {
  3189. .clock = 33000,
  3190. .hdisplay = 800,
  3191. .hsync_start = 800 + 209,
  3192. .hsync_end = 800 + 209 + 1,
  3193. .htotal = 800 + 209 + 1 + 45,
  3194. .vdisplay = 480,
  3195. .vsync_start = 480 + 22,
  3196. .vsync_end = 480 + 22 + 1,
  3197. .vtotal = 480 + 22 + 1 + 22,
  3198. };
  3199. static const struct panel_desc starry_kr070pe2t = {
  3200. .modes = &starry_kr070pe2t_mode,
  3201. .num_modes = 1,
  3202. .bpc = 8,
  3203. .size = {
  3204. .width = 152,
  3205. .height = 86,
  3206. },
  3207. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  3208. .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
  3209. .connector_type = DRM_MODE_CONNECTOR_DPI,
  3210. };
  3211. static const struct drm_display_mode starry_kr122ea0sra_mode = {
  3212. .clock = 147000,
  3213. .hdisplay = 1920,
  3214. .hsync_start = 1920 + 16,
  3215. .hsync_end = 1920 + 16 + 16,
  3216. .htotal = 1920 + 16 + 16 + 32,
  3217. .vdisplay = 1200,
  3218. .vsync_start = 1200 + 15,
  3219. .vsync_end = 1200 + 15 + 2,
  3220. .vtotal = 1200 + 15 + 2 + 18,
  3221. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  3222. };
  3223. static const struct panel_desc starry_kr122ea0sra = {
  3224. .modes = &starry_kr122ea0sra_mode,
  3225. .num_modes = 1,
  3226. .size = {
  3227. .width = 263,
  3228. .height = 164,
  3229. },
  3230. .delay = {
  3231. .prepare = 10 + 200,
  3232. .enable = 50,
  3233. .unprepare = 10 + 500,
  3234. },
  3235. };
  3236. static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
  3237. .clock = 30000,
  3238. .hdisplay = 800,
  3239. .hsync_start = 800 + 39,
  3240. .hsync_end = 800 + 39 + 47,
  3241. .htotal = 800 + 39 + 47 + 39,
  3242. .vdisplay = 480,
  3243. .vsync_start = 480 + 13,
  3244. .vsync_end = 480 + 13 + 2,
  3245. .vtotal = 480 + 13 + 2 + 29,
  3246. };
  3247. static const struct panel_desc tfc_s9700rtwv43tr_01b = {
  3248. .modes = &tfc_s9700rtwv43tr_01b_mode,
  3249. .num_modes = 1,
  3250. .bpc = 8,
  3251. .size = {
  3252. .width = 155,
  3253. .height = 90,
  3254. },
  3255. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  3256. .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
  3257. };
  3258. static const struct display_timing tianma_tm070jdhg30_timing = {
  3259. .pixelclock = { 62600000, 68200000, 78100000 },
  3260. .hactive = { 1280, 1280, 1280 },
  3261. .hfront_porch = { 15, 64, 159 },
  3262. .hback_porch = { 5, 5, 5 },
  3263. .hsync_len = { 1, 1, 256 },
  3264. .vactive = { 800, 800, 800 },
  3265. .vfront_porch = { 3, 40, 99 },
  3266. .vback_porch = { 2, 2, 2 },
  3267. .vsync_len = { 1, 1, 128 },
  3268. .flags = DISPLAY_FLAGS_DE_HIGH,
  3269. };
  3270. static const struct panel_desc tianma_tm070jdhg30 = {
  3271. .timings = &tianma_tm070jdhg30_timing,
  3272. .num_timings = 1,
  3273. .bpc = 8,
  3274. .size = {
  3275. .width = 151,
  3276. .height = 95,
  3277. },
  3278. .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
  3279. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  3280. };
  3281. static const struct panel_desc tianma_tm070jvhg33 = {
  3282. .timings = &tianma_tm070jdhg30_timing,
  3283. .num_timings = 1,
  3284. .bpc = 8,
  3285. .size = {
  3286. .width = 150,
  3287. .height = 94,
  3288. },
  3289. .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
  3290. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  3291. };
  3292. static const struct display_timing tianma_tm070rvhg71_timing = {
  3293. .pixelclock = { 27700000, 29200000, 39600000 },
  3294. .hactive = { 800, 800, 800 },
  3295. .hfront_porch = { 12, 40, 212 },
  3296. .hback_porch = { 88, 88, 88 },
  3297. .hsync_len = { 1, 1, 40 },
  3298. .vactive = { 480, 480, 480 },
  3299. .vfront_porch = { 1, 13, 88 },
  3300. .vback_porch = { 32, 32, 32 },
  3301. .vsync_len = { 1, 1, 3 },
  3302. .flags = DISPLAY_FLAGS_DE_HIGH,
  3303. };
  3304. static const struct panel_desc tianma_tm070rvhg71 = {
  3305. .timings = &tianma_tm070rvhg71_timing,
  3306. .num_timings = 1,
  3307. .bpc = 8,
  3308. .size = {
  3309. .width = 154,
  3310. .height = 86,
  3311. },
  3312. .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
  3313. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  3314. };
  3315. static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
  3316. {
  3317. .clock = 10000,
  3318. .hdisplay = 320,
  3319. .hsync_start = 320 + 50,
  3320. .hsync_end = 320 + 50 + 6,
  3321. .htotal = 320 + 50 + 6 + 38,
  3322. .vdisplay = 240,
  3323. .vsync_start = 240 + 3,
  3324. .vsync_end = 240 + 3 + 1,
  3325. .vtotal = 240 + 3 + 1 + 17,
  3326. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  3327. },
  3328. };
  3329. static const struct panel_desc ti_nspire_cx_lcd_panel = {
  3330. .modes = ti_nspire_cx_lcd_mode,
  3331. .num_modes = 1,
  3332. .bpc = 8,
  3333. .size = {
  3334. .width = 65,
  3335. .height = 49,
  3336. },
  3337. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  3338. .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
  3339. };
  3340. static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
  3341. {
  3342. .clock = 10000,
  3343. .hdisplay = 320,
  3344. .hsync_start = 320 + 6,
  3345. .hsync_end = 320 + 6 + 6,
  3346. .htotal = 320 + 6 + 6 + 6,
  3347. .vdisplay = 240,
  3348. .vsync_start = 240 + 0,
  3349. .vsync_end = 240 + 0 + 1,
  3350. .vtotal = 240 + 0 + 1 + 0,
  3351. .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
  3352. },
  3353. };
  3354. static const struct panel_desc ti_nspire_classic_lcd_panel = {
  3355. .modes = ti_nspire_classic_lcd_mode,
  3356. .num_modes = 1,
  3357. /* The grayscale panel has 8 bit for the color .. Y (black) */
  3358. .bpc = 8,
  3359. .size = {
  3360. .width = 71,
  3361. .height = 53,
  3362. },
  3363. /* This is the grayscale bus format */
  3364. .bus_format = MEDIA_BUS_FMT_Y8_1X8,
  3365. .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
  3366. };
  3367. static const struct drm_display_mode toshiba_lt089ac29000_mode = {
  3368. .clock = 79500,
  3369. .hdisplay = 1280,
  3370. .hsync_start = 1280 + 192,
  3371. .hsync_end = 1280 + 192 + 128,
  3372. .htotal = 1280 + 192 + 128 + 64,
  3373. .vdisplay = 768,
  3374. .vsync_start = 768 + 20,
  3375. .vsync_end = 768 + 20 + 7,
  3376. .vtotal = 768 + 20 + 7 + 3,
  3377. };
  3378. static const struct panel_desc toshiba_lt089ac29000 = {
  3379. .modes = &toshiba_lt089ac29000_mode,
  3380. .num_modes = 1,
  3381. .size = {
  3382. .width = 194,
  3383. .height = 116,
  3384. },
  3385. .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
  3386. .bus_flags = DRM_BUS_FLAG_DE_HIGH,
  3387. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  3388. };
  3389. static const struct drm_display_mode tpk_f07a_0102_mode = {
  3390. .clock = 33260,
  3391. .hdisplay = 800,
  3392. .hsync_start = 800 + 40,
  3393. .hsync_end = 800 + 40 + 128,
  3394. .htotal = 800 + 40 + 128 + 88,
  3395. .vdisplay = 480,
  3396. .vsync_start = 480 + 10,
  3397. .vsync_end = 480 + 10 + 2,
  3398. .vtotal = 480 + 10 + 2 + 33,
  3399. };
  3400. static const struct panel_desc tpk_f07a_0102 = {
  3401. .modes = &tpk_f07a_0102_mode,
  3402. .num_modes = 1,
  3403. .size = {
  3404. .width = 152,
  3405. .height = 91,
  3406. },
  3407. .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
  3408. };
  3409. static const struct drm_display_mode tpk_f10a_0102_mode = {
  3410. .clock = 45000,
  3411. .hdisplay = 1024,
  3412. .hsync_start = 1024 + 176,
  3413. .hsync_end = 1024 + 176 + 5,
  3414. .htotal = 1024 + 176 + 5 + 88,
  3415. .vdisplay = 600,
  3416. .vsync_start = 600 + 20,
  3417. .vsync_end = 600 + 20 + 5,
  3418. .vtotal = 600 + 20 + 5 + 25,
  3419. };
  3420. static const struct panel_desc tpk_f10a_0102 = {
  3421. .modes = &tpk_f10a_0102_mode,
  3422. .num_modes = 1,
  3423. .size = {
  3424. .width = 223,
  3425. .height = 125,
  3426. },
  3427. };
  3428. static const struct display_timing urt_umsh_8596md_timing = {
  3429. .pixelclock = { 33260000, 33260000, 33260000 },
  3430. .hactive = { 800, 800, 800 },
  3431. .hfront_porch = { 41, 41, 41 },
  3432. .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
  3433. .hsync_len = { 71, 128, 128 },
  3434. .vactive = { 480, 480, 480 },
  3435. .vfront_porch = { 10, 10, 10 },
  3436. .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
  3437. .vsync_len = { 2, 2, 2 },
  3438. .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
  3439. DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
  3440. };
  3441. static const struct panel_desc urt_umsh_8596md_lvds = {
  3442. .timings = &urt_umsh_8596md_timing,
  3443. .num_timings = 1,
  3444. .bpc = 6,
  3445. .size = {
  3446. .width = 152,
  3447. .height = 91,
  3448. },
  3449. .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
  3450. .connector_type = DRM_MODE_CONNECTOR_LVDS,
  3451. };
  3452. static const struct panel_desc urt_umsh_8596md_parallel = {
  3453. .timings = &urt_umsh_8596md_timing,
  3454. .num_timings = 1,
  3455. .bpc = 6,
  3456. .size = {
  3457. .width = 152,
  3458. .height = 91,
  3459. },
  3460. .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
  3461. };
  3462. static const struct drm_display_mode vl050_8048nt_c01_mode = {
  3463. .clock = 33333,
  3464. .hdisplay = 800,
  3465. .hsync_start = 800 + 210,
  3466. .hsync_end = 800 + 210 + 20,
  3467. .htotal = 800 + 210 + 20 + 46,
  3468. .vdisplay = 480,
  3469. .vsync_start = 480 + 22,
  3470. .vsync_end = 480 + 22 + 10,
  3471. .vtotal = 480 + 22 + 10 + 23,
  3472. .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
  3473. };
  3474. static const struct panel_desc vl050_8048nt_c01 = {
  3475. .modes = &vl050_8048nt_c01_mode,
  3476. .num_modes = 1,
  3477. .bpc = 8,
  3478. .size = {
  3479. .width = 120,
  3480. .height = 76,
  3481. },
  3482. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  3483. .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
  3484. };
  3485. static const struct drm_display_mode winstar_wf35ltiacd_mode = {
  3486. .clock = 6410,
  3487. .hdisplay = 320,
  3488. .hsync_start = 320 + 20,
  3489. .hsync_end = 320 + 20 + 30,
  3490. .htotal = 320 + 20 + 30 + 38,
  3491. .vdisplay = 240,
  3492. .vsync_start = 240 + 4,
  3493. .vsync_end = 240 + 4 + 3,
  3494. .vtotal = 240 + 4 + 3 + 15,
  3495. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  3496. };
  3497. static const struct panel_desc winstar_wf35ltiacd = {
  3498. .modes = &winstar_wf35ltiacd_mode,
  3499. .num_modes = 1,
  3500. .bpc = 8,
  3501. .size = {
  3502. .width = 70,
  3503. .height = 53,
  3504. },
  3505. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  3506. };
  3507. static const struct drm_display_mode arm_rtsm_mode[] = {
  3508. {
  3509. .clock = 65000,
  3510. .hdisplay = 1024,
  3511. .hsync_start = 1024 + 24,
  3512. .hsync_end = 1024 + 24 + 136,
  3513. .htotal = 1024 + 24 + 136 + 160,
  3514. .vdisplay = 768,
  3515. .vsync_start = 768 + 3,
  3516. .vsync_end = 768 + 3 + 6,
  3517. .vtotal = 768 + 3 + 6 + 29,
  3518. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  3519. },
  3520. };
  3521. static const struct panel_desc arm_rtsm = {
  3522. .modes = arm_rtsm_mode,
  3523. .num_modes = 1,
  3524. .bpc = 8,
  3525. .size = {
  3526. .width = 400,
  3527. .height = 300,
  3528. },
  3529. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  3530. };
  3531. static const struct drm_display_mode light_dummy_panel_modes[] = {
  3532. {
  3533. .clock = 594000,
  3534. .hdisplay = 3840,
  3535. .hsync_start = 3840 + 176,
  3536. .hsync_end = 3840 + 176 + 88,
  3537. .htotal = 3840 + 176 + 88 + 296,
  3538. .vdisplay = 2160,
  3539. .vsync_start = 2160 + 8,
  3540. .vsync_end = 2160 + 8 + 10,
  3541. .vtotal = 2160 + 8 + 10 + 72,
  3542. .type = DRM_MODE_TYPE_PREFERRED,
  3543. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  3544. }, {
  3545. .clock = 297000,
  3546. .hdisplay = 3840,
  3547. .hsync_start = 3840 + 176,
  3548. .hsync_end = 3840 + 176 + 88,
  3549. .htotal = 3840 + 176 + 88 + 296,
  3550. .vdisplay = 2160,
  3551. .vsync_start = 2160 + 8,
  3552. .vsync_end = 2160 + 8 + 10,
  3553. .vtotal = 2160 + 8 + 10 + 72,
  3554. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  3555. }, {
  3556. .clock = 148500,
  3557. .hdisplay = 1920,
  3558. .hsync_start = 1920 + 88,
  3559. .hsync_end = 1920 + 88 + 44,
  3560. .htotal = 1920 + 88 + 44 + 148,
  3561. .vdisplay = 1080,
  3562. .vsync_start = 1080 + 4,
  3563. .vsync_end = 1080 + 4 + 5,
  3564. .vtotal = 1080 + 4 + 5 + 36,
  3565. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  3566. }, {
  3567. .clock = 74250,
  3568. .hdisplay = 1920,
  3569. .hsync_start = 1920 + 88,
  3570. .hsync_end = 1920 + 88 + 44,
  3571. .htotal = 1920 + 88 + 44 + 148,
  3572. .vdisplay = 1080,
  3573. .vsync_start = 1080 + 4,
  3574. .vsync_end = 1080 + 4 + 5,
  3575. .vtotal = 1080 + 4 + 5 + 36,
  3576. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  3577. }, {
  3578. .clock = 74250,
  3579. .hdisplay = 1280,
  3580. .hsync_start = 1280 + 110,
  3581. .hsync_end = 1280 + 110 + 40,
  3582. .htotal = 1280 + 110 + 40 + 220,
  3583. .vdisplay = 720,
  3584. .vsync_start = 720 + 5,
  3585. .vsync_end = 720 + 5 + 5,
  3586. .vtotal = 720 + 5 + 5 + 20,
  3587. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  3588. }, {
  3589. .clock = 74250,
  3590. .hdisplay = 1280,
  3591. .hsync_start = 1280 + 1760,
  3592. .hsync_end = 1280 + 1760 + 40,
  3593. .htotal = 1280 + 1760 + 40 + 220,
  3594. .vdisplay = 720,
  3595. .vsync_start = 720 + 5,
  3596. .vsync_end = 720 + 5 + 5,
  3597. .vtotal = 720 + 5 + 5 + 20,
  3598. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  3599. }, {
  3600. .clock = 27000,
  3601. .hdisplay = 720,
  3602. .hsync_start = 720 + 16,
  3603. .hsync_end = 720 + 16 + 62,
  3604. .htotal = 720 + 16 + 62 + 60,
  3605. .vdisplay = 480,
  3606. .vsync_start = 480 + 9,
  3607. .vsync_end = 480 + 9 + 6,
  3608. .vtotal = 480 + 9 + 6 + 30,
  3609. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  3610. }, {
  3611. .clock = 25200,
  3612. .hdisplay = 640,
  3613. .hsync_start = 640 + 16,
  3614. .hsync_end = 640 + 16 + 96,
  3615. .htotal = 640 + 16 + 96 + 48,
  3616. .vdisplay = 480,
  3617. .vsync_start = 480 + 10,
  3618. .vsync_end = 480 + 10 + 2,
  3619. .vtotal = 480 + 10 + 2 + 33,
  3620. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  3621. },
  3622. };
  3623. static const struct panel_desc light_dummy_panel = {
  3624. .modes = light_dummy_panel_modes,
  3625. .num_modes = ARRAY_SIZE(light_dummy_panel_modes),
  3626. .bpc = 8,
  3627. .size = {
  3628. .width = 950,
  3629. .height = 540,
  3630. },
  3631. .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
  3632. };
  3633. static const struct of_device_id platform_of_match[] = {
  3634. {
  3635. .compatible = "ampire,am-1280800n3tzqw-t00h",
  3636. .data = &ampire_am_1280800n3tzqw_t00h,
  3637. }, {
  3638. .compatible = "ampire,am-480272h3tmqw-t01h",
  3639. .data = &ampire_am_480272h3tmqw_t01h,
  3640. }, {
  3641. .compatible = "ampire,am800480r3tmqwa1h",
  3642. .data = &ampire_am800480r3tmqwa1h,
  3643. }, {
  3644. .compatible = "arm,rtsm-display",
  3645. .data = &arm_rtsm,
  3646. }, {
  3647. .compatible = "armadeus,st0700-adapt",
  3648. .data = &armadeus_st0700_adapt,
  3649. }, {
  3650. .compatible = "auo,b101aw03",
  3651. .data = &auo_b101aw03,
  3652. }, {
  3653. .compatible = "auo,b101ean01",
  3654. .data = &auo_b101ean01,
  3655. }, {
  3656. .compatible = "auo,b101xtn01",
  3657. .data = &auo_b101xtn01,
  3658. }, {
  3659. .compatible = "auo,b116xa01",
  3660. .data = &auo_b116xak01,
  3661. }, {
  3662. .compatible = "auo,b116xw03",
  3663. .data = &auo_b116xw03,
  3664. }, {
  3665. .compatible = "auo,b133htn01",
  3666. .data = &auo_b133htn01,
  3667. }, {
  3668. .compatible = "auo,b133xtn01",
  3669. .data = &auo_b133xtn01,
  3670. }, {
  3671. .compatible = "auo,g070vvn01",
  3672. .data = &auo_g070vvn01,
  3673. }, {
  3674. .compatible = "auo,g101evn010",
  3675. .data = &auo_g101evn010,
  3676. }, {
  3677. .compatible = "auo,g104sn02",
  3678. .data = &auo_g104sn02,
  3679. }, {
  3680. .compatible = "auo,g121ean01",
  3681. .data = &auo_g121ean01,
  3682. }, {
  3683. .compatible = "auo,g133han01",
  3684. .data = &auo_g133han01,
  3685. }, {
  3686. .compatible = "auo,g156xtn01",
  3687. .data = &auo_g156xtn01,
  3688. }, {
  3689. .compatible = "auo,g185han01",
  3690. .data = &auo_g185han01,
  3691. }, {
  3692. .compatible = "auo,g190ean01",
  3693. .data = &auo_g190ean01,
  3694. }, {
  3695. .compatible = "auo,p320hvn03",
  3696. .data = &auo_p320hvn03,
  3697. }, {
  3698. .compatible = "auo,t215hvn01",
  3699. .data = &auo_t215hvn01,
  3700. }, {
  3701. .compatible = "avic,tm070ddh03",
  3702. .data = &avic_tm070ddh03,
  3703. }, {
  3704. .compatible = "bananapi,s070wv20-ct16",
  3705. .data = &bananapi_s070wv20_ct16,
  3706. }, {
  3707. .compatible = "boe,hv070wsa-100",
  3708. .data = &boe_hv070wsa
  3709. }, {
  3710. .compatible = "boe,nv101wxmn51",
  3711. .data = &boe_nv101wxmn51,
  3712. }, {
  3713. .compatible = "boe,nv133fhm-n61",
  3714. .data = &boe_nv133fhm_n61,
  3715. }, {
  3716. .compatible = "boe,nv133fhm-n62",
  3717. .data = &boe_nv133fhm_n61,
  3718. }, {
  3719. .compatible = "boe,nv140fhmn49",
  3720. .data = &boe_nv140fhmn49,
  3721. }, {
  3722. .compatible = "cdtech,s043wq26h-ct7",
  3723. .data = &cdtech_s043wq26h_ct7,
  3724. }, {
  3725. .compatible = "cdtech,s070pws19hp-fc21",
  3726. .data = &cdtech_s070pws19hp_fc21,
  3727. }, {
  3728. .compatible = "cdtech,s070swv29hg-dc44",
  3729. .data = &cdtech_s070swv29hg_dc44,
  3730. }, {
  3731. .compatible = "cdtech,s070wv95-ct16",
  3732. .data = &cdtech_s070wv95_ct16,
  3733. }, {
  3734. .compatible = "chefree,ch101olhlwh-002",
  3735. .data = &chefree_ch101olhlwh_002,
  3736. }, {
  3737. .compatible = "chunghwa,claa070wp03xg",
  3738. .data = &chunghwa_claa070wp03xg,
  3739. }, {
  3740. .compatible = "chunghwa,claa101wa01a",
  3741. .data = &chunghwa_claa101wa01a
  3742. }, {
  3743. .compatible = "chunghwa,claa101wb01",
  3744. .data = &chunghwa_claa101wb01
  3745. }, {
  3746. .compatible = "dataimage,scf0700c48ggu18",
  3747. .data = &dataimage_scf0700c48ggu18,
  3748. }, {
  3749. .compatible = "dlc,dlc0700yzg-1",
  3750. .data = &dlc_dlc0700yzg_1,
  3751. }, {
  3752. .compatible = "dlc,dlc1010gig",
  3753. .data = &dlc_dlc1010gig,
  3754. }, {
  3755. .compatible = "edt,et035012dm6",
  3756. .data = &edt_et035012dm6,
  3757. }, {
  3758. .compatible = "edt,etm043080dh6gp",
  3759. .data = &edt_etm043080dh6gp,
  3760. }, {
  3761. .compatible = "edt,etm0430g0dh6",
  3762. .data = &edt_etm0430g0dh6,
  3763. }, {
  3764. .compatible = "edt,et057090dhu",
  3765. .data = &edt_et057090dhu,
  3766. }, {
  3767. .compatible = "edt,et070080dh6",
  3768. .data = &edt_etm0700g0dh6,
  3769. }, {
  3770. .compatible = "edt,etm0700g0dh6",
  3771. .data = &edt_etm0700g0dh6,
  3772. }, {
  3773. .compatible = "edt,etm0700g0bdh6",
  3774. .data = &edt_etm0700g0bdh6,
  3775. }, {
  3776. .compatible = "edt,etm0700g0edh6",
  3777. .data = &edt_etm0700g0bdh6,
  3778. }, {
  3779. .compatible = "evervision,vgg804821",
  3780. .data = &evervision_vgg804821,
  3781. }, {
  3782. .compatible = "foxlink,fl500wvr00-a0t",
  3783. .data = &foxlink_fl500wvr00_a0t,
  3784. }, {
  3785. .compatible = "frida,frd350h54004",
  3786. .data = &frida_frd350h54004,
  3787. }, {
  3788. .compatible = "friendlyarm,hd702e",
  3789. .data = &friendlyarm_hd702e,
  3790. }, {
  3791. .compatible = "giantplus,gpg482739qs5",
  3792. .data = &giantplus_gpg482739qs5
  3793. }, {
  3794. .compatible = "giantplus,gpm940b0",
  3795. .data = &giantplus_gpm940b0,
  3796. }, {
  3797. .compatible = "hannstar,hsd070pww1",
  3798. .data = &hannstar_hsd070pww1,
  3799. }, {
  3800. .compatible = "hannstar,hsd100pxn1",
  3801. .data = &hannstar_hsd100pxn1,
  3802. }, {
  3803. .compatible = "hit,tx23d38vm0caa",
  3804. .data = &hitachi_tx23d38vm0caa
  3805. }, {
  3806. .compatible = "innolux,at043tn24",
  3807. .data = &innolux_at043tn24,
  3808. }, {
  3809. .compatible = "innolux,at070tn92",
  3810. .data = &innolux_at070tn92,
  3811. }, {
  3812. .compatible = "innolux,g070y2-l01",
  3813. .data = &innolux_g070y2_l01,
  3814. }, {
  3815. .compatible = "innolux,g101ice-l01",
  3816. .data = &innolux_g101ice_l01
  3817. }, {
  3818. .compatible = "innolux,g121i1-l01",
  3819. .data = &innolux_g121i1_l01
  3820. }, {
  3821. .compatible = "innolux,g121x1-l03",
  3822. .data = &innolux_g121x1_l03,
  3823. }, {
  3824. .compatible = "innolux,n116bge",
  3825. .data = &innolux_n116bge,
  3826. }, {
  3827. .compatible = "innolux,n156bge-l21",
  3828. .data = &innolux_n156bge_l21,
  3829. }, {
  3830. .compatible = "innolux,p120zdg-bf1",
  3831. .data = &innolux_p120zdg_bf1,
  3832. }, {
  3833. .compatible = "innolux,zj070na-01p",
  3834. .data = &innolux_zj070na_01p,
  3835. }, {
  3836. .compatible = "ivo,m133nwf4-r0",
  3837. .data = &ivo_m133nwf4_r0,
  3838. }, {
  3839. .compatible = "kingdisplay,kd116n21-30nv-a010",
  3840. .data = &kingdisplay_kd116n21_30nv_a010,
  3841. }, {
  3842. .compatible = "koe,tx14d24vm1bpa",
  3843. .data = &koe_tx14d24vm1bpa,
  3844. }, {
  3845. .compatible = "koe,tx26d202vm0bwa",
  3846. .data = &koe_tx26d202vm0bwa,
  3847. }, {
  3848. .compatible = "koe,tx31d200vm0baa",
  3849. .data = &koe_tx31d200vm0baa,
  3850. }, {
  3851. .compatible = "kyo,tcg121xglp",
  3852. .data = &kyo_tcg121xglp,
  3853. }, {
  3854. .compatible = "lemaker,bl035-rgb-002",
  3855. .data = &lemaker_bl035_rgb_002,
  3856. }, {
  3857. .compatible = "lg,lb070wv8",
  3858. .data = &lg_lb070wv8,
  3859. }, {
  3860. .compatible = "lg,lp079qx1-sp0v",
  3861. .data = &lg_lp079qx1_sp0v,
  3862. }, {
  3863. .compatible = "lg,lp097qx1-spa1",
  3864. .data = &lg_lp097qx1_spa1,
  3865. }, {
  3866. .compatible = "lg,lp120up1",
  3867. .data = &lg_lp120up1,
  3868. }, {
  3869. .compatible = "lg,lp129qe",
  3870. .data = &lg_lp129qe,
  3871. }, {
  3872. .compatible = "logicpd,type28",
  3873. .data = &logicpd_type_28,
  3874. }, {
  3875. .compatible = "logictechno,lt161010-2nhc",
  3876. .data = &logictechno_lt161010_2nh,
  3877. }, {
  3878. .compatible = "logictechno,lt161010-2nhr",
  3879. .data = &logictechno_lt161010_2nh,
  3880. }, {
  3881. .compatible = "logictechno,lt170410-2whc",
  3882. .data = &logictechno_lt170410_2whc,
  3883. }, {
  3884. .compatible = "mitsubishi,aa070mc01-ca1",
  3885. .data = &mitsubishi_aa070mc01,
  3886. }, {
  3887. .compatible = "nec,nl12880bc20-05",
  3888. .data = &nec_nl12880bc20_05,
  3889. }, {
  3890. .compatible = "nec,nl4827hc19-05b",
  3891. .data = &nec_nl4827hc19_05b,
  3892. }, {
  3893. .compatible = "netron-dy,e231732",
  3894. .data = &netron_dy_e231732,
  3895. }, {
  3896. .compatible = "neweast,wjfh116008a",
  3897. .data = &neweast_wjfh116008a,
  3898. }, {
  3899. .compatible = "newhaven,nhd-4.3-480272ef-atxl",
  3900. .data = &newhaven_nhd_43_480272ef_atxl,
  3901. }, {
  3902. .compatible = "nlt,nl192108ac18-02d",
  3903. .data = &nlt_nl192108ac18_02d,
  3904. }, {
  3905. .compatible = "nvd,9128",
  3906. .data = &nvd_9128,
  3907. }, {
  3908. .compatible = "okaya,rs800480t-7x0gp",
  3909. .data = &okaya_rs800480t_7x0gp,
  3910. }, {
  3911. .compatible = "olimex,lcd-olinuxino-43-ts",
  3912. .data = &olimex_lcd_olinuxino_43ts,
  3913. }, {
  3914. .compatible = "ontat,yx700wv03",
  3915. .data = &ontat_yx700wv03,
  3916. }, {
  3917. .compatible = "ortustech,com37h3m05dtc",
  3918. .data = &ortustech_com37h3m,
  3919. }, {
  3920. .compatible = "ortustech,com37h3m99dtc",
  3921. .data = &ortustech_com37h3m,
  3922. }, {
  3923. .compatible = "ortustech,com43h4m85ulc",
  3924. .data = &ortustech_com43h4m85ulc,
  3925. }, {
  3926. .compatible = "osddisplays,osd070t1718-19ts",
  3927. .data = &osddisplays_osd070t1718_19ts,
  3928. }, {
  3929. .compatible = "pda,91-00156-a0",
  3930. .data = &pda_91_00156_a0,
  3931. }, {
  3932. .compatible = "powertip,ph800480t013-idf02",
  3933. .data = &powertip_ph800480t013_idf02,
  3934. }, {
  3935. .compatible = "qiaodian,qd43003c0-40",
  3936. .data = &qd43003c0_40,
  3937. }, {
  3938. .compatible = "rocktech,rk070er9427",
  3939. .data = &rocktech_rk070er9427,
  3940. }, {
  3941. .compatible = "rocktech,rk101ii01d-ct",
  3942. .data = &rocktech_rk101ii01d_ct,
  3943. }, {
  3944. .compatible = "samsung,lsn122dl01-c01",
  3945. .data = &samsung_lsn122dl01_c01,
  3946. }, {
  3947. .compatible = "samsung,ltn101nt05",
  3948. .data = &samsung_ltn101nt05,
  3949. }, {
  3950. .compatible = "samsung,ltn140at29-301",
  3951. .data = &samsung_ltn140at29_301,
  3952. }, {
  3953. .compatible = "satoz,sat050at40h12r2",
  3954. .data = &satoz_sat050at40h12r2,
  3955. }, {
  3956. .compatible = "sharp,ld-d5116z01b",
  3957. .data = &sharp_ld_d5116z01b,
  3958. }, {
  3959. .compatible = "sharp,lq035q7db03",
  3960. .data = &sharp_lq035q7db03,
  3961. }, {
  3962. .compatible = "sharp,lq070y3dg3b",
  3963. .data = &sharp_lq070y3dg3b,
  3964. }, {
  3965. .compatible = "sharp,lq101k1ly04",
  3966. .data = &sharp_lq101k1ly04,
  3967. }, {
  3968. .compatible = "sharp,lq123p1jx31",
  3969. .data = &sharp_lq123p1jx31,
  3970. }, {
  3971. .compatible = "sharp,ls020b1dd01d",
  3972. .data = &sharp_ls020b1dd01d,
  3973. }, {
  3974. .compatible = "shelly,sca07010-bfn-lnn",
  3975. .data = &shelly_sca07010_bfn_lnn,
  3976. }, {
  3977. .compatible = "starry,kr070pe2t",
  3978. .data = &starry_kr070pe2t,
  3979. }, {
  3980. .compatible = "starry,kr122ea0sra",
  3981. .data = &starry_kr122ea0sra,
  3982. }, {
  3983. .compatible = "tfc,s9700rtwv43tr-01b",
  3984. .data = &tfc_s9700rtwv43tr_01b,
  3985. }, {
  3986. .compatible = "tianma,tm070jdhg30",
  3987. .data = &tianma_tm070jdhg30,
  3988. }, {
  3989. .compatible = "tianma,tm070jvhg33",
  3990. .data = &tianma_tm070jvhg33,
  3991. }, {
  3992. .compatible = "tianma,tm070rvhg71",
  3993. .data = &tianma_tm070rvhg71,
  3994. }, {
  3995. .compatible = "ti,nspire-cx-lcd-panel",
  3996. .data = &ti_nspire_cx_lcd_panel,
  3997. }, {
  3998. .compatible = "ti,nspire-classic-lcd-panel",
  3999. .data = &ti_nspire_classic_lcd_panel,
  4000. }, {
  4001. .compatible = "toshiba,lt089ac29000",
  4002. .data = &toshiba_lt089ac29000,
  4003. }, {
  4004. .compatible = "tpk,f07a-0102",
  4005. .data = &tpk_f07a_0102,
  4006. }, {
  4007. .compatible = "tpk,f10a-0102",
  4008. .data = &tpk_f10a_0102,
  4009. }, {
  4010. .compatible = "urt,umsh-8596md-t",
  4011. .data = &urt_umsh_8596md_parallel,
  4012. }, {
  4013. .compatible = "urt,umsh-8596md-1t",
  4014. .data = &urt_umsh_8596md_parallel,
  4015. }, {
  4016. .compatible = "urt,umsh-8596md-7t",
  4017. .data = &urt_umsh_8596md_parallel,
  4018. }, {
  4019. .compatible = "urt,umsh-8596md-11t",
  4020. .data = &urt_umsh_8596md_lvds,
  4021. }, {
  4022. .compatible = "urt,umsh-8596md-19t",
  4023. .data = &urt_umsh_8596md_lvds,
  4024. }, {
  4025. .compatible = "urt,umsh-8596md-20t",
  4026. .data = &urt_umsh_8596md_parallel,
  4027. }, {
  4028. .compatible = "vxt,vl050-8048nt-c01",
  4029. .data = &vl050_8048nt_c01,
  4030. }, {
  4031. .compatible = "winstar,wf35ltiacd",
  4032. .data = &winstar_wf35ltiacd,
  4033. }, {
  4034. .compatible = "light,dummy-panel",
  4035. .data = &light_dummy_panel,
  4036. }, {
  4037. /* Must be the last entry */
  4038. .compatible = "panel-dpi",
  4039. .data = &panel_dpi,
  4040. }, {
  4041. /* sentinel */
  4042. }
  4043. };
  4044. MODULE_DEVICE_TABLE(of, platform_of_match);
  4045. static int panel_simple_platform_probe(struct platform_device *pdev)
  4046. {
  4047. const struct of_device_id *id;
  4048. id = of_match_node(platform_of_match, pdev->dev.of_node);
  4049. if (!id)
  4050. return -ENODEV;
  4051. return panel_simple_probe(&pdev->dev, id->data);
  4052. }
  4053. static int panel_simple_platform_remove(struct platform_device *pdev)
  4054. {
  4055. return panel_simple_remove(&pdev->dev);
  4056. }
  4057. static void panel_simple_platform_shutdown(struct platform_device *pdev)
  4058. {
  4059. panel_simple_shutdown(&pdev->dev);
  4060. }
  4061. static struct platform_driver panel_simple_platform_driver = {
  4062. .driver = {
  4063. .name = "panel-simple",
  4064. .of_match_table = platform_of_match,
  4065. },
  4066. .probe = panel_simple_platform_probe,
  4067. .remove = panel_simple_platform_remove,
  4068. .shutdown = panel_simple_platform_shutdown,
  4069. };
  4070. struct panel_desc_dsi {
  4071. struct panel_desc desc;
  4072. unsigned long flags;
  4073. enum mipi_dsi_pixel_format format;
  4074. unsigned int lanes;
  4075. };
  4076. static const struct drm_display_mode auo_b080uan01_mode = {
  4077. .clock = 154500,
  4078. .hdisplay = 1200,
  4079. .hsync_start = 1200 + 62,
  4080. .hsync_end = 1200 + 62 + 4,
  4081. .htotal = 1200 + 62 + 4 + 62,
  4082. .vdisplay = 1920,
  4083. .vsync_start = 1920 + 9,
  4084. .vsync_end = 1920 + 9 + 2,
  4085. .vtotal = 1920 + 9 + 2 + 8,
  4086. };
  4087. static const struct panel_desc_dsi auo_b080uan01 = {
  4088. .desc = {
  4089. .modes = &auo_b080uan01_mode,
  4090. .num_modes = 1,
  4091. .bpc = 8,
  4092. .size = {
  4093. .width = 108,
  4094. .height = 272,
  4095. },
  4096. .connector_type = DRM_MODE_CONNECTOR_DSI,
  4097. },
  4098. .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
  4099. .format = MIPI_DSI_FMT_RGB888,
  4100. .lanes = 4,
  4101. };
  4102. static const struct drm_display_mode boe_tv080wum_nl0_mode = {
  4103. .clock = 160000,
  4104. .hdisplay = 1200,
  4105. .hsync_start = 1200 + 120,
  4106. .hsync_end = 1200 + 120 + 20,
  4107. .htotal = 1200 + 120 + 20 + 21,
  4108. .vdisplay = 1920,
  4109. .vsync_start = 1920 + 21,
  4110. .vsync_end = 1920 + 21 + 3,
  4111. .vtotal = 1920 + 21 + 3 + 18,
  4112. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  4113. };
  4114. static const struct panel_desc_dsi boe_tv080wum_nl0 = {
  4115. .desc = {
  4116. .modes = &boe_tv080wum_nl0_mode,
  4117. .num_modes = 1,
  4118. .size = {
  4119. .width = 107,
  4120. .height = 172,
  4121. },
  4122. .connector_type = DRM_MODE_CONNECTOR_DSI,
  4123. },
  4124. .flags = MIPI_DSI_MODE_VIDEO |
  4125. MIPI_DSI_MODE_VIDEO_BURST |
  4126. MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
  4127. .format = MIPI_DSI_FMT_RGB888,
  4128. .lanes = 4,
  4129. };
  4130. static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
  4131. .clock = 71000,
  4132. .hdisplay = 800,
  4133. .hsync_start = 800 + 32,
  4134. .hsync_end = 800 + 32 + 1,
  4135. .htotal = 800 + 32 + 1 + 57,
  4136. .vdisplay = 1280,
  4137. .vsync_start = 1280 + 28,
  4138. .vsync_end = 1280 + 28 + 1,
  4139. .vtotal = 1280 + 28 + 1 + 14,
  4140. };
  4141. static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
  4142. .desc = {
  4143. .modes = &lg_ld070wx3_sl01_mode,
  4144. .num_modes = 1,
  4145. .bpc = 8,
  4146. .size = {
  4147. .width = 94,
  4148. .height = 151,
  4149. },
  4150. .connector_type = DRM_MODE_CONNECTOR_DSI,
  4151. },
  4152. .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
  4153. .format = MIPI_DSI_FMT_RGB888,
  4154. .lanes = 4,
  4155. };
  4156. static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
  4157. .clock = 67000,
  4158. .hdisplay = 720,
  4159. .hsync_start = 720 + 12,
  4160. .hsync_end = 720 + 12 + 4,
  4161. .htotal = 720 + 12 + 4 + 112,
  4162. .vdisplay = 1280,
  4163. .vsync_start = 1280 + 8,
  4164. .vsync_end = 1280 + 8 + 4,
  4165. .vtotal = 1280 + 8 + 4 + 12,
  4166. };
  4167. static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
  4168. .desc = {
  4169. .modes = &lg_lh500wx1_sd03_mode,
  4170. .num_modes = 1,
  4171. .bpc = 8,
  4172. .size = {
  4173. .width = 62,
  4174. .height = 110,
  4175. },
  4176. .connector_type = DRM_MODE_CONNECTOR_DSI,
  4177. },
  4178. .flags = MIPI_DSI_MODE_VIDEO,
  4179. .format = MIPI_DSI_FMT_RGB888,
  4180. .lanes = 4,
  4181. };
  4182. static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
  4183. .clock = 157200,
  4184. .hdisplay = 1920,
  4185. .hsync_start = 1920 + 154,
  4186. .hsync_end = 1920 + 154 + 16,
  4187. .htotal = 1920 + 154 + 16 + 32,
  4188. .vdisplay = 1200,
  4189. .vsync_start = 1200 + 17,
  4190. .vsync_end = 1200 + 17 + 2,
  4191. .vtotal = 1200 + 17 + 2 + 16,
  4192. };
  4193. static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
  4194. .desc = {
  4195. .modes = &panasonic_vvx10f004b00_mode,
  4196. .num_modes = 1,
  4197. .bpc = 8,
  4198. .size = {
  4199. .width = 217,
  4200. .height = 136,
  4201. },
  4202. .connector_type = DRM_MODE_CONNECTOR_DSI,
  4203. },
  4204. .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
  4205. MIPI_DSI_CLOCK_NON_CONTINUOUS,
  4206. .format = MIPI_DSI_FMT_RGB888,
  4207. .lanes = 4,
  4208. };
  4209. static const struct drm_display_mode lg_acx467akm_7_mode = {
  4210. .clock = 150000,
  4211. .hdisplay = 1080,
  4212. .hsync_start = 1080 + 2,
  4213. .hsync_end = 1080 + 2 + 2,
  4214. .htotal = 1080 + 2 + 2 + 2,
  4215. .vdisplay = 1920,
  4216. .vsync_start = 1920 + 2,
  4217. .vsync_end = 1920 + 2 + 2,
  4218. .vtotal = 1920 + 2 + 2 + 2,
  4219. };
  4220. static const struct panel_desc_dsi lg_acx467akm_7 = {
  4221. .desc = {
  4222. .modes = &lg_acx467akm_7_mode,
  4223. .num_modes = 1,
  4224. .bpc = 8,
  4225. .size = {
  4226. .width = 62,
  4227. .height = 110,
  4228. },
  4229. .connector_type = DRM_MODE_CONNECTOR_DSI,
  4230. },
  4231. .flags = 0,
  4232. .format = MIPI_DSI_FMT_RGB888,
  4233. .lanes = 4,
  4234. };
  4235. static const struct drm_display_mode osd101t2045_53ts_mode = {
  4236. .clock = 154500,
  4237. .hdisplay = 1920,
  4238. .hsync_start = 1920 + 112,
  4239. .hsync_end = 1920 + 112 + 16,
  4240. .htotal = 1920 + 112 + 16 + 32,
  4241. .vdisplay = 1200,
  4242. .vsync_start = 1200 + 16,
  4243. .vsync_end = 1200 + 16 + 2,
  4244. .vtotal = 1200 + 16 + 2 + 16,
  4245. .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
  4246. };
  4247. static const struct panel_desc_dsi osd101t2045_53ts = {
  4248. .desc = {
  4249. .modes = &osd101t2045_53ts_mode,
  4250. .num_modes = 1,
  4251. .bpc = 8,
  4252. .size = {
  4253. .width = 217,
  4254. .height = 136,
  4255. },
  4256. .connector_type = DRM_MODE_CONNECTOR_DSI,
  4257. },
  4258. .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
  4259. MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
  4260. MIPI_DSI_MODE_EOT_PACKET,
  4261. .format = MIPI_DSI_FMT_RGB888,
  4262. .lanes = 4,
  4263. };
  4264. static const struct drm_display_mode htl_hpk070h275_mode = {
  4265. .clock = 26000,
  4266. .hdisplay = 600,
  4267. .hsync_start = 600 + 80,
  4268. .hsync_end = 600 + 80 + 2,
  4269. .htotal = 600 + 80 + 2 + 60,
  4270. .vdisplay = 1024,
  4271. .vsync_start = 1024 + 35,
  4272. .vsync_end = 1024 + 35 + 1,
  4273. .vtotal = 1024 + 35 + 1 + 25,
  4274. .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
  4275. };
  4276. static const struct panel_desc_dsi hlt_hpk070h275 = {
  4277. .desc = {
  4278. .modes = &htl_hpk070h275_mode,
  4279. .num_modes = 1,
  4280. .bpc = 8,
  4281. .size = {
  4282. .width = 89,
  4283. .height = 152,
  4284. },
  4285. .connector_type = DRM_MODE_CONNECTOR_DSI,
  4286. },
  4287. .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST,
  4288. .format = MIPI_DSI_FMT_RGB888,
  4289. .lanes = 4,
  4290. };
  4291. static const struct of_device_id dsi_of_match[] = {
  4292. {
  4293. .compatible = "auo,b080uan01",
  4294. .data = &auo_b080uan01
  4295. }, {
  4296. .compatible = "boe,tv080wum-nl0",
  4297. .data = &boe_tv080wum_nl0
  4298. }, {
  4299. .compatible = "lg,ld070wx3-sl01",
  4300. .data = &lg_ld070wx3_sl01
  4301. }, {
  4302. .compatible = "lg,lh500wx1-sd03",
  4303. .data = &lg_lh500wx1_sd03
  4304. }, {
  4305. .compatible = "panasonic,vvx10f004b00",
  4306. .data = &panasonic_vvx10f004b00
  4307. }, {
  4308. .compatible = "lg,acx467akm-7",
  4309. .data = &lg_acx467akm_7
  4310. }, {
  4311. .compatible = "osddisplays,osd101t2045-53ts",
  4312. .data = &osd101t2045_53ts
  4313. }, {
  4314. .compatible = "hlt,hpk070h275",
  4315. .data = &hlt_hpk070h275
  4316. }, {
  4317. /* sentinel */
  4318. }
  4319. };
  4320. MODULE_DEVICE_TABLE(of, dsi_of_match);
  4321. static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
  4322. {
  4323. const struct panel_desc_dsi *desc;
  4324. const struct of_device_id *id;
  4325. int err;
  4326. id = of_match_node(dsi_of_match, dsi->dev.of_node);
  4327. if (!id)
  4328. return -ENODEV;
  4329. desc = id->data;
  4330. err = panel_simple_probe(&dsi->dev, &desc->desc);
  4331. if (err < 0)
  4332. return err;
  4333. dsi->mode_flags = desc->flags;
  4334. dsi->format = desc->format;
  4335. dsi->lanes = desc->lanes;
  4336. err = mipi_dsi_attach(dsi);
  4337. if (err) {
  4338. struct panel_simple *panel = dev_get_drvdata(&dsi->dev);
  4339. drm_panel_remove(&panel->base);
  4340. }
  4341. return err;
  4342. }
  4343. static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
  4344. {
  4345. int err;
  4346. err = mipi_dsi_detach(dsi);
  4347. if (err < 0)
  4348. dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
  4349. return panel_simple_remove(&dsi->dev);
  4350. }
  4351. static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
  4352. {
  4353. panel_simple_shutdown(&dsi->dev);
  4354. }
  4355. static struct mipi_dsi_driver panel_simple_dsi_driver = {
  4356. .driver = {
  4357. .name = "panel-simple-dsi",
  4358. .of_match_table = dsi_of_match,
  4359. },
  4360. .probe = panel_simple_dsi_probe,
  4361. .remove = panel_simple_dsi_remove,
  4362. .shutdown = panel_simple_dsi_shutdown,
  4363. };
  4364. static int __init panel_simple_init(void)
  4365. {
  4366. int err;
  4367. err = platform_driver_register(&panel_simple_platform_driver);
  4368. if (err < 0)
  4369. return err;
  4370. if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
  4371. err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
  4372. if (err < 0)
  4373. return err;
  4374. }
  4375. return 0;
  4376. }
  4377. module_init(panel_simple_init);
  4378. static void __exit panel_simple_exit(void)
  4379. {
  4380. if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
  4381. mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
  4382. platform_driver_unregister(&panel_simple_platform_driver);
  4383. }
  4384. module_exit(panel_simple_exit);
  4385. MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
  4386. MODULE_DESCRIPTION("DRM Driver for Simple Panels");
  4387. MODULE_LICENSE("GPL and additional rights");