panel-himax8394.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Diiver for panels based on Himax HX8394 controller
  4. * Copyright (c) 2023, Alibaba-inc Co., Ltd
  5. *
  6. */
  7. #include <linux/delay.h>
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/of.h>
  11. #include <linux/of_device.h>
  12. #include <linux/gpio/consumer.h>
  13. #include <linux/regulator/consumer.h>
  14. #include <drm/drm_device.h>
  15. #include <drm/drm_mipi_dsi.h>
  16. #include <drm/drm_modes.h>
  17. #include <drm/drm_panel.h>
  18. #include <video/mipi_display.h>
  19. struct hx8394_panel_cmd {
  20. char cmdlen;
  21. char cmddata[0x40];
  22. };
  23. struct hx8394_panel_desc {
  24. const struct drm_display_mode *display_mode;
  25. unsigned long mode_flags;
  26. enum mipi_dsi_pixel_format format;
  27. unsigned int lanes;
  28. const struct hx8394_panel_cmd *on_cmds;
  29. unsigned int on_cmds_num;
  30. };
  31. struct panel_info {
  32. struct drm_panel base;
  33. struct mipi_dsi_device *link;
  34. const struct hx8394_panel_desc *desc;
  35. struct gpio_desc *reset;
  36. struct regulator *hsvcc;
  37. struct regulator *vspn3v3;
  38. bool prepared;
  39. bool enabled;
  40. };
  41. static inline struct panel_info *to_panel_info(struct drm_panel *panel)
  42. {
  43. return container_of(panel, struct panel_info, base);
  44. }
  45. static int hx8394_send_mipi_cmds(struct drm_panel *panel, const struct hx8394_panel_cmd *cmds)
  46. {
  47. struct panel_info *pinfo = to_panel_info(panel);
  48. unsigned int i = 0;
  49. int err;
  50. for (i = 0; i < pinfo->desc->on_cmds_num; i++) {
  51. err = mipi_dsi_dcs_write_buffer(pinfo->link, &(cmds[i].cmddata[0]), cmds[i].cmdlen);
  52. if (err < 0)
  53. return err;
  54. }
  55. return 0;
  56. }
  57. static int hx8394_panel_disable(struct drm_panel *panel)
  58. {
  59. struct panel_info *pinfo = to_panel_info(panel);
  60. int err;
  61. if (!pinfo->enabled)
  62. return 0;
  63. err = mipi_dsi_dcs_set_display_off(pinfo->link);
  64. if (err < 0) {
  65. dev_err(panel->dev, "failed to set display off: %d\n", err);
  66. return err;
  67. }
  68. pinfo->enabled = false;
  69. return 0;
  70. }
  71. static int hx8394_panel_unprepare(struct drm_panel *panel)
  72. {
  73. struct panel_info *pinfo = to_panel_info(panel);
  74. int err;
  75. if (!pinfo->prepared)
  76. return 0;
  77. err = mipi_dsi_dcs_set_display_off(pinfo->link);
  78. if (err < 0)
  79. dev_err(panel->dev, "failed to set display off: %d\n", err);
  80. err = mipi_dsi_dcs_enter_sleep_mode(pinfo->link);
  81. if (err < 0)
  82. dev_err(panel->dev, "failed to enter sleep mode: %d\n", err);
  83. /* sleep_mode_delay: 1ms - 2ms */
  84. usleep_range(1000, 2000);
  85. gpiod_set_value(pinfo->reset, 1);
  86. regulator_disable(pinfo->hsvcc);
  87. regulator_disable(pinfo->vspn3v3);
  88. pinfo->prepared = false;
  89. return 0;
  90. }
  91. static int hx8394_panel_prepare(struct drm_panel *panel)
  92. {
  93. struct panel_info *pinfo = to_panel_info(panel);
  94. int ret;
  95. if (pinfo->prepared)
  96. return 0;
  97. gpiod_set_value(pinfo->reset, 1);
  98. /* Power the panel */
  99. ret = regulator_enable(pinfo->hsvcc);
  100. if (ret) {
  101. dev_err(pinfo->base.dev, "Failed to enable hsvcc supply: %d\n", ret);
  102. return ret;
  103. }
  104. usleep_range(1000, 2000);
  105. ret = regulator_enable(pinfo->vspn3v3);
  106. if (ret) {
  107. dev_err(pinfo->base.dev, "Failed to enable vspn3v3 supply: %d\n", ret);
  108. goto fail;
  109. }
  110. usleep_range(5000, 6000);
  111. gpiod_set_value(pinfo->reset, 0);
  112. msleep(180);
  113. pinfo->prepared = true;
  114. return 0;
  115. fail:
  116. gpiod_set_value(pinfo->reset, 1);
  117. regulator_disable(pinfo->hsvcc);
  118. return ret;
  119. }
  120. static int hx8394_read_id(struct mipi_dsi_device *dsi, u8 *id1)
  121. {
  122. int ret;
  123. ret = mipi_dsi_dcs_read(dsi, 0xDA, id1, 1);
  124. if (ret < 0) {
  125. dev_err(&dsi->dev, "could not read ID1\n");
  126. return ret;
  127. }
  128. dev_info(&dsi->dev, "ID1 : 0x%02x\n", *id1);
  129. return 0;
  130. }
  131. static int hx8394_panel_enable(struct drm_panel *panel)
  132. {
  133. struct panel_info *pinfo = to_panel_info(panel);
  134. int ret;
  135. u8 id1;
  136. if (pinfo->enabled)
  137. return 0;
  138. ret = hx8394_read_id(pinfo->link, &id1);
  139. if (ret < 0)
  140. dev_info(panel->dev, "No LCD connected,pls check your hardware! ret:%d\n", ret);
  141. /* send init code */
  142. ret = hx8394_send_mipi_cmds(panel, pinfo->desc->on_cmds);
  143. if (ret < 0) {
  144. dev_err(panel->dev, "failed to send DCS Init Code: %d\n", ret);
  145. return ret;
  146. }
  147. ret = mipi_dsi_dcs_exit_sleep_mode(pinfo->link);
  148. if (ret < 0) {
  149. dev_err(panel->dev, "failed to exit sleep mode: %d\n", ret);
  150. return ret;
  151. }
  152. msleep(120);
  153. ret = mipi_dsi_dcs_set_display_on(pinfo->link);
  154. if (ret < 0) {
  155. dev_err(panel->dev, "failed to set display on: %d\n", ret);
  156. return ret;
  157. }
  158. pinfo->enabled = true;
  159. return 0;
  160. }
  161. static int hx8394_panel_get_modes(struct drm_panel *panel,
  162. struct drm_connector *connector)
  163. {
  164. struct panel_info *pinfo = to_panel_info(panel);
  165. const struct drm_display_mode *m = pinfo->desc->display_mode;
  166. struct drm_display_mode *mode;
  167. mode = drm_mode_duplicate(connector->dev, m);
  168. if (!mode) {
  169. dev_err(pinfo->base.dev, "failed to add mode %ux%u@%u\n",
  170. m->hdisplay, m->vdisplay, drm_mode_vrefresh(m));
  171. return -ENOMEM;
  172. }
  173. drm_mode_set_name(mode);
  174. mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
  175. drm_mode_probed_add(connector, mode);
  176. connector->display_info.width_mm = mode->width_mm;
  177. connector->display_info.height_mm = mode->height_mm;
  178. return 1;
  179. }
  180. static const struct drm_panel_funcs panel_funcs = {
  181. .disable = hx8394_panel_disable,
  182. .unprepare = hx8394_panel_unprepare,
  183. .prepare = hx8394_panel_prepare,
  184. .enable = hx8394_panel_enable,
  185. .get_modes = hx8394_panel_get_modes,
  186. };
  187. static const struct drm_display_mode hx8394_default_mode = {
  188. .clock = 76000,
  189. .hdisplay = 720,
  190. .hsync_start = 720 + 45,
  191. .hsync_end = 720 + 45 + 8,
  192. .htotal = 720 + 45 + 8 + 45,
  193. .vdisplay = 1280,
  194. .vsync_start = 1280 + 16,
  195. .vsync_end = 1280 + 16 + 8,
  196. .vtotal = 1280 + 16 + 8 + 16,
  197. .width_mm = 62,
  198. .height_mm = 110,
  199. .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
  200. };
  201. static const struct hx8394_panel_cmd hx8394_on_cmds[] = {
  202. { .cmdlen = 4, .cmddata = {0xB9, 0xFF, 0x83, 0x94} },
  203. { .cmdlen = 11, .cmddata = {0xB1, 0x48, 0x0A, 0x6A, 0x09, 0x33, 0x54,
  204. 0x71, 0x71, 0x2E, 0x45} },
  205. { .cmdlen = 7, .cmddata = {0xBA, 0x63, 0x03, 0x68, 0x6B, 0xB2, 0xC0} },
  206. { .cmdlen = 7, .cmddata = {0xB2, 0x00, 0x80, 0x64, 0x0C, 0x06, 0x2F} },
  207. { .cmdlen = 22, .cmddata = {0xB4, 0x1C, 0x78, 0x1C, 0x78, 0x1C, 0x78, 0x01,
  208. 0x0C, 0x86, 0x75, 0x00, 0x3F, 0x1C, 0x78, 0x1C,
  209. 0x78, 0x1C, 0x78, 0x01, 0x0C, 0x86} },
  210. { .cmdlen = 34, .cmddata = {0xD3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
  211. 0x08, 0x32, 0x10, 0x05, 0x00, 0x05, 0x32, 0x13,
  212. 0xC1, 0x00, 0x01, 0x32, 0x10, 0x08, 0x00, 0x00,
  213. 0x37, 0x03, 0x07, 0x07, 0x37, 0x05, 0x05, 0x37,
  214. 0x0C, 0x40} },
  215. { .cmdlen = 45, .cmddata = {0xD5, 0x18, 0x18, 0x18, 0x18, 0x22, 0x23, 0x20,
  216. 0x21, 0x04, 0x05, 0x06, 0x07, 0x00, 0x01, 0x02,
  217. 0x03, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
  218. 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
  219. 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
  220. 0x18, 0x19, 0x19, 0x19, 0x19} },
  221. { .cmdlen = 45, .cmddata = {0xD6, 0x18, 0x18, 0x19, 0x19, 0x21, 0x20, 0x23,
  222. 0x22, 0x03, 0x02, 0x01, 0x00, 0x07, 0x06, 0x05,
  223. 0x04, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
  224. 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
  225. 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
  226. 0x18, 0x19, 0x19, 0x18, 0x18} },
  227. { .cmdlen = 59, .cmddata = {0xE0, 0x07, 0x08, 0x09, 0x0D, 0x10, 0x14, 0x16,
  228. 0x13, 0x24, 0x36, 0x48, 0x4A, 0x58, 0x6F, 0x76,
  229. 0x80, 0x97, 0xA5, 0xA8, 0xB5, 0xC6, 0x62, 0x63,
  230. 0x68, 0x6F, 0x72, 0x78, 0x7F, 0x7F, 0x00, 0x02,
  231. 0x08, 0x0D, 0x0C, 0x0E, 0x0F, 0x10, 0x24, 0x36,
  232. 0x48, 0x4A, 0x58, 0x6F, 0x78, 0x82, 0x99, 0xA4,
  233. 0xA0, 0xB1, 0xC0, 0x5E, 0x5E, 0x64, 0x6B, 0x6C,
  234. 0x73, 0x7F, 0x7F} },
  235. { .cmdlen = 2, .cmddata = {0xCC, 0x03} },
  236. { .cmdlen = 3, .cmddata = {0xC0, 0x1F, 0x73} },
  237. { .cmdlen = 3, .cmddata = {0xB6, 0x90, 0x90} },
  238. { .cmdlen = 2, .cmddata = {0xD4, 0x02} },
  239. { .cmdlen = 2, .cmddata = {0xBD, 0x01} },
  240. { .cmdlen = 2, .cmddata = {0xB1, 0x00} },
  241. { .cmdlen = 2, .cmddata = {0xBD, 0x00} },
  242. { .cmdlen = 8, .cmddata = {0xBF, 0x40, 0x81, 0x50, 0x00, 0x1A, 0xFC, 0x01} },
  243. { .cmdlen = 2, .cmddata = {0x36, 0x02} },
  244. };
  245. static const struct hx8394_panel_desc hx8394_desc = {
  246. .display_mode = &hx8394_default_mode,
  247. .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_VIDEO_BURST,
  248. .format = MIPI_DSI_FMT_RGB888,
  249. .lanes = 4,
  250. .on_cmds = hx8394_on_cmds,
  251. .on_cmds_num = ARRAY_SIZE(hx8394_on_cmds),
  252. };
  253. static const struct of_device_id panel_of_match[] = {
  254. {
  255. .compatible = "himax,hx8394",
  256. .data = &hx8394_desc,
  257. },
  258. {
  259. /* sentinel */
  260. }
  261. };
  262. MODULE_DEVICE_TABLE(of, panel_of_match);
  263. static int hx8394_panel_add(struct panel_info *pinfo)
  264. {
  265. struct device *dev = &pinfo->link->dev;
  266. int ret;
  267. pinfo->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
  268. if (IS_ERR(pinfo->reset))
  269. return dev_err_probe(dev, PTR_ERR(pinfo->reset),
  270. "Couldn't get our reset GPIO\n");
  271. pinfo->hsvcc = devm_regulator_get(dev, "hsvcc");
  272. if (IS_ERR(pinfo->hsvcc))
  273. return dev_err_probe(dev, PTR_ERR(pinfo->hsvcc),
  274. "Failed to request hsvcc regulator\n");
  275. pinfo->vspn3v3 = devm_regulator_get(dev, "vspn3v3");
  276. if (IS_ERR(pinfo->vspn3v3))
  277. return dev_err_probe(dev, PTR_ERR(pinfo->vspn3v3),
  278. "Failed to request vspn3v3 regulator\n");
  279. drm_panel_init(&pinfo->base, dev, &panel_funcs,
  280. DRM_MODE_CONNECTOR_DSI);
  281. ret = drm_panel_of_backlight(&pinfo->base);
  282. if (ret)
  283. return ret;
  284. drm_panel_add(&pinfo->base);
  285. return 0;
  286. }
  287. static int hx8394_panel_probe(struct mipi_dsi_device *dsi)
  288. {
  289. struct panel_info *pinfo;
  290. const struct hx8394_panel_desc *desc;
  291. int err;
  292. pinfo = devm_kzalloc(&dsi->dev, sizeof(*pinfo), GFP_KERNEL);
  293. if (!pinfo)
  294. return -ENOMEM;
  295. desc = of_device_get_match_data(&dsi->dev);
  296. dsi->mode_flags = desc->mode_flags;
  297. dsi->format = desc->format;
  298. dsi->lanes = desc->lanes;
  299. pinfo->desc = desc;
  300. pinfo->link = dsi;
  301. mipi_dsi_set_drvdata(dsi, pinfo);
  302. err = hx8394_panel_add(pinfo);
  303. if (err < 0)
  304. return err;
  305. err = mipi_dsi_attach(dsi);
  306. if (err < 0)
  307. drm_panel_remove(&pinfo->base);
  308. return err;
  309. }
  310. static int hx8394_panel_remove(struct mipi_dsi_device *dsi)
  311. {
  312. struct panel_info *pinfo = mipi_dsi_get_drvdata(dsi);
  313. int err;
  314. err = hx8394_panel_disable(&pinfo->base);
  315. if (err < 0)
  316. dev_err(&dsi->dev, "failed to disable panel: %d\n", err);
  317. err = hx8394_panel_unprepare(&pinfo->base);
  318. if (err < 0)
  319. dev_err(&dsi->dev, "failed to unprepare panel: %d\n", err);
  320. err = mipi_dsi_detach(dsi);
  321. if (err < 0)
  322. dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
  323. drm_panel_remove(&pinfo->base);
  324. return 0;
  325. }
  326. static void hx8394_panel_shutdown(struct mipi_dsi_device *dsi)
  327. {
  328. struct panel_info *pinfo = mipi_dsi_get_drvdata(dsi);
  329. hx8394_panel_disable(&pinfo->base);
  330. hx8394_panel_unprepare(&pinfo->base);
  331. }
  332. static struct mipi_dsi_driver panel_driver = {
  333. .driver = {
  334. .name = "panel-himax8394",
  335. .of_match_table = panel_of_match,
  336. },
  337. .probe = hx8394_panel_probe,
  338. .remove = hx8394_panel_remove,
  339. .shutdown = hx8394_panel_shutdown,
  340. };
  341. module_mipi_dsi_driver(panel_driver);
  342. MODULE_DESCRIPTION("Himax8394 driver");
  343. MODULE_LICENSE("GPL v2");