panel-feiyang-fy07024di26a30d.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Amarula Solutions
  4. * Author: Jagan Teki <jagan@amarulasolutions.com>
  5. */
  6. #include <drm/drm_mipi_dsi.h>
  7. #include <drm/drm_modes.h>
  8. #include <drm/drm_panel.h>
  9. #include <linux/gpio/consumer.h>
  10. #include <linux/delay.h>
  11. #include <linux/module.h>
  12. #include <linux/of_device.h>
  13. #include <linux/regulator/consumer.h>
  14. #define FEIYANG_INIT_CMD_LEN 2
  15. struct feiyang {
  16. struct drm_panel panel;
  17. struct mipi_dsi_device *dsi;
  18. struct regulator *dvdd;
  19. struct regulator *avdd;
  20. struct gpio_desc *reset;
  21. };
  22. static inline struct feiyang *panel_to_feiyang(struct drm_panel *panel)
  23. {
  24. return container_of(panel, struct feiyang, panel);
  25. }
  26. struct feiyang_init_cmd {
  27. u8 data[FEIYANG_INIT_CMD_LEN];
  28. };
  29. static const struct feiyang_init_cmd feiyang_init_cmds[] = {
  30. { .data = { 0x80, 0x58 } },
  31. { .data = { 0x81, 0x47 } },
  32. { .data = { 0x82, 0xD4 } },
  33. { .data = { 0x83, 0x88 } },
  34. { .data = { 0x84, 0xA9 } },
  35. { .data = { 0x85, 0xC3 } },
  36. { .data = { 0x86, 0x82 } },
  37. };
  38. static int feiyang_prepare(struct drm_panel *panel)
  39. {
  40. struct feiyang *ctx = panel_to_feiyang(panel);
  41. struct mipi_dsi_device *dsi = ctx->dsi;
  42. unsigned int i;
  43. int ret;
  44. ret = regulator_enable(ctx->dvdd);
  45. if (ret)
  46. return ret;
  47. /* T1 (dvdd start + dvdd rise) 0 < T1 <= 10ms */
  48. msleep(10);
  49. ret = regulator_enable(ctx->avdd);
  50. if (ret)
  51. return ret;
  52. /* T3 (dvdd rise + avdd start + avdd rise) T3 >= 20ms */
  53. msleep(20);
  54. gpiod_set_value(ctx->reset, 0);
  55. /*
  56. * T5 + T6 (avdd rise + video & logic signal rise)
  57. * T5 >= 10ms, 0 < T6 <= 10ms
  58. */
  59. msleep(20);
  60. gpiod_set_value(ctx->reset, 1);
  61. /* T12 (video & logic signal rise + backlight rise) T12 >= 200ms */
  62. msleep(200);
  63. for (i = 0; i < ARRAY_SIZE(feiyang_init_cmds); i++) {
  64. const struct feiyang_init_cmd *cmd =
  65. &feiyang_init_cmds[i];
  66. ret = mipi_dsi_dcs_write_buffer(dsi, cmd->data,
  67. FEIYANG_INIT_CMD_LEN);
  68. if (ret < 0)
  69. return ret;
  70. }
  71. return 0;
  72. }
  73. static int feiyang_enable(struct drm_panel *panel)
  74. {
  75. struct feiyang *ctx = panel_to_feiyang(panel);
  76. /* T12 (video & logic signal rise + backlight rise) T12 >= 200ms */
  77. msleep(200);
  78. mipi_dsi_dcs_set_display_on(ctx->dsi);
  79. return 0;
  80. }
  81. static int feiyang_disable(struct drm_panel *panel)
  82. {
  83. struct feiyang *ctx = panel_to_feiyang(panel);
  84. return mipi_dsi_dcs_set_display_off(ctx->dsi);
  85. }
  86. static int feiyang_unprepare(struct drm_panel *panel)
  87. {
  88. struct feiyang *ctx = panel_to_feiyang(panel);
  89. int ret;
  90. ret = mipi_dsi_dcs_set_display_off(ctx->dsi);
  91. if (ret < 0)
  92. dev_err(panel->dev, "failed to set display off: %d\n", ret);
  93. ret = mipi_dsi_dcs_enter_sleep_mode(ctx->dsi);
  94. if (ret < 0)
  95. dev_err(panel->dev, "failed to enter sleep mode: %d\n", ret);
  96. /* T13 (backlight fall + video & logic signal fall) T13 >= 200ms */
  97. msleep(200);
  98. gpiod_set_value(ctx->reset, 0);
  99. regulator_disable(ctx->avdd);
  100. /* T11 (dvdd rise to fall) 0 < T11 <= 10ms */
  101. msleep(10);
  102. regulator_disable(ctx->dvdd);
  103. return 0;
  104. }
  105. static const struct drm_display_mode feiyang_default_mode = {
  106. .clock = 55000,
  107. .hdisplay = 1024,
  108. .hsync_start = 1024 + 310,
  109. .hsync_end = 1024 + 310 + 20,
  110. .htotal = 1024 + 310 + 20 + 90,
  111. .vdisplay = 600,
  112. .vsync_start = 600 + 12,
  113. .vsync_end = 600 + 12 + 2,
  114. .vtotal = 600 + 12 + 2 + 21,
  115. .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
  116. };
  117. static int feiyang_get_modes(struct drm_panel *panel,
  118. struct drm_connector *connector)
  119. {
  120. struct feiyang *ctx = panel_to_feiyang(panel);
  121. struct drm_display_mode *mode;
  122. mode = drm_mode_duplicate(connector->dev, &feiyang_default_mode);
  123. if (!mode) {
  124. dev_err(&ctx->dsi->dev, "failed to add mode %ux%u@%u\n",
  125. feiyang_default_mode.hdisplay,
  126. feiyang_default_mode.vdisplay,
  127. drm_mode_vrefresh(&feiyang_default_mode));
  128. return -ENOMEM;
  129. }
  130. drm_mode_set_name(mode);
  131. drm_mode_probed_add(connector, mode);
  132. return 1;
  133. }
  134. static const struct drm_panel_funcs feiyang_funcs = {
  135. .disable = feiyang_disable,
  136. .unprepare = feiyang_unprepare,
  137. .prepare = feiyang_prepare,
  138. .enable = feiyang_enable,
  139. .get_modes = feiyang_get_modes,
  140. };
  141. static int feiyang_dsi_probe(struct mipi_dsi_device *dsi)
  142. {
  143. struct feiyang *ctx;
  144. int ret;
  145. ctx = devm_kzalloc(&dsi->dev, sizeof(*ctx), GFP_KERNEL);
  146. if (!ctx)
  147. return -ENOMEM;
  148. mipi_dsi_set_drvdata(dsi, ctx);
  149. ctx->dsi = dsi;
  150. drm_panel_init(&ctx->panel, &dsi->dev, &feiyang_funcs,
  151. DRM_MODE_CONNECTOR_DSI);
  152. ctx->dvdd = devm_regulator_get(&dsi->dev, "dvdd");
  153. if (IS_ERR(ctx->dvdd)) {
  154. dev_err(&dsi->dev, "Couldn't get dvdd regulator\n");
  155. return PTR_ERR(ctx->dvdd);
  156. }
  157. ctx->avdd = devm_regulator_get(&dsi->dev, "avdd");
  158. if (IS_ERR(ctx->avdd)) {
  159. dev_err(&dsi->dev, "Couldn't get avdd regulator\n");
  160. return PTR_ERR(ctx->avdd);
  161. }
  162. ctx->reset = devm_gpiod_get(&dsi->dev, "reset", GPIOD_OUT_LOW);
  163. if (IS_ERR(ctx->reset)) {
  164. dev_err(&dsi->dev, "Couldn't get our reset GPIO\n");
  165. return PTR_ERR(ctx->reset);
  166. }
  167. ret = drm_panel_of_backlight(&ctx->panel);
  168. if (ret)
  169. return ret;
  170. drm_panel_add(&ctx->panel);
  171. dsi->mode_flags = MIPI_DSI_MODE_VIDEO_BURST;
  172. dsi->format = MIPI_DSI_FMT_RGB888;
  173. dsi->lanes = 4;
  174. return mipi_dsi_attach(dsi);
  175. }
  176. static int feiyang_dsi_remove(struct mipi_dsi_device *dsi)
  177. {
  178. struct feiyang *ctx = mipi_dsi_get_drvdata(dsi);
  179. mipi_dsi_detach(dsi);
  180. drm_panel_remove(&ctx->panel);
  181. return 0;
  182. }
  183. static const struct of_device_id feiyang_of_match[] = {
  184. { .compatible = "feiyang,fy07024di26a30d", },
  185. { /* sentinel */ }
  186. };
  187. MODULE_DEVICE_TABLE(of, feiyang_of_match);
  188. static struct mipi_dsi_driver feiyang_driver = {
  189. .probe = feiyang_dsi_probe,
  190. .remove = feiyang_dsi_remove,
  191. .driver = {
  192. .name = "feiyang-fy07024di26a30d",
  193. .of_match_table = feiyang_of_match,
  194. },
  195. };
  196. module_mipi_dsi_driver(feiyang_driver);
  197. MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>");
  198. MODULE_DESCRIPTION("Feiyang FY07024DI26A30-D MIPI-DSI LCD panel");
  199. MODULE_LICENSE("GPL");