drm_dp_helper.c 66 KB

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  1. /*
  2. * Copyright © 2009 Keith Packard
  3. *
  4. * Permission to use, copy, modify, distribute, and sell this software and its
  5. * documentation for any purpose is hereby granted without fee, provided that
  6. * the above copyright notice appear in all copies and that both that copyright
  7. * notice and this permission notice appear in supporting documentation, and
  8. * that the name of the copyright holders not be used in advertising or
  9. * publicity pertaining to distribution of the software without specific,
  10. * written prior permission. The copyright holders make no representations
  11. * about the suitability of this software for any purpose. It is provided "as
  12. * is" without express or implied warranty.
  13. *
  14. * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
  15. * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
  16. * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
  17. * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
  18. * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  19. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
  20. * OF THIS SOFTWARE.
  21. */
  22. #include <linux/delay.h>
  23. #include <linux/errno.h>
  24. #include <linux/i2c.h>
  25. #include <linux/init.h>
  26. #include <linux/kernel.h>
  27. #include <linux/module.h>
  28. #include <linux/sched.h>
  29. #include <linux/seq_file.h>
  30. #include <drm/drm_dp_helper.h>
  31. #include <drm/drm_print.h>
  32. #include <drm/drm_vblank.h>
  33. #include <drm/drm_dp_mst_helper.h>
  34. #include "drm_crtc_helper_internal.h"
  35. /**
  36. * DOC: dp helpers
  37. *
  38. * These functions contain some common logic and helpers at various abstraction
  39. * levels to deal with Display Port sink devices and related things like DP aux
  40. * channel transfers, EDID reading over DP aux channels, decoding certain DPCD
  41. * blocks, ...
  42. */
  43. /* Helpers for DP link training */
  44. static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
  45. {
  46. return link_status[r - DP_LANE0_1_STATUS];
  47. }
  48. static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
  49. int lane)
  50. {
  51. int i = DP_LANE0_1_STATUS + (lane >> 1);
  52. int s = (lane & 1) * 4;
  53. u8 l = dp_link_status(link_status, i);
  54. return (l >> s) & 0xf;
  55. }
  56. bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
  57. int lane_count)
  58. {
  59. u8 lane_align;
  60. u8 lane_status;
  61. int lane;
  62. lane_align = dp_link_status(link_status,
  63. DP_LANE_ALIGN_STATUS_UPDATED);
  64. if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
  65. return false;
  66. for (lane = 0; lane < lane_count; lane++) {
  67. lane_status = dp_get_lane_status(link_status, lane);
  68. if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
  69. return false;
  70. }
  71. return true;
  72. }
  73. EXPORT_SYMBOL(drm_dp_channel_eq_ok);
  74. bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
  75. int lane_count)
  76. {
  77. int lane;
  78. u8 lane_status;
  79. for (lane = 0; lane < lane_count; lane++) {
  80. lane_status = dp_get_lane_status(link_status, lane);
  81. if ((lane_status & DP_LANE_CR_DONE) == 0)
  82. return false;
  83. }
  84. return true;
  85. }
  86. EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
  87. u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
  88. int lane)
  89. {
  90. int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
  91. int s = ((lane & 1) ?
  92. DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
  93. DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
  94. u8 l = dp_link_status(link_status, i);
  95. return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
  96. }
  97. EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
  98. u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
  99. int lane)
  100. {
  101. int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
  102. int s = ((lane & 1) ?
  103. DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
  104. DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
  105. u8 l = dp_link_status(link_status, i);
  106. return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
  107. }
  108. EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
  109. u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE],
  110. unsigned int lane)
  111. {
  112. unsigned int offset = DP_ADJUST_REQUEST_POST_CURSOR2;
  113. u8 value = dp_link_status(link_status, offset);
  114. return (value >> (lane << 1)) & 0x3;
  115. }
  116. EXPORT_SYMBOL(drm_dp_get_adjust_request_post_cursor);
  117. void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
  118. {
  119. unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
  120. DP_TRAINING_AUX_RD_MASK;
  121. if (rd_interval > 4)
  122. DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n",
  123. rd_interval);
  124. if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
  125. rd_interval = 100;
  126. else
  127. rd_interval *= 4 * USEC_PER_MSEC;
  128. usleep_range(rd_interval, rd_interval * 2);
  129. }
  130. EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
  131. void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
  132. {
  133. unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
  134. DP_TRAINING_AUX_RD_MASK;
  135. if (rd_interval > 4)
  136. DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n",
  137. rd_interval);
  138. if (rd_interval == 0)
  139. rd_interval = 400;
  140. else
  141. rd_interval *= 4 * USEC_PER_MSEC;
  142. usleep_range(rd_interval, rd_interval * 2);
  143. }
  144. EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
  145. u8 drm_dp_link_rate_to_bw_code(int link_rate)
  146. {
  147. /* Spec says link_bw = link_rate / 0.27Gbps */
  148. return link_rate / 27000;
  149. }
  150. EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
  151. int drm_dp_bw_code_to_link_rate(u8 link_bw)
  152. {
  153. /* Spec says link_rate = link_bw * 0.27Gbps */
  154. return link_bw * 27000;
  155. }
  156. EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
  157. #define AUX_RETRY_INTERVAL 500 /* us */
  158. static inline void
  159. drm_dp_dump_access(const struct drm_dp_aux *aux,
  160. u8 request, uint offset, void *buffer, int ret)
  161. {
  162. const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-";
  163. if (ret > 0)
  164. DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d) %*ph\n",
  165. aux->name, offset, arrow, ret, min(ret, 20), buffer);
  166. else
  167. DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d)\n",
  168. aux->name, offset, arrow, ret);
  169. }
  170. /**
  171. * DOC: dp helpers
  172. *
  173. * The DisplayPort AUX channel is an abstraction to allow generic, driver-
  174. * independent access to AUX functionality. Drivers can take advantage of
  175. * this by filling in the fields of the drm_dp_aux structure.
  176. *
  177. * Transactions are described using a hardware-independent drm_dp_aux_msg
  178. * structure, which is passed into a driver's .transfer() implementation.
  179. * Both native and I2C-over-AUX transactions are supported.
  180. */
  181. static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,
  182. unsigned int offset, void *buffer, size_t size)
  183. {
  184. struct drm_dp_aux_msg msg;
  185. unsigned int retry, native_reply;
  186. int err = 0, ret = 0;
  187. memset(&msg, 0, sizeof(msg));
  188. msg.address = offset;
  189. msg.request = request;
  190. msg.buffer = buffer;
  191. msg.size = size;
  192. mutex_lock(&aux->hw_mutex);
  193. /*
  194. * The specification doesn't give any recommendation on how often to
  195. * retry native transactions. We used to retry 7 times like for
  196. * aux i2c transactions but real world devices this wasn't
  197. * sufficient, bump to 32 which makes Dell 4k monitors happier.
  198. */
  199. for (retry = 0; retry < 32; retry++) {
  200. if (ret != 0 && ret != -ETIMEDOUT) {
  201. usleep_range(AUX_RETRY_INTERVAL,
  202. AUX_RETRY_INTERVAL + 100);
  203. }
  204. ret = aux->transfer(aux, &msg);
  205. if (ret >= 0) {
  206. native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK;
  207. if (native_reply == DP_AUX_NATIVE_REPLY_ACK) {
  208. if (ret == size)
  209. goto unlock;
  210. ret = -EPROTO;
  211. } else
  212. ret = -EIO;
  213. }
  214. /*
  215. * We want the error we return to be the error we received on
  216. * the first transaction, since we may get a different error the
  217. * next time we retry
  218. */
  219. if (!err)
  220. err = ret;
  221. }
  222. DRM_DEBUG_KMS("%s: Too many retries, giving up. First error: %d\n",
  223. aux->name, err);
  224. ret = err;
  225. unlock:
  226. mutex_unlock(&aux->hw_mutex);
  227. return ret;
  228. }
  229. /**
  230. * drm_dp_dpcd_read() - read a series of bytes from the DPCD
  231. * @aux: DisplayPort AUX channel (SST or MST)
  232. * @offset: address of the (first) register to read
  233. * @buffer: buffer to store the register values
  234. * @size: number of bytes in @buffer
  235. *
  236. * Returns the number of bytes transferred on success, or a negative error
  237. * code on failure. -EIO is returned if the request was NAKed by the sink or
  238. * if the retry count was exceeded. If not all bytes were transferred, this
  239. * function returns -EPROTO. Errors from the underlying AUX channel transfer
  240. * function, with the exception of -EBUSY (which causes the transaction to
  241. * be retried), are propagated to the caller.
  242. */
  243. ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
  244. void *buffer, size_t size)
  245. {
  246. int ret;
  247. /*
  248. * HP ZR24w corrupts the first DPCD access after entering power save
  249. * mode. Eg. on a read, the entire buffer will be filled with the same
  250. * byte. Do a throw away read to avoid corrupting anything we care
  251. * about. Afterwards things will work correctly until the monitor
  252. * gets woken up and subsequently re-enters power save mode.
  253. *
  254. * The user pressing any button on the monitor is enough to wake it
  255. * up, so there is no particularly good place to do the workaround.
  256. * We just have to do it before any DPCD access and hope that the
  257. * monitor doesn't power down exactly after the throw away read.
  258. */
  259. if (!aux->is_remote) {
  260. ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV,
  261. buffer, 1);
  262. if (ret != 1)
  263. goto out;
  264. }
  265. if (aux->is_remote)
  266. ret = drm_dp_mst_dpcd_read(aux, offset, buffer, size);
  267. else
  268. ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset,
  269. buffer, size);
  270. out:
  271. drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret);
  272. return ret;
  273. }
  274. EXPORT_SYMBOL(drm_dp_dpcd_read);
  275. /**
  276. * drm_dp_dpcd_write() - write a series of bytes to the DPCD
  277. * @aux: DisplayPort AUX channel (SST or MST)
  278. * @offset: address of the (first) register to write
  279. * @buffer: buffer containing the values to write
  280. * @size: number of bytes in @buffer
  281. *
  282. * Returns the number of bytes transferred on success, or a negative error
  283. * code on failure. -EIO is returned if the request was NAKed by the sink or
  284. * if the retry count was exceeded. If not all bytes were transferred, this
  285. * function returns -EPROTO. Errors from the underlying AUX channel transfer
  286. * function, with the exception of -EBUSY (which causes the transaction to
  287. * be retried), are propagated to the caller.
  288. */
  289. ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
  290. void *buffer, size_t size)
  291. {
  292. int ret;
  293. if (aux->is_remote)
  294. ret = drm_dp_mst_dpcd_write(aux, offset, buffer, size);
  295. else
  296. ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset,
  297. buffer, size);
  298. drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret);
  299. return ret;
  300. }
  301. EXPORT_SYMBOL(drm_dp_dpcd_write);
  302. /**
  303. * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207)
  304. * @aux: DisplayPort AUX channel
  305. * @status: buffer to store the link status in (must be at least 6 bytes)
  306. *
  307. * Returns the number of bytes transferred on success or a negative error
  308. * code on failure.
  309. */
  310. int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
  311. u8 status[DP_LINK_STATUS_SIZE])
  312. {
  313. return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status,
  314. DP_LINK_STATUS_SIZE);
  315. }
  316. EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
  317. static bool is_edid_digital_input_dp(const struct edid *edid)
  318. {
  319. return edid && edid->revision >= 4 &&
  320. edid->input & DRM_EDID_INPUT_DIGITAL &&
  321. (edid->input & DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_DP;
  322. }
  323. /**
  324. * drm_dp_downstream_is_type() - is the downstream facing port of certain type?
  325. * @dpcd: DisplayPort configuration data
  326. * @port_cap: port capabilities
  327. * @type: port type to be checked. Can be:
  328. * %DP_DS_PORT_TYPE_DP, %DP_DS_PORT_TYPE_VGA, %DP_DS_PORT_TYPE_DVI,
  329. * %DP_DS_PORT_TYPE_HDMI, %DP_DS_PORT_TYPE_NON_EDID,
  330. * %DP_DS_PORT_TYPE_DP_DUALMODE or %DP_DS_PORT_TYPE_WIRELESS.
  331. *
  332. * Caveat: Only works with DPCD 1.1+ port caps.
  333. *
  334. * Returns: whether the downstream facing port matches the type.
  335. */
  336. bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  337. const u8 port_cap[4], u8 type)
  338. {
  339. return drm_dp_is_branch(dpcd) &&
  340. dpcd[DP_DPCD_REV] >= 0x11 &&
  341. (port_cap[0] & DP_DS_PORT_TYPE_MASK) == type;
  342. }
  343. EXPORT_SYMBOL(drm_dp_downstream_is_type);
  344. /**
  345. * drm_dp_downstream_is_tmds() - is the downstream facing port TMDS?
  346. * @dpcd: DisplayPort configuration data
  347. * @port_cap: port capabilities
  348. * @edid: EDID
  349. *
  350. * Returns: whether the downstream facing port is TMDS (HDMI/DVI).
  351. */
  352. bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  353. const u8 port_cap[4],
  354. const struct edid *edid)
  355. {
  356. if (dpcd[DP_DPCD_REV] < 0x11) {
  357. switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
  358. case DP_DWN_STRM_PORT_TYPE_TMDS:
  359. return true;
  360. default:
  361. return false;
  362. }
  363. }
  364. switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
  365. case DP_DS_PORT_TYPE_DP_DUALMODE:
  366. if (is_edid_digital_input_dp(edid))
  367. return false;
  368. fallthrough;
  369. case DP_DS_PORT_TYPE_DVI:
  370. case DP_DS_PORT_TYPE_HDMI:
  371. return true;
  372. default:
  373. return false;
  374. }
  375. }
  376. EXPORT_SYMBOL(drm_dp_downstream_is_tmds);
  377. /**
  378. * drm_dp_send_real_edid_checksum() - send back real edid checksum value
  379. * @aux: DisplayPort AUX channel
  380. * @real_edid_checksum: real edid checksum for the last block
  381. *
  382. * Returns:
  383. * True on success
  384. */
  385. bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
  386. u8 real_edid_checksum)
  387. {
  388. u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0;
  389. if (drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
  390. &auto_test_req, 1) < 1) {
  391. DRM_ERROR("%s: DPCD failed read at register 0x%x\n",
  392. aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
  393. return false;
  394. }
  395. auto_test_req &= DP_AUTOMATED_TEST_REQUEST;
  396. if (drm_dp_dpcd_read(aux, DP_TEST_REQUEST, &link_edid_read, 1) < 1) {
  397. DRM_ERROR("%s: DPCD failed read at register 0x%x\n",
  398. aux->name, DP_TEST_REQUEST);
  399. return false;
  400. }
  401. link_edid_read &= DP_TEST_LINK_EDID_READ;
  402. if (!auto_test_req || !link_edid_read) {
  403. DRM_DEBUG_KMS("%s: Source DUT does not support TEST_EDID_READ\n",
  404. aux->name);
  405. return false;
  406. }
  407. if (drm_dp_dpcd_write(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
  408. &auto_test_req, 1) < 1) {
  409. DRM_ERROR("%s: DPCD failed write at register 0x%x\n",
  410. aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
  411. return false;
  412. }
  413. /* send back checksum for the last edid extension block data */
  414. if (drm_dp_dpcd_write(aux, DP_TEST_EDID_CHECKSUM,
  415. &real_edid_checksum, 1) < 1) {
  416. DRM_ERROR("%s: DPCD failed write at register 0x%x\n",
  417. aux->name, DP_TEST_EDID_CHECKSUM);
  418. return false;
  419. }
  420. test_resp |= DP_TEST_EDID_CHECKSUM_WRITE;
  421. if (drm_dp_dpcd_write(aux, DP_TEST_RESPONSE, &test_resp, 1) < 1) {
  422. DRM_ERROR("%s: DPCD failed write at register 0x%x\n",
  423. aux->name, DP_TEST_RESPONSE);
  424. return false;
  425. }
  426. return true;
  427. }
  428. EXPORT_SYMBOL(drm_dp_send_real_edid_checksum);
  429. static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
  430. {
  431. u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK;
  432. if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE && port_count > 4)
  433. port_count = 4;
  434. return port_count;
  435. }
  436. static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux,
  437. u8 dpcd[DP_RECEIVER_CAP_SIZE])
  438. {
  439. u8 dpcd_ext[6];
  440. int ret;
  441. /*
  442. * Prior to DP1.3 the bit represented by
  443. * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
  444. * If it is set DP_DPCD_REV at 0000h could be at a value less than
  445. * the true capability of the panel. The only way to check is to
  446. * then compare 0000h and 2200h.
  447. */
  448. if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
  449. DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
  450. return 0;
  451. ret = drm_dp_dpcd_read(aux, DP_DP13_DPCD_REV, &dpcd_ext,
  452. sizeof(dpcd_ext));
  453. if (ret < 0)
  454. return ret;
  455. if (ret != sizeof(dpcd_ext))
  456. return -EIO;
  457. if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
  458. DRM_DEBUG_KMS("%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n",
  459. aux->name, dpcd[DP_DPCD_REV],
  460. dpcd_ext[DP_DPCD_REV]);
  461. return 0;
  462. }
  463. if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext)))
  464. return 0;
  465. DRM_DEBUG_KMS("%s: Base DPCD: %*ph\n",
  466. aux->name, DP_RECEIVER_CAP_SIZE, dpcd);
  467. memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext));
  468. return 0;
  469. }
  470. /**
  471. * drm_dp_read_dpcd_caps() - read DPCD caps and extended DPCD caps if
  472. * available
  473. * @aux: DisplayPort AUX channel
  474. * @dpcd: Buffer to store the resulting DPCD in
  475. *
  476. * Attempts to read the base DPCD caps for @aux. Additionally, this function
  477. * checks for and reads the extended DPRX caps (%DP_DP13_DPCD_REV) if
  478. * present.
  479. *
  480. * Returns: %0 if the DPCD was read successfully, negative error code
  481. * otherwise.
  482. */
  483. int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
  484. u8 dpcd[DP_RECEIVER_CAP_SIZE])
  485. {
  486. int ret;
  487. ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE);
  488. if (ret < 0)
  489. return ret;
  490. if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0)
  491. return -EIO;
  492. ret = drm_dp_read_extended_dpcd_caps(aux, dpcd);
  493. if (ret < 0)
  494. return ret;
  495. DRM_DEBUG_KMS("%s: DPCD: %*ph\n",
  496. aux->name, DP_RECEIVER_CAP_SIZE, dpcd);
  497. return ret;
  498. }
  499. EXPORT_SYMBOL(drm_dp_read_dpcd_caps);
  500. /**
  501. * drm_dp_read_downstream_info() - read DPCD downstream port info if available
  502. * @aux: DisplayPort AUX channel
  503. * @dpcd: A cached copy of the port's DPCD
  504. * @downstream_ports: buffer to store the downstream port info in
  505. *
  506. * See also:
  507. * drm_dp_downstream_max_clock()
  508. * drm_dp_downstream_max_bpc()
  509. *
  510. * Returns: 0 if either the downstream port info was read successfully or
  511. * there was no downstream info to read, or a negative error code otherwise.
  512. */
  513. int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
  514. const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  515. u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS])
  516. {
  517. int ret;
  518. u8 len;
  519. memset(downstream_ports, 0, DP_MAX_DOWNSTREAM_PORTS);
  520. /* No downstream info to read */
  521. if (!drm_dp_is_branch(dpcd) ||
  522. dpcd[DP_DPCD_REV] < DP_DPCD_REV_10 ||
  523. !(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
  524. return 0;
  525. /* Some branches advertise having 0 downstream ports, despite also advertising they have a
  526. * downstream port present. The DP spec isn't clear on if this is allowed or not, but since
  527. * some branches do it we need to handle it regardless.
  528. */
  529. len = drm_dp_downstream_port_count(dpcd);
  530. if (!len)
  531. return 0;
  532. if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE)
  533. len *= 4;
  534. ret = drm_dp_dpcd_read(aux, DP_DOWNSTREAM_PORT_0, downstream_ports, len);
  535. if (ret < 0)
  536. return ret;
  537. if (ret != len)
  538. return -EIO;
  539. DRM_DEBUG_KMS("%s: DPCD DFP: %*ph\n",
  540. aux->name, len, downstream_ports);
  541. return 0;
  542. }
  543. EXPORT_SYMBOL(drm_dp_read_downstream_info);
  544. /**
  545. * drm_dp_downstream_max_dotclock() - extract downstream facing port max dot clock
  546. * @dpcd: DisplayPort configuration data
  547. * @port_cap: port capabilities
  548. *
  549. * Returns: Downstream facing port max dot clock in kHz on success,
  550. * or 0 if max clock not defined
  551. */
  552. int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  553. const u8 port_cap[4])
  554. {
  555. if (!drm_dp_is_branch(dpcd))
  556. return 0;
  557. if (dpcd[DP_DPCD_REV] < 0x11)
  558. return 0;
  559. switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
  560. case DP_DS_PORT_TYPE_VGA:
  561. if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
  562. return 0;
  563. return port_cap[1] * 8000;
  564. default:
  565. return 0;
  566. }
  567. }
  568. EXPORT_SYMBOL(drm_dp_downstream_max_dotclock);
  569. /**
  570. * drm_dp_downstream_max_tmds_clock() - extract downstream facing port max TMDS clock
  571. * @dpcd: DisplayPort configuration data
  572. * @port_cap: port capabilities
  573. * @edid: EDID
  574. *
  575. * Returns: HDMI/DVI downstream facing port max TMDS clock in kHz on success,
  576. * or 0 if max TMDS clock not defined
  577. */
  578. int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  579. const u8 port_cap[4],
  580. const struct edid *edid)
  581. {
  582. if (!drm_dp_is_branch(dpcd))
  583. return 0;
  584. if (dpcd[DP_DPCD_REV] < 0x11) {
  585. switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
  586. case DP_DWN_STRM_PORT_TYPE_TMDS:
  587. return 165000;
  588. default:
  589. return 0;
  590. }
  591. }
  592. switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
  593. case DP_DS_PORT_TYPE_DP_DUALMODE:
  594. if (is_edid_digital_input_dp(edid))
  595. return 0;
  596. /*
  597. * It's left up to the driver to check the
  598. * DP dual mode adapter's max TMDS clock.
  599. *
  600. * Unfortunatley it looks like branch devices
  601. * may not fordward that the DP dual mode i2c
  602. * access so we just usually get i2c nak :(
  603. */
  604. fallthrough;
  605. case DP_DS_PORT_TYPE_HDMI:
  606. /*
  607. * We should perhaps assume 165 MHz when detailed cap
  608. * info is not available. But looks like many typical
  609. * branch devices fall into that category and so we'd
  610. * probably end up with users complaining that they can't
  611. * get high resolution modes with their favorite dongle.
  612. *
  613. * So let's limit to 300 MHz instead since DPCD 1.4
  614. * HDMI 2.0 DFPs are required to have the detailed cap
  615. * info. So it's more likely we're dealing with a HDMI 1.4
  616. * compatible* device here.
  617. */
  618. if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
  619. return 300000;
  620. return port_cap[1] * 2500;
  621. case DP_DS_PORT_TYPE_DVI:
  622. if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
  623. return 165000;
  624. /* FIXME what to do about DVI dual link? */
  625. return port_cap[1] * 2500;
  626. default:
  627. return 0;
  628. }
  629. }
  630. EXPORT_SYMBOL(drm_dp_downstream_max_tmds_clock);
  631. /**
  632. * drm_dp_downstream_min_tmds_clock() - extract downstream facing port min TMDS clock
  633. * @dpcd: DisplayPort configuration data
  634. * @port_cap: port capabilities
  635. * @edid: EDID
  636. *
  637. * Returns: HDMI/DVI downstream facing port min TMDS clock in kHz on success,
  638. * or 0 if max TMDS clock not defined
  639. */
  640. int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  641. const u8 port_cap[4],
  642. const struct edid *edid)
  643. {
  644. if (!drm_dp_is_branch(dpcd))
  645. return 0;
  646. if (dpcd[DP_DPCD_REV] < 0x11) {
  647. switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
  648. case DP_DWN_STRM_PORT_TYPE_TMDS:
  649. return 25000;
  650. default:
  651. return 0;
  652. }
  653. }
  654. switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
  655. case DP_DS_PORT_TYPE_DP_DUALMODE:
  656. if (is_edid_digital_input_dp(edid))
  657. return 0;
  658. fallthrough;
  659. case DP_DS_PORT_TYPE_DVI:
  660. case DP_DS_PORT_TYPE_HDMI:
  661. /*
  662. * Unclear whether the protocol converter could
  663. * utilize pixel replication. Assume it won't.
  664. */
  665. return 25000;
  666. default:
  667. return 0;
  668. }
  669. }
  670. EXPORT_SYMBOL(drm_dp_downstream_min_tmds_clock);
  671. /**
  672. * drm_dp_downstream_max_bpc() - extract downstream facing port max
  673. * bits per component
  674. * @dpcd: DisplayPort configuration data
  675. * @port_cap: downstream facing port capabilities
  676. * @edid: EDID
  677. *
  678. * Returns: Max bpc on success or 0 if max bpc not defined
  679. */
  680. int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  681. const u8 port_cap[4],
  682. const struct edid *edid)
  683. {
  684. if (!drm_dp_is_branch(dpcd))
  685. return 0;
  686. if (dpcd[DP_DPCD_REV] < 0x11) {
  687. switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
  688. case DP_DWN_STRM_PORT_TYPE_DP:
  689. return 0;
  690. default:
  691. return 8;
  692. }
  693. }
  694. switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
  695. case DP_DS_PORT_TYPE_DP:
  696. return 0;
  697. case DP_DS_PORT_TYPE_DP_DUALMODE:
  698. if (is_edid_digital_input_dp(edid))
  699. return 0;
  700. fallthrough;
  701. case DP_DS_PORT_TYPE_HDMI:
  702. case DP_DS_PORT_TYPE_DVI:
  703. case DP_DS_PORT_TYPE_VGA:
  704. if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
  705. return 8;
  706. switch (port_cap[2] & DP_DS_MAX_BPC_MASK) {
  707. case DP_DS_8BPC:
  708. return 8;
  709. case DP_DS_10BPC:
  710. return 10;
  711. case DP_DS_12BPC:
  712. return 12;
  713. case DP_DS_16BPC:
  714. return 16;
  715. default:
  716. return 8;
  717. }
  718. break;
  719. default:
  720. return 8;
  721. }
  722. }
  723. EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
  724. /**
  725. * drm_dp_downstream_420_passthrough() - determine downstream facing port
  726. * YCbCr 4:2:0 pass-through capability
  727. * @dpcd: DisplayPort configuration data
  728. * @port_cap: downstream facing port capabilities
  729. *
  730. * Returns: whether the downstream facing port can pass through YCbCr 4:2:0
  731. */
  732. bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  733. const u8 port_cap[4])
  734. {
  735. if (!drm_dp_is_branch(dpcd))
  736. return false;
  737. if (dpcd[DP_DPCD_REV] < 0x13)
  738. return false;
  739. switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
  740. case DP_DS_PORT_TYPE_DP:
  741. return true;
  742. case DP_DS_PORT_TYPE_HDMI:
  743. if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
  744. return false;
  745. return port_cap[3] & DP_DS_HDMI_YCBCR420_PASS_THROUGH;
  746. default:
  747. return false;
  748. }
  749. }
  750. EXPORT_SYMBOL(drm_dp_downstream_420_passthrough);
  751. /**
  752. * drm_dp_downstream_444_to_420_conversion() - determine downstream facing port
  753. * YCbCr 4:4:4->4:2:0 conversion capability
  754. * @dpcd: DisplayPort configuration data
  755. * @port_cap: downstream facing port capabilities
  756. *
  757. * Returns: whether the downstream facing port can convert YCbCr 4:4:4 to 4:2:0
  758. */
  759. bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  760. const u8 port_cap[4])
  761. {
  762. if (!drm_dp_is_branch(dpcd))
  763. return false;
  764. if (dpcd[DP_DPCD_REV] < 0x13)
  765. return false;
  766. switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
  767. case DP_DS_PORT_TYPE_HDMI:
  768. if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
  769. return false;
  770. return port_cap[3] & DP_DS_HDMI_YCBCR444_TO_420_CONV;
  771. default:
  772. return false;
  773. }
  774. }
  775. EXPORT_SYMBOL(drm_dp_downstream_444_to_420_conversion);
  776. /**
  777. * drm_dp_downstream_mode() - return a mode for downstream facing port
  778. * @dev: DRM device
  779. * @dpcd: DisplayPort configuration data
  780. * @port_cap: port capabilities
  781. *
  782. * Provides a suitable mode for downstream facing ports without EDID.
  783. *
  784. * Returns: A new drm_display_mode on success or NULL on failure
  785. */
  786. struct drm_display_mode *
  787. drm_dp_downstream_mode(struct drm_device *dev,
  788. const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  789. const u8 port_cap[4])
  790. {
  791. u8 vic;
  792. if (!drm_dp_is_branch(dpcd))
  793. return NULL;
  794. if (dpcd[DP_DPCD_REV] < 0x11)
  795. return NULL;
  796. switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
  797. case DP_DS_PORT_TYPE_NON_EDID:
  798. switch (port_cap[0] & DP_DS_NON_EDID_MASK) {
  799. case DP_DS_NON_EDID_720x480i_60:
  800. vic = 6;
  801. break;
  802. case DP_DS_NON_EDID_720x480i_50:
  803. vic = 21;
  804. break;
  805. case DP_DS_NON_EDID_1920x1080i_60:
  806. vic = 5;
  807. break;
  808. case DP_DS_NON_EDID_1920x1080i_50:
  809. vic = 20;
  810. break;
  811. case DP_DS_NON_EDID_1280x720_60:
  812. vic = 4;
  813. break;
  814. case DP_DS_NON_EDID_1280x720_50:
  815. vic = 19;
  816. break;
  817. default:
  818. return NULL;
  819. }
  820. return drm_display_mode_from_cea_vic(dev, vic);
  821. default:
  822. return NULL;
  823. }
  824. }
  825. EXPORT_SYMBOL(drm_dp_downstream_mode);
  826. /**
  827. * drm_dp_downstream_id() - identify branch device
  828. * @aux: DisplayPort AUX channel
  829. * @id: DisplayPort branch device id
  830. *
  831. * Returns branch device id on success or NULL on failure
  832. */
  833. int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6])
  834. {
  835. return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6);
  836. }
  837. EXPORT_SYMBOL(drm_dp_downstream_id);
  838. /**
  839. * drm_dp_downstream_debug() - debug DP branch devices
  840. * @m: pointer for debugfs file
  841. * @dpcd: DisplayPort configuration data
  842. * @port_cap: port capabilities
  843. * @edid: EDID
  844. * @aux: DisplayPort AUX channel
  845. *
  846. */
  847. void drm_dp_downstream_debug(struct seq_file *m,
  848. const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  849. const u8 port_cap[4],
  850. const struct edid *edid,
  851. struct drm_dp_aux *aux)
  852. {
  853. bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
  854. DP_DETAILED_CAP_INFO_AVAILABLE;
  855. int clk;
  856. int bpc;
  857. char id[7];
  858. int len;
  859. uint8_t rev[2];
  860. int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
  861. bool branch_device = drm_dp_is_branch(dpcd);
  862. seq_printf(m, "\tDP branch device present: %s\n",
  863. branch_device ? "yes" : "no");
  864. if (!branch_device)
  865. return;
  866. switch (type) {
  867. case DP_DS_PORT_TYPE_DP:
  868. seq_puts(m, "\t\tType: DisplayPort\n");
  869. break;
  870. case DP_DS_PORT_TYPE_VGA:
  871. seq_puts(m, "\t\tType: VGA\n");
  872. break;
  873. case DP_DS_PORT_TYPE_DVI:
  874. seq_puts(m, "\t\tType: DVI\n");
  875. break;
  876. case DP_DS_PORT_TYPE_HDMI:
  877. seq_puts(m, "\t\tType: HDMI\n");
  878. break;
  879. case DP_DS_PORT_TYPE_NON_EDID:
  880. seq_puts(m, "\t\tType: others without EDID support\n");
  881. break;
  882. case DP_DS_PORT_TYPE_DP_DUALMODE:
  883. seq_puts(m, "\t\tType: DP++\n");
  884. break;
  885. case DP_DS_PORT_TYPE_WIRELESS:
  886. seq_puts(m, "\t\tType: Wireless\n");
  887. break;
  888. default:
  889. seq_puts(m, "\t\tType: N/A\n");
  890. }
  891. memset(id, 0, sizeof(id));
  892. drm_dp_downstream_id(aux, id);
  893. seq_printf(m, "\t\tID: %s\n", id);
  894. len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1);
  895. if (len > 0)
  896. seq_printf(m, "\t\tHW: %d.%d\n",
  897. (rev[0] & 0xf0) >> 4, rev[0] & 0xf);
  898. len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, rev, 2);
  899. if (len > 0)
  900. seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]);
  901. if (detailed_cap_info) {
  902. clk = drm_dp_downstream_max_dotclock(dpcd, port_cap);
  903. if (clk > 0)
  904. seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk);
  905. clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, edid);
  906. if (clk > 0)
  907. seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk);
  908. clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, edid);
  909. if (clk > 0)
  910. seq_printf(m, "\t\tMin TMDS clock: %d kHz\n", clk);
  911. bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, edid);
  912. if (bpc > 0)
  913. seq_printf(m, "\t\tMax bpc: %d\n", bpc);
  914. }
  915. }
  916. EXPORT_SYMBOL(drm_dp_downstream_debug);
  917. /**
  918. * drm_dp_subconnector_type() - get DP branch device type
  919. * @dpcd: DisplayPort configuration data
  920. * @port_cap: port capabilities
  921. */
  922. enum drm_mode_subconnector
  923. drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  924. const u8 port_cap[4])
  925. {
  926. int type;
  927. if (!drm_dp_is_branch(dpcd))
  928. return DRM_MODE_SUBCONNECTOR_Native;
  929. /* DP 1.0 approach */
  930. if (dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) {
  931. type = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
  932. DP_DWN_STRM_PORT_TYPE_MASK;
  933. switch (type) {
  934. case DP_DWN_STRM_PORT_TYPE_TMDS:
  935. /* Can be HDMI or DVI-D, DVI-D is a safer option */
  936. return DRM_MODE_SUBCONNECTOR_DVID;
  937. case DP_DWN_STRM_PORT_TYPE_ANALOG:
  938. /* Can be VGA or DVI-A, VGA is more popular */
  939. return DRM_MODE_SUBCONNECTOR_VGA;
  940. case DP_DWN_STRM_PORT_TYPE_DP:
  941. return DRM_MODE_SUBCONNECTOR_DisplayPort;
  942. case DP_DWN_STRM_PORT_TYPE_OTHER:
  943. default:
  944. return DRM_MODE_SUBCONNECTOR_Unknown;
  945. }
  946. }
  947. type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
  948. switch (type) {
  949. case DP_DS_PORT_TYPE_DP:
  950. case DP_DS_PORT_TYPE_DP_DUALMODE:
  951. return DRM_MODE_SUBCONNECTOR_DisplayPort;
  952. case DP_DS_PORT_TYPE_VGA:
  953. return DRM_MODE_SUBCONNECTOR_VGA;
  954. case DP_DS_PORT_TYPE_DVI:
  955. return DRM_MODE_SUBCONNECTOR_DVID;
  956. case DP_DS_PORT_TYPE_HDMI:
  957. return DRM_MODE_SUBCONNECTOR_HDMIA;
  958. case DP_DS_PORT_TYPE_WIRELESS:
  959. return DRM_MODE_SUBCONNECTOR_Wireless;
  960. case DP_DS_PORT_TYPE_NON_EDID:
  961. default:
  962. return DRM_MODE_SUBCONNECTOR_Unknown;
  963. }
  964. }
  965. EXPORT_SYMBOL(drm_dp_subconnector_type);
  966. /**
  967. * drm_mode_set_dp_subconnector_property - set subconnector for DP connector
  968. * @connector: connector to set property on
  969. * @status: connector status
  970. * @dpcd: DisplayPort configuration data
  971. * @port_cap: port capabilities
  972. *
  973. * Called by a driver on every detect event.
  974. */
  975. void drm_dp_set_subconnector_property(struct drm_connector *connector,
  976. enum drm_connector_status status,
  977. const u8 *dpcd,
  978. const u8 port_cap[4])
  979. {
  980. enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
  981. if (status == connector_status_connected)
  982. subconnector = drm_dp_subconnector_type(dpcd, port_cap);
  983. drm_object_property_set_value(&connector->base,
  984. connector->dev->mode_config.dp_subconnector_property,
  985. subconnector);
  986. }
  987. EXPORT_SYMBOL(drm_dp_set_subconnector_property);
  988. /**
  989. * drm_dp_read_sink_count_cap() - Check whether a given connector has a valid sink
  990. * count
  991. * @connector: The DRM connector to check
  992. * @dpcd: A cached copy of the connector's DPCD RX capabilities
  993. * @desc: A cached copy of the connector's DP descriptor
  994. *
  995. * See also: drm_dp_read_sink_count()
  996. *
  997. * Returns: %True if the (e)DP connector has a valid sink count that should
  998. * be probed, %false otherwise.
  999. */
  1000. bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
  1001. const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  1002. const struct drm_dp_desc *desc)
  1003. {
  1004. /* Some eDP panels don't set a valid value for the sink count */
  1005. return connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
  1006. dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 &&
  1007. dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
  1008. !drm_dp_has_quirk(desc, 0, DP_DPCD_QUIRK_NO_SINK_COUNT);
  1009. }
  1010. EXPORT_SYMBOL(drm_dp_read_sink_count_cap);
  1011. /**
  1012. * drm_dp_read_sink_count() - Retrieve the sink count for a given sink
  1013. * @aux: The DP AUX channel to use
  1014. *
  1015. * See also: drm_dp_read_sink_count_cap()
  1016. *
  1017. * Returns: The current sink count reported by @aux, or a negative error code
  1018. * otherwise.
  1019. */
  1020. int drm_dp_read_sink_count(struct drm_dp_aux *aux)
  1021. {
  1022. u8 count;
  1023. int ret;
  1024. ret = drm_dp_dpcd_readb(aux, DP_SINK_COUNT, &count);
  1025. if (ret < 0)
  1026. return ret;
  1027. if (ret != 1)
  1028. return -EIO;
  1029. return DP_GET_SINK_COUNT(count);
  1030. }
  1031. EXPORT_SYMBOL(drm_dp_read_sink_count);
  1032. /*
  1033. * I2C-over-AUX implementation
  1034. */
  1035. static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter)
  1036. {
  1037. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
  1038. I2C_FUNC_SMBUS_READ_BLOCK_DATA |
  1039. I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
  1040. I2C_FUNC_10BIT_ADDR;
  1041. }
  1042. static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg)
  1043. {
  1044. /*
  1045. * In case of i2c defer or short i2c ack reply to a write,
  1046. * we need to switch to WRITE_STATUS_UPDATE to drain the
  1047. * rest of the message
  1048. */
  1049. if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) {
  1050. msg->request &= DP_AUX_I2C_MOT;
  1051. msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE;
  1052. }
  1053. }
  1054. #define AUX_PRECHARGE_LEN 10 /* 10 to 16 */
  1055. #define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */
  1056. #define AUX_STOP_LEN 4
  1057. #define AUX_CMD_LEN 4
  1058. #define AUX_ADDRESS_LEN 20
  1059. #define AUX_REPLY_PAD_LEN 4
  1060. #define AUX_LENGTH_LEN 8
  1061. /*
  1062. * Calculate the duration of the AUX request/reply in usec. Gives the
  1063. * "best" case estimate, ie. successful while as short as possible.
  1064. */
  1065. static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg)
  1066. {
  1067. int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
  1068. AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN;
  1069. if ((msg->request & DP_AUX_I2C_READ) == 0)
  1070. len += msg->size * 8;
  1071. return len;
  1072. }
  1073. static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg)
  1074. {
  1075. int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
  1076. AUX_CMD_LEN + AUX_REPLY_PAD_LEN;
  1077. /*
  1078. * For read we expect what was asked. For writes there will
  1079. * be 0 or 1 data bytes. Assume 0 for the "best" case.
  1080. */
  1081. if (msg->request & DP_AUX_I2C_READ)
  1082. len += msg->size * 8;
  1083. return len;
  1084. }
  1085. #define I2C_START_LEN 1
  1086. #define I2C_STOP_LEN 1
  1087. #define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */
  1088. #define I2C_DATA_LEN 9 /* DATA + ACK/NACK */
  1089. /*
  1090. * Calculate the length of the i2c transfer in usec, assuming
  1091. * the i2c bus speed is as specified. Gives the the "worst"
  1092. * case estimate, ie. successful while as long as possible.
  1093. * Doesn't account the the "MOT" bit, and instead assumes each
  1094. * message includes a START, ADDRESS and STOP. Neither does it
  1095. * account for additional random variables such as clock stretching.
  1096. */
  1097. static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg,
  1098. int i2c_speed_khz)
  1099. {
  1100. /* AUX bitrate is 1MHz, i2c bitrate as specified */
  1101. return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN +
  1102. msg->size * I2C_DATA_LEN +
  1103. I2C_STOP_LEN) * 1000, i2c_speed_khz);
  1104. }
  1105. /*
  1106. * Deterine how many retries should be attempted to successfully transfer
  1107. * the specified message, based on the estimated durations of the
  1108. * i2c and AUX transfers.
  1109. */
  1110. static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg,
  1111. int i2c_speed_khz)
  1112. {
  1113. int aux_time_us = drm_dp_aux_req_duration(msg) +
  1114. drm_dp_aux_reply_duration(msg);
  1115. int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz);
  1116. return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL);
  1117. }
  1118. /*
  1119. * FIXME currently assumes 10 kHz as some real world devices seem
  1120. * to require it. We should query/set the speed via DPCD if supported.
  1121. */
  1122. static int dp_aux_i2c_speed_khz __read_mostly = 10;
  1123. module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644);
  1124. MODULE_PARM_DESC(dp_aux_i2c_speed_khz,
  1125. "Assumed speed of the i2c bus in kHz, (1-400, default 10)");
  1126. /*
  1127. * Transfer a single I2C-over-AUX message and handle various error conditions,
  1128. * retrying the transaction as appropriate. It is assumed that the
  1129. * &drm_dp_aux.transfer function does not modify anything in the msg other than the
  1130. * reply field.
  1131. *
  1132. * Returns bytes transferred on success, or a negative error code on failure.
  1133. */
  1134. static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
  1135. {
  1136. unsigned int retry, defer_i2c;
  1137. int ret;
  1138. /*
  1139. * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device
  1140. * is required to retry at least seven times upon receiving AUX_DEFER
  1141. * before giving up the AUX transaction.
  1142. *
  1143. * We also try to account for the i2c bus speed.
  1144. */
  1145. int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz));
  1146. for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) {
  1147. ret = aux->transfer(aux, msg);
  1148. if (ret < 0) {
  1149. if (ret == -EBUSY)
  1150. continue;
  1151. /*
  1152. * While timeouts can be errors, they're usually normal
  1153. * behavior (for instance, when a driver tries to
  1154. * communicate with a non-existant DisplayPort device).
  1155. * Avoid spamming the kernel log with timeout errors.
  1156. */
  1157. if (ret == -ETIMEDOUT)
  1158. DRM_DEBUG_KMS_RATELIMITED("%s: transaction timed out\n",
  1159. aux->name);
  1160. else
  1161. DRM_DEBUG_KMS("%s: transaction failed: %d\n",
  1162. aux->name, ret);
  1163. return ret;
  1164. }
  1165. switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) {
  1166. case DP_AUX_NATIVE_REPLY_ACK:
  1167. /*
  1168. * For I2C-over-AUX transactions this isn't enough, we
  1169. * need to check for the I2C ACK reply.
  1170. */
  1171. break;
  1172. case DP_AUX_NATIVE_REPLY_NACK:
  1173. DRM_DEBUG_KMS("%s: native nack (result=%d, size=%zu)\n",
  1174. aux->name, ret, msg->size);
  1175. return -EREMOTEIO;
  1176. case DP_AUX_NATIVE_REPLY_DEFER:
  1177. DRM_DEBUG_KMS("%s: native defer\n", aux->name);
  1178. /*
  1179. * We could check for I2C bit rate capabilities and if
  1180. * available adjust this interval. We could also be
  1181. * more careful with DP-to-legacy adapters where a
  1182. * long legacy cable may force very low I2C bit rates.
  1183. *
  1184. * For now just defer for long enough to hopefully be
  1185. * safe for all use-cases.
  1186. */
  1187. usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
  1188. continue;
  1189. default:
  1190. DRM_ERROR("%s: invalid native reply %#04x\n",
  1191. aux->name, msg->reply);
  1192. return -EREMOTEIO;
  1193. }
  1194. switch (msg->reply & DP_AUX_I2C_REPLY_MASK) {
  1195. case DP_AUX_I2C_REPLY_ACK:
  1196. /*
  1197. * Both native ACK and I2C ACK replies received. We
  1198. * can assume the transfer was successful.
  1199. */
  1200. if (ret != msg->size)
  1201. drm_dp_i2c_msg_write_status_update(msg);
  1202. return ret;
  1203. case DP_AUX_I2C_REPLY_NACK:
  1204. DRM_DEBUG_KMS("%s: I2C nack (result=%d, size=%zu)\n",
  1205. aux->name, ret, msg->size);
  1206. aux->i2c_nack_count++;
  1207. return -EREMOTEIO;
  1208. case DP_AUX_I2C_REPLY_DEFER:
  1209. DRM_DEBUG_KMS("%s: I2C defer\n", aux->name);
  1210. /* DP Compliance Test 4.2.2.5 Requirement:
  1211. * Must have at least 7 retries for I2C defers on the
  1212. * transaction to pass this test
  1213. */
  1214. aux->i2c_defer_count++;
  1215. if (defer_i2c < 7)
  1216. defer_i2c++;
  1217. usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
  1218. drm_dp_i2c_msg_write_status_update(msg);
  1219. continue;
  1220. default:
  1221. DRM_ERROR("%s: invalid I2C reply %#04x\n",
  1222. aux->name, msg->reply);
  1223. return -EREMOTEIO;
  1224. }
  1225. }
  1226. DRM_DEBUG_KMS("%s: Too many retries, giving up\n", aux->name);
  1227. return -EREMOTEIO;
  1228. }
  1229. static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg,
  1230. const struct i2c_msg *i2c_msg)
  1231. {
  1232. msg->request = (i2c_msg->flags & I2C_M_RD) ?
  1233. DP_AUX_I2C_READ : DP_AUX_I2C_WRITE;
  1234. if (!(i2c_msg->flags & I2C_M_STOP))
  1235. msg->request |= DP_AUX_I2C_MOT;
  1236. }
  1237. /*
  1238. * Keep retrying drm_dp_i2c_do_msg until all data has been transferred.
  1239. *
  1240. * Returns an error code on failure, or a recommended transfer size on success.
  1241. */
  1242. static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg)
  1243. {
  1244. int err, ret = orig_msg->size;
  1245. struct drm_dp_aux_msg msg = *orig_msg;
  1246. while (msg.size > 0) {
  1247. err = drm_dp_i2c_do_msg(aux, &msg);
  1248. if (err <= 0)
  1249. return err == 0 ? -EPROTO : err;
  1250. if (err < msg.size && err < ret) {
  1251. DRM_DEBUG_KMS("%s: Partial I2C reply: requested %zu bytes got %d bytes\n",
  1252. aux->name, msg.size, err);
  1253. ret = err;
  1254. }
  1255. msg.size -= err;
  1256. msg.buffer += err;
  1257. }
  1258. return ret;
  1259. }
  1260. /*
  1261. * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX
  1262. * packets to be as large as possible. If not, the I2C transactions never
  1263. * succeed. Hence the default is maximum.
  1264. */
  1265. static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES;
  1266. module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644);
  1267. MODULE_PARM_DESC(dp_aux_i2c_transfer_size,
  1268. "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)");
  1269. static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
  1270. int num)
  1271. {
  1272. struct drm_dp_aux *aux = adapter->algo_data;
  1273. unsigned int i, j;
  1274. unsigned transfer_size;
  1275. struct drm_dp_aux_msg msg;
  1276. int err = 0;
  1277. dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES);
  1278. memset(&msg, 0, sizeof(msg));
  1279. for (i = 0; i < num; i++) {
  1280. msg.address = msgs[i].addr;
  1281. drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
  1282. /* Send a bare address packet to start the transaction.
  1283. * Zero sized messages specify an address only (bare
  1284. * address) transaction.
  1285. */
  1286. msg.buffer = NULL;
  1287. msg.size = 0;
  1288. err = drm_dp_i2c_do_msg(aux, &msg);
  1289. /*
  1290. * Reset msg.request in case in case it got
  1291. * changed into a WRITE_STATUS_UPDATE.
  1292. */
  1293. drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
  1294. if (err < 0)
  1295. break;
  1296. /* We want each transaction to be as large as possible, but
  1297. * we'll go to smaller sizes if the hardware gives us a
  1298. * short reply.
  1299. */
  1300. transfer_size = dp_aux_i2c_transfer_size;
  1301. for (j = 0; j < msgs[i].len; j += msg.size) {
  1302. msg.buffer = msgs[i].buf + j;
  1303. msg.size = min(transfer_size, msgs[i].len - j);
  1304. err = drm_dp_i2c_drain_msg(aux, &msg);
  1305. /*
  1306. * Reset msg.request in case in case it got
  1307. * changed into a WRITE_STATUS_UPDATE.
  1308. */
  1309. drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
  1310. if (err < 0)
  1311. break;
  1312. transfer_size = err;
  1313. }
  1314. if (err < 0)
  1315. break;
  1316. }
  1317. if (err >= 0)
  1318. err = num;
  1319. /* Send a bare address packet to close out the transaction.
  1320. * Zero sized messages specify an address only (bare
  1321. * address) transaction.
  1322. */
  1323. msg.request &= ~DP_AUX_I2C_MOT;
  1324. msg.buffer = NULL;
  1325. msg.size = 0;
  1326. (void)drm_dp_i2c_do_msg(aux, &msg);
  1327. return err;
  1328. }
  1329. static const struct i2c_algorithm drm_dp_i2c_algo = {
  1330. .functionality = drm_dp_i2c_functionality,
  1331. .master_xfer = drm_dp_i2c_xfer,
  1332. };
  1333. static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c)
  1334. {
  1335. return container_of(i2c, struct drm_dp_aux, ddc);
  1336. }
  1337. static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
  1338. {
  1339. mutex_lock(&i2c_to_aux(i2c)->hw_mutex);
  1340. }
  1341. static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags)
  1342. {
  1343. return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex);
  1344. }
  1345. static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
  1346. {
  1347. mutex_unlock(&i2c_to_aux(i2c)->hw_mutex);
  1348. }
  1349. static const struct i2c_lock_operations drm_dp_i2c_lock_ops = {
  1350. .lock_bus = lock_bus,
  1351. .trylock_bus = trylock_bus,
  1352. .unlock_bus = unlock_bus,
  1353. };
  1354. static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc)
  1355. {
  1356. u8 buf, count;
  1357. int ret;
  1358. ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
  1359. if (ret < 0)
  1360. return ret;
  1361. WARN_ON(!(buf & DP_TEST_SINK_START));
  1362. ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC, &buf);
  1363. if (ret < 0)
  1364. return ret;
  1365. count = buf & DP_TEST_COUNT_MASK;
  1366. if (count == aux->crc_count)
  1367. return -EAGAIN; /* No CRC yet */
  1368. aux->crc_count = count;
  1369. /*
  1370. * At DP_TEST_CRC_R_CR, there's 6 bytes containing CRC data, 2 bytes
  1371. * per component (RGB or CrYCb).
  1372. */
  1373. ret = drm_dp_dpcd_read(aux, DP_TEST_CRC_R_CR, crc, 6);
  1374. if (ret < 0)
  1375. return ret;
  1376. return 0;
  1377. }
  1378. static void drm_dp_aux_crc_work(struct work_struct *work)
  1379. {
  1380. struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux,
  1381. crc_work);
  1382. struct drm_crtc *crtc;
  1383. u8 crc_bytes[6];
  1384. uint32_t crcs[3];
  1385. int ret;
  1386. if (WARN_ON(!aux->crtc))
  1387. return;
  1388. crtc = aux->crtc;
  1389. while (crtc->crc.opened) {
  1390. drm_crtc_wait_one_vblank(crtc);
  1391. if (!crtc->crc.opened)
  1392. break;
  1393. ret = drm_dp_aux_get_crc(aux, crc_bytes);
  1394. if (ret == -EAGAIN) {
  1395. usleep_range(1000, 2000);
  1396. ret = drm_dp_aux_get_crc(aux, crc_bytes);
  1397. }
  1398. if (ret == -EAGAIN) {
  1399. DRM_DEBUG_KMS("%s: Get CRC failed after retrying: %d\n",
  1400. aux->name, ret);
  1401. continue;
  1402. } else if (ret) {
  1403. DRM_DEBUG_KMS("%s: Failed to get a CRC: %d\n",
  1404. aux->name, ret);
  1405. continue;
  1406. }
  1407. crcs[0] = crc_bytes[0] | crc_bytes[1] << 8;
  1408. crcs[1] = crc_bytes[2] | crc_bytes[3] << 8;
  1409. crcs[2] = crc_bytes[4] | crc_bytes[5] << 8;
  1410. drm_crtc_add_crc_entry(crtc, false, 0, crcs);
  1411. }
  1412. }
  1413. /**
  1414. * drm_dp_remote_aux_init() - minimally initialise a remote aux channel
  1415. * @aux: DisplayPort AUX channel
  1416. *
  1417. * Used for remote aux channel in general. Merely initialize the crc work
  1418. * struct.
  1419. */
  1420. void drm_dp_remote_aux_init(struct drm_dp_aux *aux)
  1421. {
  1422. INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
  1423. }
  1424. EXPORT_SYMBOL(drm_dp_remote_aux_init);
  1425. /**
  1426. * drm_dp_aux_init() - minimally initialise an aux channel
  1427. * @aux: DisplayPort AUX channel
  1428. *
  1429. * If you need to use the drm_dp_aux's i2c adapter prior to registering it
  1430. * with the outside world, call drm_dp_aux_init() first. You must still
  1431. * call drm_dp_aux_register() once the connector has been registered to
  1432. * allow userspace access to the auxiliary DP channel.
  1433. */
  1434. void drm_dp_aux_init(struct drm_dp_aux *aux)
  1435. {
  1436. mutex_init(&aux->hw_mutex);
  1437. mutex_init(&aux->cec.lock);
  1438. INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
  1439. aux->ddc.algo = &drm_dp_i2c_algo;
  1440. aux->ddc.algo_data = aux;
  1441. aux->ddc.retries = 3;
  1442. aux->ddc.lock_ops = &drm_dp_i2c_lock_ops;
  1443. }
  1444. EXPORT_SYMBOL(drm_dp_aux_init);
  1445. /**
  1446. * drm_dp_aux_register() - initialise and register aux channel
  1447. * @aux: DisplayPort AUX channel
  1448. *
  1449. * Automatically calls drm_dp_aux_init() if this hasn't been done yet.
  1450. * This should only be called when the underlying &struct drm_connector is
  1451. * initialiazed already. Therefore the best place to call this is from
  1452. * &drm_connector_funcs.late_register. Not that drivers which don't follow this
  1453. * will Oops when CONFIG_DRM_DP_AUX_CHARDEV is enabled.
  1454. *
  1455. * Drivers which need to use the aux channel before that point (e.g. at driver
  1456. * load time, before drm_dev_register() has been called) need to call
  1457. * drm_dp_aux_init().
  1458. *
  1459. * Returns 0 on success or a negative error code on failure.
  1460. */
  1461. int drm_dp_aux_register(struct drm_dp_aux *aux)
  1462. {
  1463. int ret;
  1464. if (!aux->ddc.algo)
  1465. drm_dp_aux_init(aux);
  1466. aux->ddc.class = I2C_CLASS_DDC;
  1467. aux->ddc.owner = THIS_MODULE;
  1468. aux->ddc.dev.parent = aux->dev;
  1469. strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev),
  1470. sizeof(aux->ddc.name));
  1471. ret = drm_dp_aux_register_devnode(aux);
  1472. if (ret)
  1473. return ret;
  1474. ret = i2c_add_adapter(&aux->ddc);
  1475. if (ret) {
  1476. drm_dp_aux_unregister_devnode(aux);
  1477. return ret;
  1478. }
  1479. return 0;
  1480. }
  1481. EXPORT_SYMBOL(drm_dp_aux_register);
  1482. /**
  1483. * drm_dp_aux_unregister() - unregister an AUX adapter
  1484. * @aux: DisplayPort AUX channel
  1485. */
  1486. void drm_dp_aux_unregister(struct drm_dp_aux *aux)
  1487. {
  1488. drm_dp_aux_unregister_devnode(aux);
  1489. i2c_del_adapter(&aux->ddc);
  1490. }
  1491. EXPORT_SYMBOL(drm_dp_aux_unregister);
  1492. #define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x)
  1493. /**
  1494. * drm_dp_psr_setup_time() - PSR setup in time usec
  1495. * @psr_cap: PSR capabilities from DPCD
  1496. *
  1497. * Returns:
  1498. * PSR setup time for the panel in microseconds, negative
  1499. * error code on failure.
  1500. */
  1501. int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
  1502. {
  1503. static const u16 psr_setup_time_us[] = {
  1504. PSR_SETUP_TIME(330),
  1505. PSR_SETUP_TIME(275),
  1506. PSR_SETUP_TIME(220),
  1507. PSR_SETUP_TIME(165),
  1508. PSR_SETUP_TIME(110),
  1509. PSR_SETUP_TIME(55),
  1510. PSR_SETUP_TIME(0),
  1511. };
  1512. int i;
  1513. i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT;
  1514. if (i >= ARRAY_SIZE(psr_setup_time_us))
  1515. return -EINVAL;
  1516. return psr_setup_time_us[i];
  1517. }
  1518. EXPORT_SYMBOL(drm_dp_psr_setup_time);
  1519. #undef PSR_SETUP_TIME
  1520. /**
  1521. * drm_dp_start_crc() - start capture of frame CRCs
  1522. * @aux: DisplayPort AUX channel
  1523. * @crtc: CRTC displaying the frames whose CRCs are to be captured
  1524. *
  1525. * Returns 0 on success or a negative error code on failure.
  1526. */
  1527. int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc)
  1528. {
  1529. u8 buf;
  1530. int ret;
  1531. ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
  1532. if (ret < 0)
  1533. return ret;
  1534. ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf | DP_TEST_SINK_START);
  1535. if (ret < 0)
  1536. return ret;
  1537. aux->crc_count = 0;
  1538. aux->crtc = crtc;
  1539. schedule_work(&aux->crc_work);
  1540. return 0;
  1541. }
  1542. EXPORT_SYMBOL(drm_dp_start_crc);
  1543. /**
  1544. * drm_dp_stop_crc() - stop capture of frame CRCs
  1545. * @aux: DisplayPort AUX channel
  1546. *
  1547. * Returns 0 on success or a negative error code on failure.
  1548. */
  1549. int drm_dp_stop_crc(struct drm_dp_aux *aux)
  1550. {
  1551. u8 buf;
  1552. int ret;
  1553. ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
  1554. if (ret < 0)
  1555. return ret;
  1556. ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf & ~DP_TEST_SINK_START);
  1557. if (ret < 0)
  1558. return ret;
  1559. flush_work(&aux->crc_work);
  1560. aux->crtc = NULL;
  1561. return 0;
  1562. }
  1563. EXPORT_SYMBOL(drm_dp_stop_crc);
  1564. struct dpcd_quirk {
  1565. u8 oui[3];
  1566. u8 device_id[6];
  1567. bool is_branch;
  1568. u32 quirks;
  1569. };
  1570. #define OUI(first, second, third) { (first), (second), (third) }
  1571. #define DEVICE_ID(first, second, third, fourth, fifth, sixth) \
  1572. { (first), (second), (third), (fourth), (fifth), (sixth) }
  1573. #define DEVICE_ID_ANY DEVICE_ID(0, 0, 0, 0, 0, 0)
  1574. static const struct dpcd_quirk dpcd_quirk_list[] = {
  1575. /* Analogix 7737 needs reduced M and N at HBR2 link rates */
  1576. { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
  1577. /* LG LP140WF6-SPM1 eDP panel */
  1578. { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
  1579. /* Apple panels need some additional handling to support PSR */
  1580. { OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) },
  1581. /* CH7511 seems to leave SINK_COUNT zeroed */
  1582. { OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
  1583. /* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */
  1584. { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
  1585. /* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */
  1586. { OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
  1587. };
  1588. #undef OUI
  1589. /*
  1590. * Get a bit mask of DPCD quirks for the sink/branch device identified by
  1591. * ident. The quirk data is shared but it's up to the drivers to act on the
  1592. * data.
  1593. *
  1594. * For now, only the OUI (first three bytes) is used, but this may be extended
  1595. * to device identification string and hardware/firmware revisions later.
  1596. */
  1597. static u32
  1598. drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch)
  1599. {
  1600. const struct dpcd_quirk *quirk;
  1601. u32 quirks = 0;
  1602. int i;
  1603. u8 any_device[] = DEVICE_ID_ANY;
  1604. for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) {
  1605. quirk = &dpcd_quirk_list[i];
  1606. if (quirk->is_branch != is_branch)
  1607. continue;
  1608. if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0)
  1609. continue;
  1610. if (memcmp(quirk->device_id, any_device, sizeof(any_device)) != 0 &&
  1611. memcmp(quirk->device_id, ident->device_id, sizeof(ident->device_id)) != 0)
  1612. continue;
  1613. quirks |= quirk->quirks;
  1614. }
  1615. return quirks;
  1616. }
  1617. #undef DEVICE_ID_ANY
  1618. #undef DEVICE_ID
  1619. struct edid_quirk {
  1620. u8 mfg_id[2];
  1621. u8 prod_id[2];
  1622. u32 quirks;
  1623. };
  1624. #define MFG(first, second) { (first), (second) }
  1625. #define PROD_ID(first, second) { (first), (second) }
  1626. /*
  1627. * Some devices have unreliable OUIDs where they don't set the device ID
  1628. * correctly, and as a result we need to use the EDID for finding additional
  1629. * DP quirks in such cases.
  1630. */
  1631. static const struct edid_quirk edid_quirk_list[] = {
  1632. /* Optional 4K AMOLED panel in the ThinkPad X1 Extreme 2nd Generation
  1633. * only supports DPCD backlight controls
  1634. */
  1635. { MFG(0x4c, 0x83), PROD_ID(0x41, 0x41), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
  1636. /*
  1637. * Some Dell CML 2020 systems have panels support both AUX and PWM
  1638. * backlight control, and some only support AUX backlight control. All
  1639. * said panels start up in AUX mode by default, and we don't have any
  1640. * support for disabling HDR mode on these panels which would be
  1641. * required to switch to PWM backlight control mode (plus, I'm not
  1642. * even sure we want PWM backlight controls over DPCD backlight
  1643. * controls anyway...). Until we have a better way of detecting these,
  1644. * force DPCD backlight mode on all of them.
  1645. */
  1646. { MFG(0x06, 0xaf), PROD_ID(0x9b, 0x32), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
  1647. { MFG(0x06, 0xaf), PROD_ID(0xeb, 0x41), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
  1648. { MFG(0x4d, 0x10), PROD_ID(0xc7, 0x14), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
  1649. { MFG(0x4d, 0x10), PROD_ID(0xe6, 0x14), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
  1650. { MFG(0x4c, 0x83), PROD_ID(0x47, 0x41), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
  1651. };
  1652. #undef MFG
  1653. #undef PROD_ID
  1654. /**
  1655. * drm_dp_get_edid_quirks() - Check the EDID of a DP device to find additional
  1656. * DP-specific quirks
  1657. * @edid: The EDID to check
  1658. *
  1659. * While OUIDs are meant to be used to recognize a DisplayPort device, a lot
  1660. * of manufacturers don't seem to like following standards and neglect to fill
  1661. * the dev-ID in, making it impossible to only use OUIDs for determining
  1662. * quirks in some cases. This function can be used to check the EDID and look
  1663. * up any additional DP quirks. The bits returned by this function correspond
  1664. * to the quirk bits in &drm_dp_quirk.
  1665. *
  1666. * Returns: a bitmask of quirks, if any. The driver can check this using
  1667. * drm_dp_has_quirk().
  1668. */
  1669. u32 drm_dp_get_edid_quirks(const struct edid *edid)
  1670. {
  1671. const struct edid_quirk *quirk;
  1672. u32 quirks = 0;
  1673. int i;
  1674. if (!edid)
  1675. return 0;
  1676. for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
  1677. quirk = &edid_quirk_list[i];
  1678. if (memcmp(quirk->mfg_id, edid->mfg_id,
  1679. sizeof(edid->mfg_id)) == 0 &&
  1680. memcmp(quirk->prod_id, edid->prod_code,
  1681. sizeof(edid->prod_code)) == 0)
  1682. quirks |= quirk->quirks;
  1683. }
  1684. DRM_DEBUG_KMS("DP sink: EDID mfg %*phD prod-ID %*phD quirks: 0x%04x\n",
  1685. (int)sizeof(edid->mfg_id), edid->mfg_id,
  1686. (int)sizeof(edid->prod_code), edid->prod_code, quirks);
  1687. return quirks;
  1688. }
  1689. EXPORT_SYMBOL(drm_dp_get_edid_quirks);
  1690. /**
  1691. * drm_dp_read_desc - read sink/branch descriptor from DPCD
  1692. * @aux: DisplayPort AUX channel
  1693. * @desc: Device descriptor to fill from DPCD
  1694. * @is_branch: true for branch devices, false for sink devices
  1695. *
  1696. * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the
  1697. * identification.
  1698. *
  1699. * Returns 0 on success or a negative error code on failure.
  1700. */
  1701. int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
  1702. bool is_branch)
  1703. {
  1704. struct drm_dp_dpcd_ident *ident = &desc->ident;
  1705. unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI;
  1706. int ret, dev_id_len;
  1707. ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident));
  1708. if (ret < 0)
  1709. return ret;
  1710. desc->quirks = drm_dp_get_quirks(ident, is_branch);
  1711. dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id));
  1712. DRM_DEBUG_KMS("%s: DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n",
  1713. aux->name, is_branch ? "branch" : "sink",
  1714. (int)sizeof(ident->oui), ident->oui,
  1715. dev_id_len, ident->device_id,
  1716. ident->hw_rev >> 4, ident->hw_rev & 0xf,
  1717. ident->sw_major_rev, ident->sw_minor_rev,
  1718. desc->quirks);
  1719. return 0;
  1720. }
  1721. EXPORT_SYMBOL(drm_dp_read_desc);
  1722. /**
  1723. * drm_dp_dsc_sink_max_slice_count() - Get the max slice count
  1724. * supported by the DSC sink.
  1725. * @dsc_dpcd: DSC capabilities from DPCD
  1726. * @is_edp: true if its eDP, false for DP
  1727. *
  1728. * Read the slice capabilities DPCD register from DSC sink to get
  1729. * the maximum slice count supported. This is used to populate
  1730. * the DSC parameters in the &struct drm_dsc_config by the driver.
  1731. * Driver creates an infoframe using these parameters to populate
  1732. * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
  1733. * infoframe using the helper function drm_dsc_pps_infoframe_pack()
  1734. *
  1735. * Returns:
  1736. * Maximum slice count supported by DSC sink or 0 its invalid
  1737. */
  1738. u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
  1739. bool is_edp)
  1740. {
  1741. u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
  1742. if (is_edp) {
  1743. /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */
  1744. if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
  1745. return 4;
  1746. if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
  1747. return 2;
  1748. if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
  1749. return 1;
  1750. } else {
  1751. /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */
  1752. u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT];
  1753. if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK)
  1754. return 24;
  1755. if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK)
  1756. return 20;
  1757. if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK)
  1758. return 16;
  1759. if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)
  1760. return 12;
  1761. if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)
  1762. return 10;
  1763. if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)
  1764. return 8;
  1765. if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)
  1766. return 6;
  1767. if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
  1768. return 4;
  1769. if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
  1770. return 2;
  1771. if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
  1772. return 1;
  1773. }
  1774. return 0;
  1775. }
  1776. EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
  1777. /**
  1778. * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits
  1779. * @dsc_dpcd: DSC capabilities from DPCD
  1780. *
  1781. * Read the DSC DPCD register to parse the line buffer depth in bits which is
  1782. * number of bits of precision within the decoder line buffer supported by
  1783. * the DSC sink. This is used to populate the DSC parameters in the
  1784. * &struct drm_dsc_config by the driver.
  1785. * Driver creates an infoframe using these parameters to populate
  1786. * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
  1787. * infoframe using the helper function drm_dsc_pps_infoframe_pack()
  1788. *
  1789. * Returns:
  1790. * Line buffer depth supported by DSC panel or 0 its invalid
  1791. */
  1792. u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
  1793. {
  1794. u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT];
  1795. switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) {
  1796. case DP_DSC_LINE_BUF_BIT_DEPTH_9:
  1797. return 9;
  1798. case DP_DSC_LINE_BUF_BIT_DEPTH_10:
  1799. return 10;
  1800. case DP_DSC_LINE_BUF_BIT_DEPTH_11:
  1801. return 11;
  1802. case DP_DSC_LINE_BUF_BIT_DEPTH_12:
  1803. return 12;
  1804. case DP_DSC_LINE_BUF_BIT_DEPTH_13:
  1805. return 13;
  1806. case DP_DSC_LINE_BUF_BIT_DEPTH_14:
  1807. return 14;
  1808. case DP_DSC_LINE_BUF_BIT_DEPTH_15:
  1809. return 15;
  1810. case DP_DSC_LINE_BUF_BIT_DEPTH_16:
  1811. return 16;
  1812. case DP_DSC_LINE_BUF_BIT_DEPTH_8:
  1813. return 8;
  1814. }
  1815. return 0;
  1816. }
  1817. EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
  1818. /**
  1819. * drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component
  1820. * values supported by the DSC sink.
  1821. * @dsc_dpcd: DSC capabilities from DPCD
  1822. * @dsc_bpc: An array to be filled by this helper with supported
  1823. * input bpcs.
  1824. *
  1825. * Read the DSC DPCD from the sink device to parse the supported bits per
  1826. * component values. This is used to populate the DSC parameters
  1827. * in the &struct drm_dsc_config by the driver.
  1828. * Driver creates an infoframe using these parameters to populate
  1829. * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
  1830. * infoframe using the helper function drm_dsc_pps_infoframe_pack()
  1831. *
  1832. * Returns:
  1833. * Number of input BPC values parsed from the DPCD
  1834. */
  1835. int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
  1836. u8 dsc_bpc[3])
  1837. {
  1838. int num_bpc = 0;
  1839. u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
  1840. if (color_depth & DP_DSC_12_BPC)
  1841. dsc_bpc[num_bpc++] = 12;
  1842. if (color_depth & DP_DSC_10_BPC)
  1843. dsc_bpc[num_bpc++] = 10;
  1844. if (color_depth & DP_DSC_8_BPC)
  1845. dsc_bpc[num_bpc++] = 8;
  1846. return num_bpc;
  1847. }
  1848. EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
  1849. /**
  1850. * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
  1851. * @aux: DisplayPort AUX channel
  1852. * @data: DP phy compliance test parameters.
  1853. *
  1854. * Returns 0 on success or a negative error code on failure.
  1855. */
  1856. int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
  1857. struct drm_dp_phy_test_params *data)
  1858. {
  1859. int err;
  1860. u8 rate, lanes;
  1861. err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate);
  1862. if (err < 0)
  1863. return err;
  1864. data->link_rate = drm_dp_bw_code_to_link_rate(rate);
  1865. err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes);
  1866. if (err < 0)
  1867. return err;
  1868. data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
  1869. if (lanes & DP_ENHANCED_FRAME_CAP)
  1870. data->enhanced_frame_cap = true;
  1871. err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern);
  1872. if (err < 0)
  1873. return err;
  1874. switch (data->phy_pattern) {
  1875. case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
  1876. err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
  1877. &data->custom80, sizeof(data->custom80));
  1878. if (err < 0)
  1879. return err;
  1880. break;
  1881. case DP_PHY_TEST_PATTERN_CP2520:
  1882. err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
  1883. &data->hbr2_reset,
  1884. sizeof(data->hbr2_reset));
  1885. if (err < 0)
  1886. return err;
  1887. }
  1888. return 0;
  1889. }
  1890. EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
  1891. /**
  1892. * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
  1893. * @aux: DisplayPort AUX channel
  1894. * @data: DP phy compliance test parameters.
  1895. * @dp_rev: DP revision to use for compliance testing
  1896. *
  1897. * Returns 0 on success or a negative error code on failure.
  1898. */
  1899. int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
  1900. struct drm_dp_phy_test_params *data, u8 dp_rev)
  1901. {
  1902. int err, i;
  1903. u8 link_config[2];
  1904. u8 test_pattern;
  1905. link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
  1906. link_config[1] = data->num_lanes;
  1907. if (data->enhanced_frame_cap)
  1908. link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
  1909. err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2);
  1910. if (err < 0)
  1911. return err;
  1912. test_pattern = data->phy_pattern;
  1913. if (dp_rev < 0x12) {
  1914. test_pattern = (test_pattern << 2) &
  1915. DP_LINK_QUAL_PATTERN_11_MASK;
  1916. err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
  1917. test_pattern);
  1918. if (err < 0)
  1919. return err;
  1920. } else {
  1921. for (i = 0; i < data->num_lanes; i++) {
  1922. err = drm_dp_dpcd_writeb(aux,
  1923. DP_LINK_QUAL_LANE0_SET + i,
  1924. test_pattern);
  1925. if (err < 0)
  1926. return err;
  1927. }
  1928. }
  1929. return 0;
  1930. }
  1931. EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
  1932. static const char *dp_pixelformat_get_name(enum dp_pixelformat pixelformat)
  1933. {
  1934. if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
  1935. return "Invalid";
  1936. switch (pixelformat) {
  1937. case DP_PIXELFORMAT_RGB:
  1938. return "RGB";
  1939. case DP_PIXELFORMAT_YUV444:
  1940. return "YUV444";
  1941. case DP_PIXELFORMAT_YUV422:
  1942. return "YUV422";
  1943. case DP_PIXELFORMAT_YUV420:
  1944. return "YUV420";
  1945. case DP_PIXELFORMAT_Y_ONLY:
  1946. return "Y_ONLY";
  1947. case DP_PIXELFORMAT_RAW:
  1948. return "RAW";
  1949. default:
  1950. return "Reserved";
  1951. }
  1952. }
  1953. static const char *dp_colorimetry_get_name(enum dp_pixelformat pixelformat,
  1954. enum dp_colorimetry colorimetry)
  1955. {
  1956. if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
  1957. return "Invalid";
  1958. switch (colorimetry) {
  1959. case DP_COLORIMETRY_DEFAULT:
  1960. switch (pixelformat) {
  1961. case DP_PIXELFORMAT_RGB:
  1962. return "sRGB";
  1963. case DP_PIXELFORMAT_YUV444:
  1964. case DP_PIXELFORMAT_YUV422:
  1965. case DP_PIXELFORMAT_YUV420:
  1966. return "BT.601";
  1967. case DP_PIXELFORMAT_Y_ONLY:
  1968. return "DICOM PS3.14";
  1969. case DP_PIXELFORMAT_RAW:
  1970. return "Custom Color Profile";
  1971. default:
  1972. return "Reserved";
  1973. }
  1974. case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */
  1975. switch (pixelformat) {
  1976. case DP_PIXELFORMAT_RGB:
  1977. return "Wide Fixed";
  1978. case DP_PIXELFORMAT_YUV444:
  1979. case DP_PIXELFORMAT_YUV422:
  1980. case DP_PIXELFORMAT_YUV420:
  1981. return "BT.709";
  1982. default:
  1983. return "Reserved";
  1984. }
  1985. case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */
  1986. switch (pixelformat) {
  1987. case DP_PIXELFORMAT_RGB:
  1988. return "Wide Float";
  1989. case DP_PIXELFORMAT_YUV444:
  1990. case DP_PIXELFORMAT_YUV422:
  1991. case DP_PIXELFORMAT_YUV420:
  1992. return "xvYCC 601";
  1993. default:
  1994. return "Reserved";
  1995. }
  1996. case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
  1997. switch (pixelformat) {
  1998. case DP_PIXELFORMAT_RGB:
  1999. return "OpRGB";
  2000. case DP_PIXELFORMAT_YUV444:
  2001. case DP_PIXELFORMAT_YUV422:
  2002. case DP_PIXELFORMAT_YUV420:
  2003. return "xvYCC 709";
  2004. default:
  2005. return "Reserved";
  2006. }
  2007. case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */
  2008. switch (pixelformat) {
  2009. case DP_PIXELFORMAT_RGB:
  2010. return "DCI-P3";
  2011. case DP_PIXELFORMAT_YUV444:
  2012. case DP_PIXELFORMAT_YUV422:
  2013. case DP_PIXELFORMAT_YUV420:
  2014. return "sYCC 601";
  2015. default:
  2016. return "Reserved";
  2017. }
  2018. case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */
  2019. switch (pixelformat) {
  2020. case DP_PIXELFORMAT_RGB:
  2021. return "Custom Profile";
  2022. case DP_PIXELFORMAT_YUV444:
  2023. case DP_PIXELFORMAT_YUV422:
  2024. case DP_PIXELFORMAT_YUV420:
  2025. return "OpYCC 601";
  2026. default:
  2027. return "Reserved";
  2028. }
  2029. case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */
  2030. switch (pixelformat) {
  2031. case DP_PIXELFORMAT_RGB:
  2032. return "BT.2020 RGB";
  2033. case DP_PIXELFORMAT_YUV444:
  2034. case DP_PIXELFORMAT_YUV422:
  2035. case DP_PIXELFORMAT_YUV420:
  2036. return "BT.2020 CYCC";
  2037. default:
  2038. return "Reserved";
  2039. }
  2040. case DP_COLORIMETRY_BT2020_YCC:
  2041. switch (pixelformat) {
  2042. case DP_PIXELFORMAT_YUV444:
  2043. case DP_PIXELFORMAT_YUV422:
  2044. case DP_PIXELFORMAT_YUV420:
  2045. return "BT.2020 YCC";
  2046. default:
  2047. return "Reserved";
  2048. }
  2049. default:
  2050. return "Invalid";
  2051. }
  2052. }
  2053. static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range)
  2054. {
  2055. switch (dynamic_range) {
  2056. case DP_DYNAMIC_RANGE_VESA:
  2057. return "VESA range";
  2058. case DP_DYNAMIC_RANGE_CTA:
  2059. return "CTA range";
  2060. default:
  2061. return "Invalid";
  2062. }
  2063. }
  2064. static const char *dp_content_type_get_name(enum dp_content_type content_type)
  2065. {
  2066. switch (content_type) {
  2067. case DP_CONTENT_TYPE_NOT_DEFINED:
  2068. return "Not defined";
  2069. case DP_CONTENT_TYPE_GRAPHICS:
  2070. return "Graphics";
  2071. case DP_CONTENT_TYPE_PHOTO:
  2072. return "Photo";
  2073. case DP_CONTENT_TYPE_VIDEO:
  2074. return "Video";
  2075. case DP_CONTENT_TYPE_GAME:
  2076. return "Game";
  2077. default:
  2078. return "Reserved";
  2079. }
  2080. }
  2081. void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
  2082. const struct drm_dp_vsc_sdp *vsc)
  2083. {
  2084. #define DP_SDP_LOG(fmt, ...) dev_printk(level, dev, fmt, ##__VA_ARGS__)
  2085. DP_SDP_LOG("DP SDP: %s, revision %u, length %u\n", "VSC",
  2086. vsc->revision, vsc->length);
  2087. DP_SDP_LOG(" pixelformat: %s\n",
  2088. dp_pixelformat_get_name(vsc->pixelformat));
  2089. DP_SDP_LOG(" colorimetry: %s\n",
  2090. dp_colorimetry_get_name(vsc->pixelformat, vsc->colorimetry));
  2091. DP_SDP_LOG(" bpc: %u\n", vsc->bpc);
  2092. DP_SDP_LOG(" dynamic range: %s\n",
  2093. dp_dynamic_range_get_name(vsc->dynamic_range));
  2094. DP_SDP_LOG(" content type: %s\n",
  2095. dp_content_type_get_name(vsc->content_type));
  2096. #undef DP_SDP_LOG
  2097. }
  2098. EXPORT_SYMBOL(drm_dp_vsc_sdp_log);