light.dtsi 57 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2021 Alibaba Group Holding Limited.
  4. */
  5. #include <dt-bindings/pinctrl/light-fm-left-pinctrl.h>
  6. #include <dt-bindings/pinctrl/light-fm-right-pinctrl.h>
  7. #include <dt-bindings/pinctrl/light-fm-aon-pinctrl.h>
  8. #include <dt-bindings/clock/light-fm-ap-clock.h>
  9. #include <dt-bindings/clock/light-vpsys.h>
  10. #include <dt-bindings/clock/light-vosys.h>
  11. #include <dt-bindings/clock/light-visys.h>
  12. #include <dt-bindings/clock/light-dspsys.h>
  13. #include <dt-bindings/firmware/thead/rsrc.h>
  14. #include <dt-bindings/soc/thead,light-iopmp.h>
  15. #include <dt-bindings/thermal/thermal.h>
  16. #include <dt-bindings/reset/light-reset.h>
  17. / {
  18. compatible = "thead,light";
  19. #address-cells = <2>;
  20. #size-cells = <2>;
  21. aliases {
  22. ethernet0 = &gmac0;
  23. ethernet1 = &gmac1;
  24. gpio0 = &gpio0;
  25. gpio1 = &gpio1;
  26. gpio2 = &gpio2;
  27. gpio3 = &gpio3;
  28. i2c0 = &i2c0;
  29. i2c1 = &i2c1;
  30. i2c2 = &i2c2;
  31. i2c3 = &i2c3;
  32. i2c4 = &i2c4;
  33. audio_i2c0 = &audio_i2c0;
  34. audio_i2c1 = &audio_i2c1;
  35. mmc0 = &emmc;
  36. mmc1 = &sdhci0;
  37. serial0 = &uart0;
  38. serial1 = &uart1;
  39. serial2 = &uart2;
  40. serial3 = &uart3;
  41. serial4 = &uart4;
  42. serial5 = &uart5;
  43. spi0 = &spi0;
  44. spi1 = &qspi0;
  45. spi2 = &qspi1;
  46. flash_led0 = &vvcam_flash_led0;
  47. vivcam0 = &vvcam_sensor0;
  48. vivcam1 = &vvcam_sensor1;
  49. vivcam2 = &vvcam_sensor2;
  50. vivcam3 = &vvcam_sensor3;
  51. vivcam4 = &vvcam_sensor4;
  52. vivcam5 = &vvcam_sensor5;
  53. vivcam6 = &vvcam_sensor6;
  54. viv_video0 = &video0;
  55. viv_video1 = &video1;
  56. viv_video2 = &video2;
  57. viv_video3 = &video3;
  58. viv_video4 = &video4;
  59. viv_video5 = &video5;
  60. viv_video6 = &video6;
  61. viv_video7 = &video7;
  62. viv_video8 = &video8;
  63. viv_video9 = &video9;
  64. viv_video10 = &video10;
  65. viv_video11 = &video11;
  66. viv_video12 = &video12;
  67. viv_video13 = &video13;
  68. viv_video14 = &video14;
  69. viv_video15 = &video15;
  70. };
  71. memory@0 {
  72. device_type = "memory";
  73. reg = <0x0 0x200000 0x0 0xffe00000>;
  74. };
  75. resmem: reserved-memory {
  76. #address-cells = <2>;
  77. #size-cells = <2>;
  78. ranges;
  79. /* global autoconfigured region for contiguous allocations */
  80. cmamem: linux,cma {
  81. compatible = "shared-dma-pool";
  82. reusable;
  83. size = <0 0x14000000>; // 320MB by default
  84. alloc-ranges = <0 0x64000000 0 0x14000000>; // [0x6400_0000 ~ 0x7800_0000]
  85. linux,cma-default;
  86. };
  87. };
  88. thermal-zones {
  89. cpu-thermal-zone {
  90. polling-delay-passive = <250>;
  91. polling-delay = <2000>;
  92. thermal-sensors = <&pvt 0>;
  93. trips {
  94. cpu_config0: trip0 {
  95. temperature = <85000>;
  96. hysteresis = <2000>;
  97. type = "passive";
  98. };
  99. cpu_config1: trip1 {
  100. temperature = <110000>;
  101. hysteresis = <2000>;
  102. type = "critical";
  103. };
  104. };
  105. cooling-maps {
  106. cpu_cdev {
  107. trip = <&cpu_config0>;
  108. cooling-device =
  109. <&c910_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  110. <&c910_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  111. <&c910_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  112. <&c910_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  113. };
  114. };
  115. };
  116. };
  117. cpus: cpus {
  118. #address-cells = <1>;
  119. #size-cells = <0>;
  120. timebase-frequency = <3000000>;
  121. c910_0: cpu@0 {
  122. device_type = "cpu";
  123. reg = <0>;
  124. status = "okay";
  125. compatible = "riscv";
  126. riscv,isa = "rv64imafdcvsu";
  127. mmu-type = "riscv,sv39";
  128. cpu-freq = "1.848Ghz";
  129. cpu-icache = "64KB";
  130. cpu-dcache = "64KB";
  131. cpu-l2cache = "1MB";
  132. cpu-tlb = "1024 4-ways";
  133. cpu-cacheline = "64Bytes";
  134. cpu-vector = "0.7.1";
  135. #cooling-cells = <2>;
  136. operating-points = <
  137. /* kHz uV */
  138. 300000 600000
  139. 800000 700000
  140. 1500000 800000
  141. 1848000 1000000
  142. >;
  143. light,dvddm-operating-points = <
  144. /* kHz uV */
  145. 300000 750000
  146. 800000 800000
  147. 1500000 800000
  148. 1848000 1000000
  149. >;
  150. clock-latency = <61036>;
  151. clocks = <&clk C910_CCLK>,
  152. <&clk C910_CCLK_I0>,
  153. <&clk CPU_PLL1_FOUTPOSTDIV>,
  154. <&clk CPU_PLL0_FOUTPOSTDIV>;
  155. clock-names = "c910_cclk", "c910_cclk_i0",
  156. "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
  157. dvdd-supply = <&dvdd_cpu_reg>;
  158. dvddm-supply = <&dvddm_cpu_reg>;
  159. cpu0_intc: interrupt-controller {
  160. #interrupt-cells = <1>;
  161. compatible = "riscv,cpu-intc";
  162. interrupt-controller;
  163. };
  164. };
  165. c910_1: cpu@1 {
  166. device_type = "cpu";
  167. reg = <1>;
  168. status = "okay";
  169. compatible = "riscv";
  170. riscv,isa = "rv64imafdcvsu";
  171. mmu-type = "riscv,sv39";
  172. cpu-freq = "1.848Ghz";
  173. cpu-icache = "64KB";
  174. cpu-dcache = "64KB";
  175. cpu-l2cache = "1MB";
  176. cpu-tlb = "1024 4-ways";
  177. cpu-cacheline = "64Bytes";
  178. cpu-vector = "0.7.1";
  179. #cooling-cells = <2>;
  180. operating-points = <
  181. /* kHz uV */
  182. 300000 600000
  183. 800000 700000
  184. 1500000 800000
  185. 1848000 1000000
  186. >;
  187. light,dvddm-operating-points = <
  188. /* kHz uV */
  189. 300000 750000
  190. 800000 800000
  191. 1500000 800000
  192. 1848000 1000000
  193. >;
  194. clock-latency = <61036>;
  195. clocks = <&clk C910_CCLK>,
  196. <&clk C910_CCLK_I0>,
  197. <&clk CPU_PLL1_FOUTPOSTDIV>,
  198. <&clk CPU_PLL0_FOUTPOSTDIV>;
  199. clock-names = "c910_cclk", "c910_cclk_i0",
  200. "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
  201. dvdd-supply = <&dvdd_cpu_reg>;
  202. dvddm-supply = <&dvddm_cpu_reg>;
  203. cpu1_intc: interrupt-controller {
  204. #interrupt-cells = <1>;
  205. compatible = "riscv,cpu-intc";
  206. interrupt-controller;
  207. };
  208. };
  209. c910_2: cpu@2 {
  210. device_type = "cpu";
  211. reg = <2>;
  212. status = "okay";
  213. compatible = "riscv";
  214. riscv,isa = "rv64imafdcvsu";
  215. mmu-type = "riscv,sv39";
  216. cpu-freq = "1.848Ghz";
  217. cpu-icache = "64KB";
  218. cpu-dcache = "64KB";
  219. cpu-l2cache = "1MB";
  220. cpu-tlb = "1024 4-ways";
  221. cpu-cacheline = "64Bytes";
  222. cpu-vector = "0.7.1";
  223. #cooling-cells = <2>;
  224. operating-points = <
  225. /* kHz uV */
  226. 300000 600000
  227. 800000 700000
  228. 1500000 800000
  229. 1848000 1000000
  230. >;
  231. light,dvddm-operating-points = <
  232. /* kHz uV */
  233. 300000 750000
  234. 800000 800000
  235. 1500000 800000
  236. 1848000 1000000
  237. >;
  238. clock-latency = <61036>;
  239. clocks = <&clk C910_CCLK>,
  240. <&clk C910_CCLK_I0>,
  241. <&clk CPU_PLL1_FOUTPOSTDIV>,
  242. <&clk CPU_PLL0_FOUTPOSTDIV>;
  243. clock-names = "c910_cclk", "c910_cclk_i0",
  244. "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
  245. dvdd-supply = <&dvdd_cpu_reg>;
  246. dvddm-supply = <&dvddm_cpu_reg>;
  247. cpu2_intc: interrupt-controller {
  248. #interrupt-cells = <1>;
  249. compatible = "riscv,cpu-intc";
  250. interrupt-controller;
  251. };
  252. };
  253. c910_3: cpu@3 {
  254. device_type = "cpu";
  255. reg = <3>;
  256. status = "okay";
  257. compatible = "riscv";
  258. riscv,isa = "rv64imafdcvsu";
  259. mmu-type = "riscv,sv39";
  260. cpu-freq = "1.848Ghz";
  261. cpu-icache = "64KB";
  262. cpu-dcache = "64KB";
  263. cpu-l2cache = "1MB";
  264. cpu-tlb = "1024 4-ways";
  265. cpu-cacheline = "64Bytes";
  266. cpu-vector = "0.7.1";
  267. #cooling-cells = <2>;
  268. operating-points = <
  269. /* kHz uV */
  270. 300000 600000
  271. 800000 700000
  272. 1500000 800000
  273. 1848000 1000000
  274. >;
  275. light,dvddm-operating-points = <
  276. /* kHz uV */
  277. 300000 750000
  278. 800000 800000
  279. 1500000 800000
  280. 1848000 1000000
  281. >;
  282. clock-latency = <61036>;
  283. clocks = <&clk C910_CCLK>,
  284. <&clk C910_CCLK_I0>,
  285. <&clk CPU_PLL1_FOUTPOSTDIV>,
  286. <&clk CPU_PLL0_FOUTPOSTDIV>;
  287. clock-names = "c910_cclk", "c910_cclk_i0",
  288. "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
  289. dvdd-supply = <&dvdd_cpu_reg>;
  290. dvddm-supply = <&dvddm_cpu_reg>;
  291. cpu3_intc: interrupt-controller {
  292. #interrupt-cells = <1>;
  293. compatible = "riscv,cpu-intc";
  294. interrupt-controller;
  295. };
  296. };
  297. };
  298. display-subsystem {
  299. compatible = "verisilicon,display-subsystem";
  300. ports = <&dpu_disp0>, <&dpu_disp1>;
  301. status = "disabled";
  302. };
  303. dpu-encoders {
  304. compatible = "simple-bus";
  305. #address-cells = <1>;
  306. #size-cells = <0>;
  307. dpu_enc0: dpu-encoder@0 {
  308. /* default encoder is DSI */
  309. compatible = "verisilicon,dsi-encoder";
  310. reg = <0>;
  311. status = "disabled";
  312. ports {
  313. #address-cells = <1>;
  314. #size-cells = <0>;
  315. /* input */
  316. port@0 {
  317. reg = <0>;
  318. enc0_in: endpoint {
  319. remote-endpoint = <&disp0_out>;
  320. };
  321. };
  322. };
  323. };
  324. dpu_enc1: dpu-encoder@1 {
  325. /* default encoder is DSI */
  326. compatible = "verisilicon,dsi-encoder";
  327. reg = <1>;
  328. status = "disabled";
  329. ports {
  330. #address-cells = <1>;
  331. #size-cells = <0>;
  332. /* input */
  333. port@0 {
  334. reg = <0>;
  335. enc1_in: endpoint {
  336. remote-endpoint = <&disp1_out>;
  337. };
  338. };
  339. };
  340. };
  341. };
  342. soc {
  343. compatible = "simple-bus";
  344. #address-cells = <2>;
  345. #size-cells = <2>;
  346. ranges;
  347. reset: reset-sample {
  348. compatible = "thead,reset-sample";
  349. plic-delegate = <0xff 0xd81ffffc>;
  350. entry-reg = <0xff 0xff019050>;
  351. entry-cnt = <4>;
  352. control-reg = <0xff 0xff015004>;
  353. control-val = <0x1c>;
  354. csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
  355. };
  356. clint0: clint@ffdc000000 {
  357. compatible = "riscv,clint0";
  358. interrupts-extended = <
  359. &cpu0_intc 3 &cpu0_intc 7
  360. &cpu1_intc 3 &cpu1_intc 7
  361. &cpu2_intc 3 &cpu2_intc 7
  362. &cpu3_intc 3 &cpu3_intc 7
  363. >;
  364. reg = <0xff 0xdc000000 0x0 0x04000000>;
  365. clint,has-no-64bit-mmio;
  366. };
  367. intc: interrupt-controller@ffd8000000 {
  368. #interrupt-cells = <1>;
  369. compatible = "riscv,plic0";
  370. interrupt-controller;
  371. interrupts-extended = <
  372. &cpu0_intc 0xffffffff &cpu0_intc 9
  373. &cpu1_intc 0xffffffff &cpu1_intc 9
  374. &cpu2_intc 0xffffffff &cpu2_intc 9
  375. &cpu3_intc 0xffffffff &cpu3_intc 9
  376. >;
  377. reg = <0xff 0xd8000000 0x0 0x04000000>;
  378. reg-names = "control";
  379. riscv,max-priority = <7>;
  380. riscv,ndev = <240>;
  381. };
  382. clocks {
  383. compatible = "simple-bus";
  384. #address-cells = <1>;
  385. #size-cells = <0>;
  386. dummy_clock_apb: apb-clock@0 {
  387. compatible = "fixed-clock";
  388. reg = <0>; /* Not address, just for index */
  389. clock-frequency = <62500000>;
  390. clock-output-names = "dummy_clock_apb";
  391. #clock-cells = <0>;
  392. };
  393. dummy_clock_ref: ref-clock@1 {
  394. compatible = "fixed-clock";
  395. reg = <1>; /* Not address, just for index */
  396. clock-frequency = <50000000>;
  397. clock-output-names = "dummy_clock_ref";
  398. #clock-cells = <0>;
  399. };
  400. dummy_clock_suspend: suspend-clock@2 {
  401. compatible = "fixed-clock";
  402. reg = <2>; /* Not address, just for index */
  403. clock-frequency = <50000000>;
  404. clock-output-names = "dummy_clock_suspend";
  405. #clock-cells = <0>;
  406. };
  407. dummy_clock_rtc: rtc-clock@3 {
  408. compatible = "fixed-clock";
  409. reg = <3>; /* Not address, just for index */
  410. clock-frequency = <32768>;
  411. clock-output-names = "dummy_clock_rtc";
  412. #clock-cells = <0>;
  413. };
  414. dummy_clock_ahb: ahb-clock@4 {
  415. compatible = "fixed-clock";
  416. reg = <4>; /* Not address, just for index */
  417. clock-frequency = <50000000>;
  418. clock-output-names = "dummy_clock_ahb";
  419. #clock-cells = <0>;
  420. };
  421. dummy_clock_gpu: gpu-clock@6 {
  422. compatible = "fixed-clock";
  423. reg = <6>; /* Not address, just for index */
  424. clock-frequency = <18000000>;
  425. clock-output-names = "dummy_clock_gpu";
  426. #clock-cells = <0>;
  427. };
  428. dummy_clock_dphy_ref: dphy-ref-clock@7 {
  429. compatible = "fixed-clock";
  430. reg = <7>; /* Not address, just for index */
  431. clock-frequency = <24000000>;
  432. clock-output-names = "dummy_clock_dphy_ref";
  433. #clock-cells = <0>;
  434. };
  435. dummy_clock_dphy_cfg: dphy-cfg-clock@8 {
  436. compatible = "fixed-clock";
  437. reg = <8>; /* Not address, just for index */
  438. clock-frequency = <24000000>;
  439. clock-output-names = "dummy_clock_dphy_cfg";
  440. #clock-cells = <0>;
  441. };
  442. dummy_clock_dpu_pixel0: dpu-pixel-clock@9 {
  443. compatible = "fixed-clock";
  444. reg = <9>;
  445. clock-frequency = <72000000>;
  446. clock-output-names = "dummy_clock_dpu_pixel0";
  447. #clock-cells = <0>;
  448. };
  449. dummy_clock_dpu_pixel1: dpu-pixel-clock@10 {
  450. compatible = "fixed-clock";
  451. reg = <10>;
  452. clock-frequency = <74250000>;
  453. clock-output-names = "dummy_clock_dpu_pixel1";
  454. #clock-cells = <0>;
  455. };
  456. osc_32k: clock-osc-32k@11 {
  457. compatible = "fixed-clock";
  458. reg = <11>;
  459. #clock-cells = <0>;
  460. clock-frequency = <32768>;
  461. clock-output-names = "osc_32k";
  462. };
  463. osc_24m: clock-osc-24m@12 {
  464. compatible = "fixed-clock";
  465. reg = <12>;
  466. #clock-cells = <0>;
  467. clock-frequency = <24000000>;
  468. clock-output-names = "osc_24m";
  469. };
  470. rc_24m: clock-rc-24m@13 {
  471. compatible = "fixed-clock";
  472. reg = <13>;
  473. #clock-cells = <0>;
  474. clock-frequency = <24000000>;
  475. clock-output-names = "rc_24m";
  476. };
  477. dummy_clock_eip: eip-clock@14 {
  478. compatible = "fixed-clock";
  479. reg = <14>; /* Not address, just for index */
  480. clock-frequency = <400000000>;
  481. clock-output-names = "dummy_clock_eip";
  482. #clock-cells = <0>;
  483. };
  484. dummy_clock_spi: spi-clock@15 {
  485. compatible = "fixed-clock";
  486. reg = <15>; /* Not address, just for index */
  487. clock-frequency = <396000000>;
  488. clock-output-names = "dummy_clock_spi";
  489. #clock-cells = <0>;
  490. };
  491. dummy_clock_qspi: spi-clock@16 {
  492. compatible = "fixed-clock";
  493. reg = <15>; /* Not address, just for index */
  494. clock-frequency = <792000000>;
  495. clock-output-names = "dummy_clock_qspi";
  496. #clock-cells = <0>;
  497. };
  498. dummy_gmac_ahb: gmac-ahb-clock@16 {
  499. compatible = "fixed-clock";
  500. reg = <16>;
  501. clock-frequency = <250000000>;
  502. clock-output-names = "dummy_gmac_ahb";
  503. #clock-cells = <0>;
  504. };
  505. dummy_clock_gmac: gmac-clock@17 {
  506. compatible = "fixed-clock";
  507. reg = <17>;
  508. clock-frequency = <500000000>;
  509. clock-output-names = "dummy_clock_gmac";
  510. #clock-cells = <0>;
  511. };
  512. dummy_clock_sdhci: sdhci-clock@18 {
  513. compatible = "fixed-clock";
  514. reg = <18>; /* Not address, just for index */
  515. clock-frequency = <198000000>;
  516. clock-output-names = "dummy_clock_sdhci";
  517. #clock-cells = <0>;
  518. };
  519. dummy_clock_aonsys_clk: aonsys-clk-clock@19 {
  520. compatible = "fixed-clock";
  521. reg = <19>; /* Not address, just for index */
  522. clock-frequency = <73728000>;
  523. clock-output-names = "dummy_clock_aonsys_clk";
  524. #clock-cells = <0>;
  525. };
  526. dummy_clock_uart_sclk: uart-sclk-clock@20 {
  527. compatible = "fixed-clock";
  528. reg = <20>; /* Not address, just for index */
  529. clock-frequency = <100000000>;
  530. clock-output-names = "dummy_clock_uart_sclk";
  531. #clock-cells = <0>;
  532. };
  533. dummy_clock_visys: visys-dummy-clock@21 {
  534. compatible = "fixed-clock";
  535. reg = <21>;
  536. clock-frequency = <24000000>;
  537. #clock-cells = <0>;
  538. };
  539. };
  540. iso7816: iso7816-card@fff7f30000 {
  541. compatible = "thead,light-iso7816-card";
  542. reg = <0xff 0xf7f30000 0x0 0x4000>;
  543. pinctrl-names = "default";
  544. pinctrl-0 = <&pinctrl_iso7816>;
  545. interrupts = <69>;
  546. interrupt-parent = <&intc>;
  547. status = "disabled";
  548. };
  549. teesys_syscon: teesys-reg@ffff200000 {
  550. compatible = "syscon";
  551. reg = <0xff 0xff200000 0x0 0x10000>;
  552. };
  553. visys_reg: visys-reg@ffe4040000 {
  554. compatible = "thead,light-visys-reg", "syscon";
  555. reg = <0xff 0xe4040000 0x0 0x1000>;
  556. status = "disabled";
  557. };
  558. dspsys_reg: dspsys-reg@ffef040000 {
  559. compatible = "thead,light-dspsys-reg", "syscon";
  560. reg = <0xff 0xef040000 0x0 0x1000>;
  561. status = "okay";
  562. };
  563. audio_ioctrl: audio_ioctrl@ffcb01d000 {
  564. compatible = "thead,light-audio-ioctrl-reg", "syscon";
  565. reg = <0xff 0xcb01d000 0x0 0x1000>;
  566. status = "okay";
  567. };
  568. audio_cpr: audio_cpr@ffcb000000 {
  569. compatible = "thead,light-audio-cpr-reg", "syscon";
  570. reg = <0xff 0xcb000000 0x0 0x1000>;
  571. status = "okay";
  572. };
  573. nvmem_controller: efuse@ffff210000 {
  574. compatible = "thead,light-fm-efuse", "syscon";
  575. reg = <0xff 0xff210000 0x0 0x10000>;
  576. thead,teesys = <&teesys_syscon>;
  577. #address-cells = <1>;
  578. #size-cells = <1>;
  579. gmac0_mac_address: mac-address@176 {
  580. reg = <0xb0 6>;
  581. };
  582. gmac1_mac_address: mac-address@184 {
  583. reg = <0xb8 6>;
  584. };
  585. };
  586. misc_sysreg: misc_sysreg@ffec02c000 {
  587. compatible = "thead,light-misc-sysreg", "syscon";
  588. reg = <0xff 0xec02c000 0x0 0x1000>;
  589. status = "okay";
  590. };
  591. usb3_drd: usb3_drd@ffec03f000 {
  592. compatible = "thead,light-usb3-drd", "syscon";
  593. reg = <0xff 0xec03f000 0x0 0x1000>;
  594. status = "okay";
  595. };
  596. gpio0: gpio@ffec005000 {
  597. compatible = "snps,dw-apb-gpio";
  598. reg = <0xff 0xec005000 0x0 0x1000>;
  599. #address-cells = <1>;
  600. #size-cells = <0>;
  601. gpio0_porta: gpio0-controller@0 {
  602. compatible = "snps,dw-apb-gpio-port";
  603. gpio-controller;
  604. #gpio-cells = <2>;
  605. nr-gpios-snps = <32>;
  606. reg = <0>;
  607. interrupt-controller;
  608. #interrupt-cells = <2>;
  609. interrupt-parent = <&intc>;
  610. interrupts = <56>;
  611. };
  612. };
  613. gpio1: gpio@ffec006000 {
  614. compatible = "snps,dw-apb-gpio";
  615. reg = <0xff 0xec006000 0x0 0x1000>;
  616. #address-cells = <1>;
  617. #size-cells = <0>;
  618. gpio1_porta: gpio1-controller@0 {
  619. compatible = "snps,dw-apb-gpio-port";
  620. gpio-controller;
  621. #gpio-cells = <2>;
  622. nr-gpios-snps = <32>;
  623. reg = <0>;
  624. interrupt-controller;
  625. #interrupt-cells = <2>;
  626. interrupt-parent = <&intc>;
  627. interrupts = <57>;
  628. };
  629. };
  630. gpio2: gpio@ffe7f34000 {
  631. compatible = "snps,dw-apb-gpio";
  632. reg = <0xff 0xe7f34000 0x0 0x1000>;
  633. #address-cells = <1>;
  634. #size-cells = <0>;
  635. gpio2_porta: gpio2-controller@0 {
  636. compatible = "snps,dw-apb-gpio-port";
  637. gpio-controller;
  638. #gpio-cells = <2>;
  639. nr-gpios-snps = <32>;
  640. reg = <0>;
  641. interrupt-controller;
  642. #interrupt-cells = <2>;
  643. interrupt-parent = <&intc>;
  644. interrupts = <58>;
  645. };
  646. };
  647. gpio3: gpio@ffe7f38000 {
  648. compatible = "snps,dw-apb-gpio";
  649. reg = <0xff 0xe7f38000 0x0 0x1000>;
  650. #address-cells = <1>;
  651. #size-cells = <0>;
  652. gpio3_porta: gpio3-controller@0 {
  653. compatible = "snps,dw-apb-gpio-port";
  654. gpio-controller;
  655. #gpio-cells = <2>;
  656. nr-gpios-snps = <32>;
  657. reg = <0>;
  658. interrupt-controller;
  659. #interrupt-cells = <2>;
  660. interrupt-parent = <&intc>;
  661. interrupts = <59>;
  662. };
  663. };
  664. ao_gpio: gpio@fffff41000 {
  665. compatible = "snps,dw-apb-gpio";
  666. reg = <0xff 0xfff41000 0x0 0x1000>;
  667. #address-cells = <1>;
  668. #size-cells = <0>;
  669. ao_gpio_porta: ao_gpio-controller@0 {
  670. compatible = "snps,dw-apb-gpio-port";
  671. gpio-controller;
  672. #gpio-cells = <2>;
  673. nr-gpios-snps = <32>;
  674. reg = <0>;
  675. interrupt-controller;
  676. #interrupt-cells = <2>;
  677. interrupt-parent = <&intc>;
  678. interrupts = <76>;
  679. };
  680. };
  681. ao_gpio4: gpio@fffff52000 {
  682. compatible = "snps,dw-apb-gpio";
  683. reg = <0xff 0xfff52000 0x0 0x1000>;
  684. #address-cells = <1>;
  685. #size-cells = <0>;
  686. ao_gpio4_porta: ao_gpio4-controller@0 {
  687. compatible = "snps,dw-apb-gpio-port";
  688. gpio-controller;
  689. #gpio-cells = <2>;
  690. nr-gpios-snps = <32>;
  691. reg = <0>;
  692. interrupt-controller;
  693. #interrupt-cells = <2>;
  694. interrupt-parent = <&intc>;
  695. interrupts = <55>;
  696. };
  697. };
  698. padctrl1_apsys: pinctrl1-apsys@ffe7f3c000 {
  699. compatible = "thead,light-fm-left-pinctrl";
  700. reg = <0xff 0xe7f3c000 0x0 0x1000>;
  701. status = "okay";
  702. };
  703. padctrl0_apsys: padctrl0-apsys@ffec007000 {
  704. compatible = "thead,light-fm-right-pinctrl";
  705. reg = <0xff 0xec007000 0x0 0x1000>;
  706. status = "okay";
  707. };
  708. pwm: pwm@ffec01c000 {
  709. compatible = "thead,pwm-light";
  710. reg = <0xff 0xec01c000 0x0 0x4000>;
  711. #pwm-cells = <2>;
  712. clocks = <&clk CLKGEN_PWM_PCLK>,
  713. <&clk CLKGEN_PWM_CCLK>;
  714. clock-names = "pclk", "cclk";
  715. pinctrl-names = "default";
  716. pinctrl-0 = <&pinctrl_pwm>;
  717. };
  718. timer0: timer@ffefc32000 {
  719. compatible = "snps,dw-apb-timer";
  720. reg = <0xff 0xefc32000 0x0 0x14>;
  721. clocks = <&dummy_clock_apb>;
  722. clock-names = "timer";
  723. clock-frequency = <62500000>;
  724. interrupts = <16>;
  725. interrupt-parent = <&intc>;
  726. status = "okay";
  727. };
  728. timer1: timer@ffefc32014 {
  729. compatible = "snps,dw-apb-timer";
  730. reg = <0xff 0xefc32014 0x0 0x14>;
  731. clocks = <&dummy_clock_apb>;
  732. clock-names = "timer";
  733. clock-frequency = <62500000>;
  734. interrupts = <17>;
  735. interrupt-parent = <&intc>;
  736. status = "okay";
  737. };
  738. timer2: timer@ffefc32028 {
  739. compatible = "snps,dw-apb-timer";
  740. reg = <0xff 0xefc32028 0x0 0x14>;
  741. clocks = <&dummy_clock_apb>;
  742. clock-names = "timer";
  743. clock-frequency = <62500000>;
  744. interrupts = <18>;
  745. interrupt-parent = <&intc>;
  746. status = "disabled";
  747. };
  748. timer3: timer@ffefc3203c {
  749. compatible = "snps,dw-apb-timer";
  750. reg = <0xff 0xefc3203c 0x0 0x14>;
  751. clocks = <&dummy_clock_apb>;
  752. clock-names = "timer";
  753. clock-frequency = <62500000>;
  754. interrupts = <19>;
  755. interrupt-parent = <&intc>;
  756. status = "disabled";
  757. };
  758. padctrl_aosys: padctrl-aosys@fffff4a000 {
  759. compatible = "thead,light-fm-aon-pinctrl";
  760. reg = <0xff 0xfff4a000 0x0 0x2000>;
  761. status = "okay";
  762. };
  763. timer4: timer@ffffc33000 {
  764. compatible = "snps,dw-apb-timer";
  765. reg = <0xff 0xffc33000 0x0 0x14>;
  766. clocks = <&dummy_clock_apb>;
  767. clock-names = "timer";
  768. clock-frequency = <62500000>;
  769. interrupts = <20>;
  770. interrupt-parent = <&intc>;
  771. status = "disabled";
  772. };
  773. timer5: timer@ffffc33014 {
  774. compatible = "snps,dw-apb-timer";
  775. reg = <0xff 0xffc33014 0x0 0x14>;
  776. clocks = <&dummy_clock_apb>;
  777. clock-names = "timer";
  778. clock-frequency = <62500000>;
  779. interrupts = <21>;
  780. interrupt-parent = <&intc>;
  781. status = "disabled";
  782. };
  783. timer6: timer@ffffc33028 {
  784. compatible = "snps,dw-apb-timer";
  785. reg = <0xff 0xffc33028 0x0 0x14>;
  786. clocks = <&dummy_clock_apb>;
  787. clock-names = "timer";
  788. clock-frequency = <62500000>;
  789. interrupts = <22>;
  790. interrupt-parent = <&intc>;
  791. status = "disabled";
  792. };
  793. timer7: timer@ffffc3303c {
  794. compatible = "snps,dw-apb-timer";
  795. reg = <0xff 0xffc3303c 0x0 0x14>;
  796. clocks = <&dummy_clock_apb>;
  797. clock-names = "timer";
  798. clock-frequency = <62500000>;
  799. interrupts = <23>;
  800. interrupt-parent = <&intc>;
  801. status = "disabled";
  802. };
  803. uart0: serial@ffe7014000 { /* Normal serial, for C910 log */
  804. compatible = "snps,dw-apb-uart";
  805. reg = <0xff 0xe7014000 0x0 0x4000>;
  806. interrupt-parent = <&intc>;
  807. interrupts = <36>;
  808. clocks = <&clk CLKGEN_UART0_SCLK>;
  809. clock-names = "baudclk";
  810. reg-shift = <2>;
  811. reg-io-width = <4>;
  812. hw-flow-control = "unsupport";
  813. status = "okay";
  814. };
  815. uart1: serial@ffe7f00000 { /* Normal serial, for C902 log */
  816. compatible = "snps,dw-apb-uart";
  817. reg = <0xff 0xe7f00000 0x0 0x4000>;
  818. interrupt-parent = <&intc>;
  819. interrupts = <37>;
  820. clocks = <&clk CLKGEN_UART1_SCLK>;
  821. clock-names = "baudclk";
  822. reg-shift = <2>;
  823. reg-io-width = <4>;
  824. hw-flow-control = "unsupport";
  825. status = "okay";
  826. };
  827. uart2: serial@ffec010000 { /* IRDA supported serial, not in 85P bit */
  828. compatible = "snps,dw-apb-uart";
  829. reg = <0xff 0xec010000 0x0 0x4000>;
  830. interrupt-parent = <&intc>;
  831. interrupts = <38>;
  832. clocks = <&clk CLKGEN_UART2_SCLK>;
  833. clock-names = "baudclk";
  834. reg-shift = <2>;
  835. reg-io-width = <4>;
  836. hw-flow-control = "unsupport";
  837. status = "disabled";
  838. };
  839. uart3: serial@ffe7f04000 { /* IRDA supported serial, not in 85P bit */
  840. compatible = "snps,dw-apb-uart";
  841. reg = <0xff 0xe7f04000 0x0 0x4000>;
  842. interrupt-parent = <&intc>;
  843. interrupts = <39>;
  844. clocks = <&clk CLKGEN_UART3_SCLK>;
  845. clock-names = "baudclk";
  846. reg-shift = <2>;
  847. reg-io-width = <4>;
  848. hw-flow-control = "unsupport";
  849. status = "disabled";
  850. };
  851. uart4: serial@fff7f08000 { /* High Speed with Flow Ctrol serial */
  852. compatible = "snps,dw-apb-uart";
  853. reg = <0xff 0xf7f08000 0x0 0x4000>;
  854. interrupt-parent = <&intc>;
  855. interrupts = <40>;
  856. clocks = <&clk CLKGEN_UART4_SCLK>;
  857. clock-names = "baudclk";
  858. reg-shift = <2>;
  859. reg-io-width = <4>;
  860. hw-flow-control = "support";
  861. status = "okay";
  862. };
  863. uart5: serial@fff7f0c000 { /* Normal serial, for external SE, not in 85P bit */
  864. compatible = "snps,dw-apb-uart";
  865. reg = <0xff 0xf7f0c000 0x0 0x4000>;
  866. interrupt-parent = <&intc>;
  867. interrupts = <41>;
  868. clocks = <&clk CLKGEN_UART5_SCLK>;
  869. clock-names = "baudclk";
  870. reg-shift = <2>;
  871. reg-io-width = <4>;
  872. hw-flow-control = "unsupport";
  873. status = "disabled";
  874. };
  875. adc: adc@0xfffff51000 {
  876. compatible = "thead,light-adc";
  877. reg = <0xff 0xfff51000 0x0 0x1000>;
  878. interrupt-parent = <&intc>;
  879. interrupts = <61>;
  880. clocks = <&dummy_clock_aonsys_clk>;
  881. clock-names = "adc";
  882. /* ADC pin is proprietary,no need to config pinctrl */
  883. status = "disabled";
  884. };
  885. spi0: spi@ffe700c000 {
  886. compatible = "snps,dw-apb-ssi";
  887. reg = <0xff 0xe700c000 0x0 0x1000>;
  888. pinctrl-names = "default";
  889. pinctrl-0 = <&pinctrl_spi0>;
  890. interrupt-parent = <&intc>;
  891. interrupts = <54>;
  892. clocks = <&dummy_clock_spi>;
  893. num-cs = <2>;
  894. #address-cells = <1>;
  895. #size-cells = <0>;
  896. };
  897. qspi0: spi@ffea000000 {
  898. compatible = "snps,dw-apb-ssi-quad";
  899. reg = <0xff 0xea000000 0x0 0x1000>;
  900. pinctrl-names = "default";
  901. pinctrl-0 = <&pinctrl_qspi0>;
  902. interrupt-parent = <&intc>;
  903. interrupts = <52>;
  904. clocks = <&dummy_clock_qspi>;
  905. #address-cells = <1>;
  906. #size-cells = <0>;
  907. };
  908. qspi1: spi@fff8000000 {
  909. compatible = "snps,dw-apb-ssi-quad";
  910. reg = <0xff 0xf8000000 0x0 0x1000>;
  911. pinctrl-names = "default";
  912. pinctrl-0 = <&pinctrl_qspi1>;
  913. interrupt-parent = <&intc>;
  914. interrupts = <53>;
  915. clocks = <&dummy_clock_spi>;
  916. #address-cells = <1>;
  917. #size-cells = <0>;
  918. };
  919. g2d: gc620@ffecc80000 {
  920. compatible = "thead,c910-gc620";
  921. reg = <0xff 0xecc80000 0x0 0x40000>;
  922. interrupt-parent = <&intc>;
  923. interrupts = <101>;
  924. interrupt-names = "irq_2d";
  925. clocks = <&vpsys_clk_gate LIGHT_VPSYS_G2D_PCLK>,
  926. <&vpsys_clk_gate LIGHT_VPSYS_G2D_ACLK>,
  927. <&vpsys_clk_gate LIGHT_VPSYS_G2D_CCLK>;
  928. clock-names = "pclk", "aclk", "cclk";
  929. status = "okay";
  930. };
  931. dsi0: dw-mipi-dsi0@ffef500000 {
  932. compatible = "thead,light-mipi-dsi", "simple-bus", "syscon";
  933. reg = <0xff 0xef500000 0x0 0x10000>;
  934. status = "disabled";
  935. dphy_0: dsi0-dphy {
  936. compatible = "thead,light-mipi-dphy";
  937. regmap = <&dsi0>;
  938. vosys-regmap = <&vosys_reg>;
  939. clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_REFCLK>,
  940. <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_CFG_CLK>,
  941. <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_PCLK>,
  942. <&clk OSC_24M>,
  943. <&clk OSC_24M>;
  944. clock-names = "refclk", "cfgclk", "pclk", "prefclk", "pcfgclk";
  945. #phy-cells = <0>;
  946. };
  947. dhost_0: dsi0-host {
  948. compatible = "verisilicon,dw-mipi-dsi";
  949. regmap = <&dsi0>;
  950. interrupt-parent = <&intc>;
  951. interrupts = <129>;
  952. clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_PCLK>,
  953. <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_PIXCLK>;
  954. clock-names = "pclk", "pixclk";
  955. phys = <&dphy_0>;
  956. phy-names = "dphy";
  957. #address-cells = <1>;
  958. #size-cells = <0>;
  959. };
  960. };
  961. dsi1: dw-mipi-dsi1@ffef510000 {
  962. compatible = "thead,light-mipi-dsi", "simple-bus", "syscon";
  963. reg = <0xff 0xef510000 0x0 0x10000>;
  964. status = "disabled";
  965. dphy_1: dsi1-dphy {
  966. compatible = "thead,light-mipi-dphy";
  967. regmap = <&dsi1>;
  968. vosys-regmap = <&vosys_reg>;
  969. clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_REFCLK>,
  970. <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_CFG_CLK>,
  971. <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_PCLK>,
  972. <&clk OSC_24M>,
  973. <&clk OSC_24M>;
  974. clock-names = "refclk", "cfgclk", "pclk", "prefclk", "pcfgclk";
  975. #phy-cells = <0>;
  976. };
  977. dhost_1: dsi1-host {
  978. compatible = "verisilicon,dw-mipi-dsi";
  979. regmap = <&dsi1>;
  980. interrupt-parent = <&intc>;
  981. interrupts = <129>;
  982. clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_PCLK>,
  983. <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_PIXCLK>;
  984. clock-names = "pclk", "pixclk";
  985. phys = <&dphy_1>;
  986. phy-names = "dphy";
  987. #address-cells = <1>;
  988. #size-cells = <0>;
  989. };
  990. };
  991. vosys_reg: vosys@ffef528000 {
  992. compatible = "thead,light-vo-subsys", "syscon";
  993. reg = <0xff 0xef528000 0x0 0x1000>;
  994. status = "okay";
  995. };
  996. hdmi_tx: dw-hdmi-tx@ffef540000 {
  997. compatible = "thead,light-hdmi-tx";
  998. reg = <0xff 0xef540000 0x0 0x40000>;
  999. interrupt-parent = <&intc>;
  1000. interrupts = <111>;
  1001. clocks = <&vosys_clk_gate LIGHT_CLKGEN_HDMI_PCLK>,
  1002. <&vosys_clk_gate LIGHT_CLKGEN_HDMI_SFR_CLK>,
  1003. <&vosys_clk_gate LIGHT_CLKGEN_HDMI_CEC_CLK>,
  1004. <&vosys_clk_gate LIGHT_CLKGEN_HDMI_PIXCLK>,
  1005. <&vosys_clk_gate LIGHT_CLKGEN_HDMI_I2S_CLK>;
  1006. clock-names = "iahb", "isfr", "cec", "pixclk", "i2s";
  1007. reg-io-width = <4>;
  1008. phy_version = <301>;
  1009. /* TODO: add phy property */
  1010. status = "disabled";
  1011. };
  1012. dpu: dc8200@ffef600000 {
  1013. compatible = "verisilicon,dc8200";
  1014. #address-cells = <1>;
  1015. #size-cells = <0>;
  1016. reg = <0xff 0xef600000 0x0 0x100>,
  1017. <0xff 0xef600800 0x0 0x2000>,
  1018. <0xff 0xef630010 0x0 0x60>;
  1019. interrupt-parent = <&intc>;
  1020. interrupts = <93>;
  1021. clocks = <&vosys_clk_gate LIGHT_CLKGEN_DPU_CCLK>,
  1022. <&vosys_clk_gate LIGHT_CLKGEN_DPU_PIXCLK0>,
  1023. <&vosys_clk_gate LIGHT_CLKGEN_DPU_PIXCLK1>,
  1024. <&vosys_clk_gate LIGHT_CLKGEN_DPU_ACLK>,
  1025. <&vosys_clk_gate LIGHT_CLKGEN_DPU_HCLK>,
  1026. <&clk DPU0_PLL_DIV_CLK>,
  1027. <&clk DPU1_PLL_DIV_CLK>,
  1028. <&clk DPU0_PLL_FOUTPOSTDIV>,
  1029. <&clk DPU1_PLL_FOUTPOSTDIV>;
  1030. clock-names = "core_clk", "pix_clk0", "pix_clk1",
  1031. "axi_clk", "cfg_clk", "pixclk0",
  1032. "pixclk1", "dpu0_pll_foutpostdiv",
  1033. "dpu1_pll_foutpostdiv";
  1034. status = "disabled";
  1035. dpu_disp0: port@0 {
  1036. reg = <0>;
  1037. disp0_out: endpoint {
  1038. remote-endpoint = <&enc0_in>;
  1039. };
  1040. };
  1041. dpu_disp1: port@1 {
  1042. reg = <1>;
  1043. disp1_out: endpoint {
  1044. remote-endpoint = <&enc1_in>;
  1045. };
  1046. };
  1047. };
  1048. watchdog0: watchdog@ffefc30000 {
  1049. compatible = "snps,dw-wdt";
  1050. reg = <0xff 0xefc30000 0x0 0x1000>;
  1051. interrupt-parent = <&intc>;
  1052. interrupts = <24>;
  1053. clocks = <&clk CLKGEN_WDT0_PCLK>;
  1054. clock-names = "tclk";
  1055. resets = <&rst LIGHT_RESET_WDT0>;
  1056. status = "okay";
  1057. };
  1058. watchdog1: watchdog@ffefc31000 {
  1059. compatible = "snps,dw-wdt";
  1060. reg = <0xff 0xefc31000 0x0 0x1000>;
  1061. interrupt-parent = <&intc>;
  1062. interrupts = <25>;
  1063. clocks = <&clk CLKGEN_WDT1_PCLK>;
  1064. clock-names = "tclk";
  1065. resets = <&rst LIGHT_RESET_WDT1>;
  1066. status = "okay";
  1067. };
  1068. rtc: rtc@fffff40000 {
  1069. compatible = "apm,xgene-rtc";
  1070. reg = <0xff 0xfff40000 0x0 0x1000>;
  1071. interrupt-parent = <&intc>;
  1072. interrupts = <74>;
  1073. clocks = <&dummy_clock_rtc>;
  1074. clock-names = "rtc";
  1075. status = "okay";
  1076. };
  1077. usb_1: usb@ffec03f000 {
  1078. compatible = "thead,dwc3";
  1079. usb3-misc-regmap = <&misc_sysreg>;
  1080. usb3-drd-regmap = <&usb3_drd>;
  1081. #address-cells = <2>;
  1082. #size-cells = <2>;
  1083. ranges;
  1084. usb: dwc3@ffe7040000 {
  1085. compatible = "snps,dwc3";
  1086. reg = <0xff 0xe7040000 0x0 0x10000>;
  1087. interrupt-parent = <&intc>;
  1088. interrupts = <68>;
  1089. clocks = <&dummy_clock_ref>, <&dummy_clock_apb>, <&dummy_clock_suspend>;
  1090. clock-names = "ref", "bus_early", "suspend";
  1091. reg-shift = <2>;
  1092. reg-io-width = <4>;
  1093. maximum-speed = "super-speed";
  1094. dr_mode = "host";
  1095. dma-mask = <0xf 0xffffffff>;
  1096. snps,usb3_lpm_capable;
  1097. snps,usb_sofitpsync;
  1098. status = "okay";
  1099. };
  1100. };
  1101. pmu: pmu {
  1102. interrupt-parent = <&cpu0_intc>;
  1103. interrupts = <17>;
  1104. compatible = "riscv,c910_pmu";
  1105. };
  1106. clk: clock-controller@ffef010000 {
  1107. compatible = "thead,light-fm-ree-clk";
  1108. reg = <0xff 0xef010000 0x0 0x1000>;
  1109. #clock-cells = <1>;
  1110. clocks = <&osc_32k>, <&osc_24m>, <&rc_24m>;
  1111. clock-names = "osc_32k", "osc_24m", "rc_24m";
  1112. status = "okay";
  1113. };
  1114. rst: reset-controller@ffef014000 {
  1115. compatible = "thead,light-reset-src","syscon";
  1116. reg = <0xff 0xef014000 0x0 0x1000>;
  1117. #reset-cells = <1>;
  1118. status = "okay";
  1119. };
  1120. sys_reg: sys_reg@ffef010100 {
  1121. compatible = "thead,light_sys_reg";
  1122. reg = <0xff 0xef010100 0x0 0x100>;
  1123. status = "okay";
  1124. };
  1125. dmac0: dmac@ffefc00000 {
  1126. compatible = "snps,axi-dma-1.01a";
  1127. reg = <0xff 0xefc00000 0x0 0x1000>;
  1128. interrupt-parent = <&intc>;
  1129. interrupts = <27>;
  1130. clocks = <&dummy_clock_apb>, <&dummy_clock_apb>;
  1131. clock-names = "core-clk", "cfgr-clk";
  1132. #dma-cells = <1>;
  1133. dma-channels = <4>;
  1134. snps,block-size = <65536 65536 65536 65536>;
  1135. snps,priority = <0 1 2 3>;
  1136. snps,dma-masters = <1>;
  1137. snps,data-width = <4>;
  1138. snps,axi-max-burst-len = <16>;
  1139. status = "okay";
  1140. };
  1141. dmac1: tee_dmac@ffff340000 {
  1142. compatible = "snps,axi-dma-1.01a";
  1143. reg = <0xff 0xff340000 0x0 0x1000>;
  1144. interrupt-parent = <&intc>;
  1145. interrupts = <150>;
  1146. clocks = <&dummy_clock_apb>, <&dummy_clock_apb>;
  1147. clock-names = "core-clk", "cfgr-clk";
  1148. #dma-cells = <1>;
  1149. dma-channels = <4>;
  1150. snps,block-size = <65536 65536 65536 65536>;
  1151. snps,priority = <0 1 2 3>;
  1152. snps,dma-masters = <1>;
  1153. snps,data-width = <4>;
  1154. snps,axi-max-burst-len = <16>;
  1155. status = "disabled";
  1156. };
  1157. dmac2: audio_dmac@0xFFC8000000 {
  1158. compatible = "snps,axi-dma-1.01a";
  1159. reg = <0xff 0xc8000000 0x0 0x2000>;
  1160. interrupt-parent = <&intc>;
  1161. interrupts = <167>;
  1162. clocks = <&dummy_clock_apb>, <&dummy_clock_apb>;
  1163. clock-names = "core-clk", "cfgr-clk";
  1164. #dma-cells = <1>;
  1165. dma-channels = <16>;
  1166. snps,block-size = <65536 65536 65536 65536
  1167. 65536 65536 65536 65536
  1168. 65536 65536 65536 65536
  1169. 65536 65536 65536 65536>;
  1170. snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
  1171. snps,dma-masters = <1>;
  1172. snps,data-width = <4>;
  1173. snps,axi-max-burst-len = <16>;
  1174. status = "okay";
  1175. };
  1176. stmmac_axi_setup: stmmac-axi-config {
  1177. snps,wr_osr_lmt = <3>;
  1178. snps,rd_osr_lmt = <3>;
  1179. snps,blen = <16 8 4 0 0 0 0>;
  1180. };
  1181. gmac0: ethernet@ffe7070000 {
  1182. compatible = "thead,light-dwmac";
  1183. reg = <0xff 0xe7070000 0x0 0x2000
  1184. 0xff 0xec00301c 0x0 0x4
  1185. 0xff 0xec003020 0x0 0x4
  1186. 0xff 0xec003000 0x0 0x1c>;
  1187. reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg";
  1188. interrupt-parent = <&intc>;
  1189. interrupts = <66>;
  1190. interrupt-names = "macirq";
  1191. clocks = <&clk CLKGEN_GMAC0_CCLK>;
  1192. clock-names = "gmac_pll_clk";
  1193. snps,pbl = <32>;
  1194. snps,fixed-burst;
  1195. snps,axi-config = <&stmmac_axi_setup>;
  1196. nvmem-cells = <&gmac0_mac_address>;
  1197. nvmem-cell-names = "mac-address";
  1198. };
  1199. gmac1: ethernet@ffe7060000 {
  1200. compatible = "thead,light-dwmac";
  1201. reg = <0xff 0xe7060000 0x0 0x2000
  1202. 0xff 0xec00401c 0x0 0x4
  1203. 0xff 0xec004020 0x0 0x4
  1204. 0xff 0xec004000 0x0 0x1c>;
  1205. reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg";
  1206. interrupt-parent = <&intc>;
  1207. interrupts = <67>;
  1208. interrupt-names = "macirq";
  1209. clocks = <&clk CLKGEN_GMAC1_CCLK>;
  1210. clock-names = "gmac_pll_clk";
  1211. snps,pbl = <32>;
  1212. snps,fixed-burst;
  1213. snps,axi-config = <&stmmac_axi_setup>;
  1214. nvmem-cells = <&gmac1_mac_address>;
  1215. nvmem-cell-names = "mac-address";
  1216. };
  1217. emmc: sdhci@ffe7080000 {
  1218. compatible = "snps,dwcmshc-sdhci";
  1219. reg = <0xff 0xe7080000 0x0 0x10000
  1220. 0xff 0xef014060 0x0 0x4>;
  1221. interrupt-parent = <&intc>;
  1222. interrupts = <62>;
  1223. interrupt-names = "sdhciirq";
  1224. clocks = <&dummy_clock_sdhci>;
  1225. clock-names = "core";
  1226. };
  1227. sdhci0: sd@ffe7090000 {
  1228. compatible = "snps,dwcmshc-sdhci";
  1229. reg = <0xff 0xe7090000 0x0 0x10000
  1230. 0xff 0xef014064 0x0 0x4>;
  1231. interrupt-parent = <&intc>;
  1232. interrupts = <64>;
  1233. interrupt-names = "sdhci0irq";
  1234. clocks = <&dummy_clock_sdhci>;
  1235. clock-names = "core";
  1236. };
  1237. sdhci1: sd@ffe70a0000 {
  1238. compatible = "snps,dwcmshc-sdhci";
  1239. reg = <0xff 0xe70a0000 0x0 0x10000
  1240. 0xff 0xef014064 0x0 0x4>;
  1241. interrupt-parent = <&intc>;
  1242. interrupts = <71>;
  1243. interrupt-names = "sdhci1irq";
  1244. clocks = <&dummy_clock_sdhci>;
  1245. clock-names = "core";
  1246. };
  1247. hwspinlock: hwspinlock@ffefc10000 {
  1248. compatible = "light,hwspinlock";
  1249. reg = <0xff 0xefc10000 0x0 0x10000>;
  1250. status = "disabled";
  1251. };
  1252. npu: vha@fffc800000 {
  1253. compatible = "img,ax3386-nna";
  1254. reg = <0xff 0xfc800000 0x0 0x100000>;
  1255. interrupt-parent = <&intc>;
  1256. interrupts = <113>;
  1257. interrupt-names = "npuirq";
  1258. power-domains = <&pd LIGHT_AON_NPU_PD>;
  1259. clocks = <&clk CLKGEN_TOP_APB_SX_PCLK>,
  1260. <&clk CLKGEN_TOP_AXI4S_ACLK>;
  1261. clock-names = "pclk", "aclk";
  1262. vha_clk_rate = <1000000000>;
  1263. ldo_vha-supply = <&npu>;
  1264. dma-mask = <0xf 0xffffffff>;
  1265. status = "disabled";
  1266. };
  1267. gpu: gpu@ffef400000 {
  1268. compatible = "img,gpu";
  1269. reg = <0xff 0xef400000 0x0 0x100000>;
  1270. interrupt-parent = <&intc>;
  1271. interrupts = <102>;
  1272. interrupt-names = "gpuirq";
  1273. vosys-regmap = <&vosys_reg>;
  1274. power-domains = <&pd LIGHT_AON_GPU_PD>;
  1275. clocks = <&vosys_clk_gate LIGHT_CLKGEN_GPU_CORE_CLK>,
  1276. <&vosys_clk_gate LIGHT_CLKGEN_GPU_CFG_ACLK>;
  1277. clock-names = "cclk", "aclk";
  1278. gpu_clk_rate = <18000000>;
  1279. dma-mask = <0xf 0xffffffff>;
  1280. status = "disabled";
  1281. };
  1282. fce: fce@fffcc50000 {
  1283. compatible = "thead,light-fce";
  1284. reg = <0xff 0xfcc50000 0x0 0x10000>;
  1285. interrupt-parent = <&intc>;
  1286. interrupts = <100>;
  1287. interrupt-names = "fceirq";
  1288. clocks = <&vpsys_clk_gate LIGHT_VPSYS_FCE_ACLK>,
  1289. <&vpsys_clk_gate LIGHT_VPSYS_FCE_PCLK>;
  1290. clock-names = "aclk", "pclk";
  1291. dma-mask = <0xf 0xffffffff>;
  1292. status = "disabled";
  1293. };
  1294. vdec: vdec@ffecc00000 {
  1295. compatible = "thead,light-vc8000d";
  1296. reg = <0xff 0xecc00000 0x0 0x8000>;
  1297. interrupt-parent = <&intc>;
  1298. interrupts = <131>;
  1299. power-domains = <&pd LIGHT_AON_VDEC_PD>;
  1300. clocks = <&vpsys_clk_gate LIGHT_VPSYS_VDEC_ACLK>,
  1301. <&vpsys_clk_gate LIGHT_VPSYS_VDEC_CCLK>,
  1302. <&vpsys_clk_gate LIGHT_VPSYS_VDEC_PCLK>;
  1303. clock-names = "aclk", "cclk", "pclk";
  1304. status = "disabled";
  1305. };
  1306. venc: venc@ffecc10000 {
  1307. compatible = "thead,light-vc8000e";
  1308. reg = <0xff 0xecc10000 0x0 0x8000>;
  1309. interrupt-parent = <&intc>;
  1310. interrupts = <133>;
  1311. power-domains = <&pd LIGHT_AON_VENC_PD>;
  1312. clocks = <&vpsys_clk_gate LIGHT_VPSYS_VENC_ACLK>,
  1313. <&vpsys_clk_gate LIGHT_VPSYS_VENC_CCLK>,
  1314. <&vpsys_clk_gate LIGHT_VPSYS_VENC_PCLK>;
  1315. clock-names = "aclk", "cclk", "pclk";
  1316. status = "disabled";
  1317. };
  1318. isp_venc_shake: shake@ffe4078000 {
  1319. compatible = "thead,light-ivs";
  1320. reg = <0xff 0xe4078000 0x0 0x1000>;
  1321. interrupt-parent = <&intc>;
  1322. interrupts = <158>;
  1323. status = "disabled";
  1324. };
  1325. vidmem: vidmem@ffecc08000 {
  1326. compatible = "thead,light-vidmem";
  1327. reg = <0xff 0xecc08000 0x0 0x1000>;
  1328. status = "disabled";
  1329. };
  1330. light_i2s: light_i2s@ffe7034000 {
  1331. #sound-dai-cells = <1>;
  1332. compatible = "light,light-i2s";
  1333. reg = <0xff 0xe7034000 0x0 0x4000>;
  1334. pinctrl-names = "default";
  1335. pinctrl-0 = <&pinctrl_audio_i2s0>;
  1336. light,mode = "i2s-master";
  1337. light,sel = "ap_i2s";
  1338. interrupt-parent = <&intc>;
  1339. interrupts = <70>;
  1340. dmas = <&dmac0 35>, <&dmac0 40>;
  1341. dma-names = "tx", "rx";
  1342. light,dma_maxburst = <4>;
  1343. #dma-cells = <1>;
  1344. clocks = <&dummy_clock_apb>;
  1345. clock-names = "pclk";
  1346. status = "disabled";
  1347. };
  1348. i2s0: audio_i2s0@0xffcb014000 {
  1349. #sound-dai-cells = <1>;
  1350. compatible = "light,light-i2s";
  1351. reg = <0xff 0xcb014000 0x0 0x1000>;
  1352. audio-pin-regmap = <&audio_ioctrl>;
  1353. audio-cpr-regmap = <&audio_cpr>;
  1354. pinctrl-names = "default";
  1355. light,mode = "i2s-master";
  1356. light,sel = "i2s0";
  1357. interrupt-parent = <&intc>;
  1358. interrupts = <174>;
  1359. dmas = <&dmac2 9>, <&dmac2 16>;
  1360. dma-names = "tx", "rx";
  1361. light,dma_maxburst = <4>;
  1362. #dma-cells = <1>;
  1363. clocks = <&dummy_clock_apb>;
  1364. clock-names = "pclk";
  1365. status = "disabled";
  1366. };
  1367. i2s1: audio_i2s1@0xffcb015000 {
  1368. #sound-dai-cells = <1>;
  1369. compatible = "light,light-i2s";
  1370. reg = <0xff 0xcb015000 0x0 0x1000>;
  1371. audio-pin-regmap = <&audio_ioctrl>;
  1372. audio-cpr-regmap = <&audio_cpr>;
  1373. pinctrl-names = "default";
  1374. light,mode = "i2s-master";
  1375. light,sel = "i2s1";
  1376. interrupt-parent = <&intc>;
  1377. interrupts = <175>;
  1378. dmas = <&dmac2 11>, <&dmac2 17>;
  1379. dma-names = "tx", "rx";
  1380. light,dma_maxburst = <4>;
  1381. #dma-cells = <1>;
  1382. clocks = <&dummy_clock_apb>;
  1383. clock-names = "pclk";
  1384. status = "disabled";
  1385. };
  1386. i2s2: audio_i2s2@0xffcb016000 {
  1387. #sound-dai-cells = <1>;
  1388. compatible = "light,light-i2s";
  1389. reg = <0xff 0xcb016000 0x0 0x1000>;
  1390. audio-pin-regmap = <&audio_ioctrl>;
  1391. audio-cpr-regmap = <&audio_cpr>;
  1392. pinctrl-names = "default";
  1393. light,mode = "i2s-master";
  1394. light,sel = "i2s2";
  1395. interrupt-parent = <&intc>;
  1396. interrupts = <176>;
  1397. dmas = <&dmac2 13>, <&dmac2 12>;
  1398. dma-names = "tx", "rx";
  1399. light,dma_maxburst = <4>;
  1400. #dma-cells = <1>;
  1401. clocks = <&dummy_clock_apb>;
  1402. clock-names = "pclk";
  1403. status = "disabled";
  1404. };
  1405. i2s3: audio_i2s3@0xffcb017000 {
  1406. #sound-dai-cells = <1>;
  1407. compatible = "light,light-i2s";
  1408. reg = <0xff 0xcb017000 0x0 0x1000>;
  1409. pinctrl-names = "default";
  1410. light,mode = "i2s-master";
  1411. light,sel = "i2s3";
  1412. interrupt-parent = <&intc>;
  1413. interrupts = <177>;
  1414. dmas = <&dmac2 14>, <&dmac2 16>;
  1415. dma-names = "tx", "rx";
  1416. light,dma_maxburst = <4>;
  1417. #dma-cells = <1>;
  1418. clocks = <&dummy_clock_apb>;
  1419. clock-names = "pclk";
  1420. status = "disabled";
  1421. };
  1422. pvt: pvt@fffff4e000 {
  1423. compatible = "moortec,mr75203";
  1424. reg = <0xff 0xfff4e000 0x0 0x80>,
  1425. <0xff 0xfff4e080 0x0 0x100>,
  1426. <0xff 0xfff4e180 0x0 0x680>,
  1427. <0xff 0xfff4e800 0x0 0x600>;
  1428. reg-names = "common", "ts", "pd", "vm";
  1429. clocks = <&dummy_clock_aonsys_clk>;
  1430. #thermal-sensor-cells = <1>;
  1431. status = "okay";
  1432. };
  1433. i2c0: i2c@ffe7f20000 {
  1434. compatible = "snps,designware-i2c";
  1435. reg = <0xff 0xe7f20000 0x0 0x4000>;
  1436. interrupt-parent = <&intc>;
  1437. interrupts = <44>;
  1438. clocks = <&dummy_clock_apb>;
  1439. clock-frequency = <100000>;
  1440. ss_hcnt = /bits/ 16 <0x104>;
  1441. ss_lcnt = /bits/ 16 <0xec>;
  1442. fs_hcnt = /bits/ 16 <0x37>;
  1443. fs_lcnt = /bits/ 16 <0x42>;
  1444. fp_hcnt = /bits/ 16 <0x14>;
  1445. fp_lcnt = /bits/ 16 <0x1a>;
  1446. hs_hcnt = /bits/ 16 <0x9>;
  1447. hs_lcnt = /bits/ 16 <0x11>;
  1448. #address-cells = <1>;
  1449. #size-cells = <0>;
  1450. };
  1451. i2c1: i2c@ffe7f24000 {
  1452. compatible = "snps,designware-i2c";
  1453. reg = <0xff 0xe7f24000 0x0 0x4000>;
  1454. interrupt-parent = <&intc>;
  1455. interrupts = <45>;
  1456. clocks = <&dummy_clock_apb>;
  1457. clock-frequency = <100000>;
  1458. ss_hcnt = /bits/ 16 <0x104>;
  1459. ss_lcnt = /bits/ 16 <0xec>;
  1460. fs_hcnt = /bits/ 16 <0x37>;
  1461. fs_lcnt = /bits/ 16 <0x42>;
  1462. fp_hcnt = /bits/ 16 <0x14>;
  1463. fp_lcnt = /bits/ 16 <0x1a>;
  1464. hs_hcnt = /bits/ 16 <0x9>;
  1465. hs_lcnt = /bits/ 16 <0x11>;
  1466. #address-cells = <1>;
  1467. #size-cells = <0>;
  1468. };
  1469. i2c2: i2c@ffec00c000{
  1470. compatible = "snps,designware-i2c";
  1471. reg = <0xff 0xec00c000 0x0 0x4000>;
  1472. interrupt-parent = <&intc>;
  1473. interrupts = <46>;
  1474. clocks = <&dummy_clock_apb>;
  1475. clock-frequency = <100000>;
  1476. ss_hcnt = /bits/ 16 <0x104>;
  1477. ss_lcnt = /bits/ 16 <0xec>;
  1478. fs_hcnt = /bits/ 16 <0x37>;
  1479. fs_lcnt = /bits/ 16 <0x42>;
  1480. fp_hcnt = /bits/ 16 <0x14>;
  1481. fp_lcnt = /bits/ 16 <0x1a>;
  1482. hs_hcnt = /bits/ 16 <0x9>;
  1483. hs_lcnt = /bits/ 16 <0x11>;
  1484. status = "disabled";
  1485. #address-cells = <1>;
  1486. #size-cells = <0>;
  1487. };
  1488. i2c3: i2c@ffec014000{
  1489. compatible = "snps,designware-i2c";
  1490. reg = <0xff 0xec014000 0x0 0x4000>;
  1491. interrupt-parent = <&intc>;
  1492. interrupts = <47>;
  1493. clocks = <&dummy_clock_apb>;
  1494. clock-frequency = <100000>;
  1495. ss_hcnt = /bits/ 16 <0x104>;
  1496. ss_lcnt = /bits/ 16 <0xec>;
  1497. fs_hcnt = /bits/ 16 <0x37>;
  1498. fs_lcnt = /bits/ 16 <0x42>;
  1499. fp_hcnt = /bits/ 16 <0x14>;
  1500. fp_lcnt = /bits/ 16 <0x1a>;
  1501. hs_hcnt = /bits/ 16 <0x9>;
  1502. hs_lcnt = /bits/ 16 <0x11>;
  1503. status = "disabled";
  1504. #address-cells = <1>;
  1505. #size-cells = <0>;
  1506. };
  1507. i2c4: i2c@ffe7f28000{
  1508. compatible = "snps,designware-i2c";
  1509. reg = <0xff 0xe7f28000 0x0 0x4000>;
  1510. interrupt-parent = <&intc>;
  1511. interrupts = <48>;
  1512. clocks = <&dummy_clock_apb>;
  1513. clock-frequency = <100000>;
  1514. ss_hcnt = /bits/ 16 <0x104>;
  1515. ss_lcnt = /bits/ 16 <0xec>;
  1516. fs_hcnt = /bits/ 16 <0x37>;
  1517. fs_lcnt = /bits/ 16 <0x42>;
  1518. fp_hcnt = /bits/ 16 <0x14>;
  1519. fp_lcnt = /bits/ 16 <0x1a>;
  1520. hs_hcnt = /bits/ 16 <0x9>;
  1521. hs_lcnt = /bits/ 16 <0x11>;
  1522. status = "disabled";
  1523. #address-cells = <1>;
  1524. #size-cells = <0>;
  1525. };
  1526. audio_i2c0: i2c@0xffcb01a000 {
  1527. compatible = "snps,designware-i2c";
  1528. reg = <0xff 0xcb01a000 0x0 0x1000>;
  1529. interrupt-parent = <&intc>;
  1530. interrupts = <182>;
  1531. clocks = <&dummy_clock_apb>;
  1532. clock-frequency = <100000>;
  1533. ss_hcnt = /bits/ 16 <0x82>;
  1534. ss_lcnt = /bits/ 16 <0x78>;
  1535. fs_hcnt = /bits/ 16 <0x37>;
  1536. fs_lcnt = /bits/ 16 <0x42>;
  1537. fp_hcnt = /bits/ 16 <0x14>;
  1538. fp_lcnt = /bits/ 16 <0x1a>;
  1539. hs_hcnt = /bits/ 16 <0x5>;
  1540. hs_lcnt = /bits/ 16 <0x15>;
  1541. #address-cells = <1>;
  1542. #size-cells = <0>;
  1543. };
  1544. audio_i2c1: i2c@0xffcb01b000 {
  1545. compatible = "snps,designware-i2c";
  1546. reg = <0xff 0xcb01b000 0x0 0x1000>;
  1547. interrupt-parent = <&intc>;
  1548. interrupts = <183>;
  1549. clocks = <&dummy_clock_apb>;
  1550. clock-frequency = <100000>;
  1551. ss_hcnt = /bits/ 16 <0x82>;
  1552. ss_lcnt = /bits/ 16 <0x78>;
  1553. fs_hcnt = /bits/ 16 <0x37>;
  1554. fs_lcnt = /bits/ 16 <0x42>;
  1555. fp_hcnt = /bits/ 16 <0x14>;
  1556. fp_lcnt = /bits/ 16 <0x1a>;
  1557. hs_hcnt = /bits/ 16 <0x5>;
  1558. hs_lcnt = /bits/ 16 <0x15>;
  1559. status = "disabled";
  1560. #address-cells = <1>;
  1561. #size-cells = <0>;
  1562. };
  1563. isp0: isp@ffe4100000 {
  1564. compatible = "thead,light-isp";
  1565. reg = <0xff 0xe4100000 0x0 0x10000>;
  1566. interrupt-parent = <&intc>;
  1567. interrupts = <117>,<118>;
  1568. clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP0_ACLK>,
  1569. <&visys_clk_gate LIGHT_CLKGEN_ISP0_HCLK>,
  1570. <&visys_clk_gate LIGHT_CLKGEN_ISP0_PIXELCLK>,
  1571. <&visys_clk_gate LIGHT_CLKGEN_ISP0_CLK>;
  1572. clock-names = "aclk", "hclk", "isp0_pclk", "cclk";
  1573. status = "disabled";
  1574. };
  1575. isp1: isp@ffe4110000 {
  1576. compatible = "thead,light-isp";
  1577. reg = <0xff 0xe4110000 0x0 0x10000>;
  1578. interrupt-parent = <&intc>;
  1579. interrupts = <120>,<121>;
  1580. clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP0_ACLK>,
  1581. <&visys_clk_gate LIGHT_CLKGEN_ISP0_HCLK>,
  1582. <&visys_clk_gate LIGHT_CLKGEN_ISP0_PIXELCLK>,
  1583. <&visys_clk_gate LIGHT_CLKGEN_ISP1_CLK>,
  1584. <&visys_clk_gate LIGHT_CLKGEN_ISP1_PIXELCLK>;
  1585. clock-names = "aclk", "hclk", "isp0_pclk", "cclk", "isp1_pclk";
  1586. status = "disabled";
  1587. };
  1588. isp_ry0: isp_ry@ffe4120000 {
  1589. compatible = "thead,light-isp_ry";
  1590. reg = <0xff 0xe4120000 0x0 0x10000>;
  1591. interrupt-parent = <&intc>;
  1592. interrupts = <123>,<124>;
  1593. clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_ACLK>,
  1594. <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_HCLK>,
  1595. <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_CCLK>;
  1596. clock-names = "aclk", "hclk", "cclk";
  1597. status = "disabled";
  1598. };
  1599. dewarp: dewarp@ffe4130000 {
  1600. compatible = "thead,light-dewarp";
  1601. reg = <0xff 0xe4130000 0x0 0x10000>;
  1602. interrupt-parent = <&intc>;
  1603. interrupts = <98>,<99>;
  1604. clocks = <&visys_clk_gate LIGHT_CLKGEN_DW200_ACLK>,
  1605. <&visys_clk_gate LIGHT_CLKGEN_DW200_HCLK>,
  1606. <&visys_clk_gate LIGHT_CLKGEN_DW200_CLK_VSE>,
  1607. <&visys_clk_gate LIGHT_CLKGEN_DW200_CLK_DWE>;
  1608. clock-names = "aclk", "hclk", "vseclk", "dweclk";
  1609. status = "disabled";
  1610. };
  1611. dec400_isp0: dec400@ffe4060000 {
  1612. compatible = "thead,dec400";
  1613. reg = <0xff 0xe4060000 0x0 0x8000>;
  1614. status = "disabled";
  1615. };
  1616. dec400_isp1: dec400@ffe4068000 {
  1617. compatible = "thead,dec400";
  1618. reg = <0xff 0xe4068000 0x0 0x8000>;
  1619. status = "disabled";
  1620. };
  1621. dec400_isp2: dec400@ffe4070000 {
  1622. compatible = "thead,dec400";
  1623. reg = <0xff 0xe4070000 0x0 0x8000>;
  1624. status = "disabled";
  1625. };
  1626. bm_visys: bm_visys@ffe4040000 {
  1627. compatible = "thead,light-bm-visys";
  1628. reg = <0xff 0xe4040000 0x0 0x1000>;
  1629. status = "disabled";
  1630. };
  1631. bm_csi0: csi@ffe4000000{ //CSI2
  1632. compatible = "thead,light-bm-csi";
  1633. reg = < 0xff 0xe4000000 0x0 0x10000>;
  1634. interrupt-parent = <&intc>;
  1635. interrupts = <128>;
  1636. dphyglueiftester = <0x180>;
  1637. sysreg_mipi_csi_ctrl = <0x140>;
  1638. clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PCLK>,
  1639. <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PIXCLK>,
  1640. <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>;
  1641. clock-names = "pclk", "pixclk", "cfg_clk";
  1642. phy_name = "CSI_4LANE";
  1643. status = "disabled";
  1644. };
  1645. csia_reg: visys-reg@ffe4020000 {
  1646. compatible = "thead,light-visys-reg", "syscon";
  1647. reg = < 0xff 0xe4020000 0x0 0x10000>;
  1648. status = "okay";
  1649. };
  1650. bm_csi1: csi@ffe4010000{ //CSI2X2_B
  1651. compatible = "thead,light-bm-csi";
  1652. reg = < 0xff 0xe4010000 0x0 0x10000>;
  1653. interrupt-parent = <&intc>;
  1654. interrupts = <126>; // 110 + 16 int_mipi_csi2x2_int0
  1655. dphyglueiftester = <0x182>; // for FPGA PHY only. ASIC not needed.
  1656. sysreg_mipi_csi_ctrl = <0x148>;
  1657. visys-regmap = <&visys_reg>;
  1658. csia-regmap = <&csia_reg>;
  1659. clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PCLK>,
  1660. <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PIXCLK>,
  1661. <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>;
  1662. clock-names = "pclk", "pixclk", "cfg_clk";
  1663. phy_name = "CSI_B";
  1664. status = "disabled";
  1665. };
  1666. bm_csi2: csi@ffe4020000{ //CSI2X2_A
  1667. compatible = "thead,light-bm-csi";
  1668. reg = < 0xff 0xe4020000 0x0 0x10000>;
  1669. interrupt-parent = <&intc>;
  1670. interrupts = <127>;
  1671. dphyglueiftester = <0x184>;
  1672. sysreg_mipi_csi_ctrl = <0x144>;
  1673. clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PCLK>,
  1674. <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PIXCLK>,
  1675. <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>;
  1676. clock-names = "pclk", "pixclk", "cfg_clk";
  1677. phy_name = "CSI_A";
  1678. status = "disabled";
  1679. };
  1680. bm_isp0: bm_isp@ffe4100000 {
  1681. compatible = "thead,light-bm-isp";
  1682. reg = <0xff 0xe4100000 0x0 0x10000>;
  1683. status = "disabled";
  1684. };
  1685. bm_isp1: bm_isp@ffe4110000 {
  1686. compatible = "thead,light-bm-isp";
  1687. reg = <0xff 0xe4110000 0x0 0x10000>;
  1688. status = "disabled";
  1689. };
  1690. //isp-ry
  1691. bm_isp2: bm_isp@ffe4120000 {
  1692. compatible = "thead,light-bm-isp";
  1693. reg = <0xff 0xe4120000 0x0 0x10000>;
  1694. status = "disabled";
  1695. };
  1696. vi_pre: vi_pre@ffe4030000 {
  1697. compatible = "thead,vi_pre";
  1698. reg = <0xff 0xe4030000 0x0 0x1000>;
  1699. interrupt-parent = <&intc>;
  1700. interrupts = <134>;
  1701. clocks = <&visys_clk_gate LIGHT_CLKGEN_VIPRE_ACLK>,
  1702. <&visys_clk_gate LIGHT_CLKGEN_VIPRE_PCLK>,
  1703. <&visys_clk_gate LIGHT_CLKGEN_VIPRE_PIXELCLK>;
  1704. clock-names ="aclk", "pclk", "pixclk";
  1705. status = "disabled";
  1706. };
  1707. video0: cam_dev@100 {
  1708. compatible = "thead,video";
  1709. status = "disabled";
  1710. };
  1711. video1: cam_dev@200 {
  1712. compatible = "thead,video";
  1713. status = "disabled";
  1714. };
  1715. video2: cam_dev@300 {
  1716. compatible = "thead,video";
  1717. status = "disabled";
  1718. };
  1719. video3: cam_dev@400 {
  1720. compatible = "thead,video";
  1721. status = "disabled";
  1722. };
  1723. video4: cam_dev@500 {
  1724. compatible = "thead,video";
  1725. status = "disabled";
  1726. };
  1727. video5: cam_dev@600 {
  1728. compatible = "thead,video";
  1729. status = "disabled";
  1730. };
  1731. video6: cam_dev@700 {
  1732. compatible = "thead,video";
  1733. status = "disabled";
  1734. };
  1735. video7: cam_dev@800 {
  1736. compatible = "thead,video";
  1737. status = "disabled";
  1738. };
  1739. video8: cam_dev@900 {
  1740. compatible = "thead,video";
  1741. status = "disabled";
  1742. };
  1743. video9: cam_dev@a00 {
  1744. compatible = "thead,video";
  1745. status = "disabled";
  1746. };
  1747. video10: cam_dev@b00 {
  1748. compatible = "thead,video";
  1749. status = "disabled";
  1750. };
  1751. video11: cam_dev@c00 {
  1752. compatible = "thead,video";
  1753. status = "disabled";
  1754. };
  1755. video12: cam_dev@d00 {
  1756. compatible = "thead,video";
  1757. status = "disabled";
  1758. };
  1759. video13: cam_dev@e00 {
  1760. compatible = "thead,video";
  1761. status = "disabled";
  1762. };
  1763. video14: cam_dev@f00 {
  1764. compatible = "thead,video";
  1765. status = "disabled";
  1766. };
  1767. video15: cam_dev@f01 {
  1768. compatible = "thead,video";
  1769. status = "disabled";
  1770. };
  1771. vvcam_flash_led0: vvcam_flash_led@0 {
  1772. compatible = "thead,light-vvcam-flash_led";
  1773. status = "disabled";
  1774. };
  1775. vvcam_sensor0: vvcam_sensor@0 {
  1776. compatible = "thead,light-vvcam-sensor";
  1777. status = "disabled";
  1778. };
  1779. vvcam_sensor1: vvcam_sensor@1 {
  1780. compatible = "thead,light-vvcam-sensor";
  1781. status = "disabled";
  1782. };
  1783. vvcam_sensor2: vvcam_sensor@2 {
  1784. compatible = "thead,light-vvcam-sensor";
  1785. status = "disabled";
  1786. };
  1787. vvcam_sensor3: vvcam_sensor@3 {
  1788. compatible = "thead,light-vvcam-sensor";
  1789. status = "disabled";
  1790. };
  1791. vvcam_sensor4: vvcam_sensor@4 {
  1792. compatible = "thead,light-vvcam-sensor";
  1793. status = "disabled";
  1794. };
  1795. vvcam_sensor5: vvcam_sensor@5 {
  1796. compatible = "thead,light-vvcam-sensor";
  1797. status = "disabled";
  1798. };
  1799. vvcam_sensor6: vvcam_sensor@6 {
  1800. compatible = "thead,light-vvcam-sensor";
  1801. status = "disabled";
  1802. };
  1803. xtensa_dsp: dsp@01{
  1804. compatible = "thead,dsp-hw-common";
  1805. reg = <0xff 0xef040000 0x0 0x001000 >; /*DSP_SYSREG(0x0000-0xFFF) */
  1806. status = "disabled";
  1807. };
  1808. xtensa_dsp0: dsp@0 {
  1809. compatible = "cdns,xrp-hw-simple";
  1810. reg = <0xff 0xe4040190 0x0 0x000010 /* host irq DSP->CPU INT Register */
  1811. 0xff 0xe40401e0 0x0 0x000010 /* device irq CPU->DSP INT Register */
  1812. 0xff 0xef048000 0x0 0x008000>; /* DSP shared memory */
  1813. dsp = <0>;
  1814. dspsys-rst-bit = <8>; /*bit# in DSP_SYSREG*/
  1815. dspsys-bus-offset = <0x90>; /*in DSP_SYSREG*/
  1816. device-irq = <0x4 1 24>; /*0xff 0xe40401e4 offset to clear DSP I]RQ, bit#, IRQ# */
  1817. device-irq-host-offset = <0x8>; /*0xff 0xe40401e8 offset to trigger DSP IRQ*/
  1818. device-irq-mode = <1>; /*level trigger*/
  1819. host-irq = <0x4 1>; /*0xff 0xe4040194 offset to clear, bit# */
  1820. host-irq-mode = <1>; /*level trigger */
  1821. host-irq-offset = <0x8>; /* 0xff 0xe4040198 offset to trigger ,device side*/
  1822. interrupt-parent = <&intc>;
  1823. interrupts = <156>;
  1824. firmware-name = "xrp0.elf";
  1825. clocks = <&dummy_clock_visys>,
  1826. <&dummy_clock_visys>;
  1827. clock-names = "pclk", "cclk";
  1828. status = "disabled";
  1829. #address-cells = <2>;
  1830. #size-cells = <1>;
  1831. ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000
  1832. 0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000
  1833. 0x00 0xfa000000 0xff 0xe0000000 0x00180000
  1834. 0x00 0xe0180000 0xff 0xe0180000 0x00040000
  1835. 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */
  1836. dsp@0 {
  1837. ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000
  1838. 0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000
  1839. 0x00 0xfa000000 0xff 0xe0000000 0x00180000
  1840. 0x00 0xe0180000 0xff 0xe0180000 0x00040000
  1841. 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */
  1842. };
  1843. };
  1844. xtensa_dsp1: dsp@1 {
  1845. compatible = "cdns,xrp-hw-simple";
  1846. reg = <0xff 0xe40401a0 0x0 0x000010 /* host irq DSP->CPU INT Register */
  1847. 0xff 0xe40401d0 0x0 0x000010 /* device irq CPU->DSP INT Register */
  1848. 0xff 0xef050000 0x0 0x008000>; /* DSP shared memory */
  1849. dsp = <1>;
  1850. dspsys-rst-bit = <8>; /*bit# in DSP_SYSREG*/
  1851. dspsys-bus-offset = <0x90>; /*in DSP_SYSREG*/
  1852. device-irq = <0x4 1 24>; /*0xff 0xe40401e4 offset to clear DSP I]RQ, bit#, IRQ# */
  1853. device-irq-host-offset = <0x8>; /*0xff 0xe40401e8 offset to trigger DSP IRQ*/
  1854. device-irq-mode = <1>; /*level trigger*/
  1855. host-irq = <0x4 1>; /*0xff 0xe4040194 offset to clear, bit# */
  1856. host-irq-mode = <1>; /*level trigger */
  1857. host-irq-offset = <0x8>; /* 0xff 0xe4040198 offset to trigger ,device side*/
  1858. interrupt-parent = <&intc>;
  1859. interrupts = <157>;
  1860. firmware-name = "xrp1.elf";
  1861. clocks = <&dummy_clock_visys>,
  1862. <&dummy_clock_visys>;
  1863. clock-names = "pclk", "cclk";
  1864. status = "disabled";
  1865. #address-cells = <2>;
  1866. #size-cells = <1>;
  1867. ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000
  1868. 0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000
  1869. 0x00 0xfa000000 0xff 0xe0000000 0x00180000
  1870. 0x00 0xe0180000 0xff 0xe01C0000 0x00040000
  1871. 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */
  1872. dsp@0 {
  1873. ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000
  1874. 0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000
  1875. 0x00 0xfa000000 0xff 0xe0000000 0x00180000
  1876. 0x00 0xe0180000 0xff 0xe01C0000 0x00040000
  1877. 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */
  1878. };
  1879. };
  1880. pmp: pmp@ffdc020000 {
  1881. compatible = "pmp";
  1882. reg = <0xff 0xdc020000 0x0 0x1000>;
  1883. };
  1884. mrvbr: mrvbr@ffff018050 {
  1885. compatible = "mrvbr";
  1886. reg = <0xff 0xff019050 0x0 0x1000>;
  1887. };
  1888. mrmr: mrmr@ffff014004 {
  1889. compatible = "mrmr";
  1890. reg = <0xff 0xff015004 0x0 0x1000>;
  1891. };
  1892. bmu: ddr-pmu@ffff008000 {
  1893. compatible = "thead,light-ddr-pmu";
  1894. reg = <0xff 0xff008000 0x0 0x800
  1895. 0xff 0xff008800 0x0 0x800
  1896. 0xff 0xff009000 0x0 0x800
  1897. 0xff 0xff009800 0x0 0x800
  1898. 0xff 0xff00a000 0x0 0x800>;
  1899. interrupt-parent = <&intc>;
  1900. interrupts = <87>;
  1901. status = "okay";
  1902. };
  1903. mbox_910t: mbox@ffffc38000 {
  1904. compatible = "thead,light-mbox";
  1905. reg = <0xff 0xffc38000 0x0 0x4000>,
  1906. <0xff 0xffc44000 0x0 0x1000>,
  1907. <0xff 0xffc4c000 0x0 0x1000>,
  1908. <0xff 0xffc54000 0x0 0x1000>;
  1909. reg-names = "local_base", "remote_icu0", "remote_icu1", "remote_icu2";
  1910. interrupt-parent = <&intc>;
  1911. interrupts = <28>;
  1912. clocks = <&dummy_clock_apb>;
  1913. clock-names = "ipg";
  1914. icu_cpu_id = <0>;
  1915. #mbox-cells = <2>;
  1916. };
  1917. trng: rng@ffff300000 {
  1918. compatible = "inside-secure,safexcel-eip76";
  1919. reg = <0xff 0xff300000 0x0 0x7d>;
  1920. interrupt-parent = <&intc>;
  1921. interrupts = <149>;
  1922. clocks = <&dummy_clock_eip>;
  1923. status = "disabled";
  1924. };
  1925. eip_28: eip-28@ffff300000 {
  1926. compatible = "xlnx,sunrise-fpga-1.0", "safexcel-eip-28";
  1927. reg = <0xff 0xff300000 0x0 0x40000>;
  1928. interrupt-parent = <&intc>;
  1929. interrupts = <144>,<145>,<146>,<147>;
  1930. clocks = <&dummy_clock_eip>;
  1931. status = "disabled";
  1932. };
  1933. khvhost: khvhost {
  1934. compatible = "thead,khv-host";
  1935. interrupt-parent = <&intc>;
  1936. interrupts = <215>; /* TEE INT SRC_7 */
  1937. };
  1938. visys_clk_gate: visys-clk-gate { /* VI_SYSREG_R */
  1939. compatible = "thead,visys-gate-controller";
  1940. visys-regmap = <&visys_reg>;
  1941. #clock-cells = <1>;
  1942. status = "okay";
  1943. };
  1944. vpsys_clk_gate: vpsys-clk-gate@ffecc30000 { /* VP_SYSREG_R */
  1945. compatible = "thead,vpsys-gate-controller";
  1946. reg = <0xff 0xecc30000 0x0 0x1000>;
  1947. #clock-cells = <1>;
  1948. status = "okay";
  1949. };
  1950. vosys_clk_gate: vosys-clk-gate@ffef528000 { /* VO_SYSREG_R */
  1951. compatible = "thead,vosys-gate-controller";
  1952. reg = <0xff 0xef528000 0x0 0x1000>;
  1953. #clock-cells = <1>;
  1954. status = "okay";
  1955. };
  1956. dspsys_clk_gate: dspsys-clk-gate {
  1957. compatible = "thead,dspsys-gate-controller";
  1958. dspsys-regmap = <&dspsys_reg>;
  1959. #clock-cells = <1>;
  1960. status = "okay";
  1961. };
  1962. };
  1963. };