light-lpi4a-ref.dts 30 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2021 Alibaba Group Holding Limited.
  4. */
  5. /dts-v1/;
  6. #include "light.dtsi"
  7. #include <dt-bindings/input/linux-event-codes.h>
  8. #include <dt-bindings/gpio/gpio.h>
  9. #include "light-vi-devices.dtsi"
  10. / {
  11. chosen {
  12. bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000";
  13. stdout-path = "serial0:115200n8";
  14. };
  15. leds {
  16. compatible = "gpio-leds";
  17. status = "disabled";
  18. led0 {
  19. label = "SYS_STATUS";
  20. gpios = <&gpio1_porta 15 0>; /* GPIO_ACTIVE_HIGH: 0 */
  21. default-state = "off";
  22. };
  23. };
  24. display-subsystem {
  25. status = "okay";
  26. };
  27. lcd0_backlight: pwm-backlight@0 {
  28. compatible = "pwm-backlight";
  29. pwms = <&pwm 0 5000000>;
  30. brightness-levels = <0 4 8 16 32 64 128 255>;
  31. default-brightness-level = <7>;
  32. };
  33. light_iopmp: iopmp {
  34. compatible = "thead,light-iopmp";
  35. /* config#1: multiple valid regions */
  36. iopmp_emmc: IOPMP_EMMC {
  37. regions = <0x000000 0x100000>,
  38. <0x100000 0x200000>;
  39. attr = <0xFFFFFFFF>;
  40. dummy_slave= <0x800000>;
  41. };
  42. /* config#2: iopmp bypass */
  43. iopmp_sdio0: IOPMP_SDIO0 {
  44. bypass_en;
  45. };
  46. /* config#3: iopmp default region set */
  47. iopmp_sdio1: IOPMP_SDIO1 {
  48. attr = <0xFFFFFFFF>;
  49. is_default_region;
  50. };
  51. iopmp_usb0: IOPMP_USB0 {
  52. attr = <0xFFFFFFFF>;
  53. is_default_region;
  54. };
  55. iopmp_ao: IOPMP_AO {
  56. is_default_region;
  57. };
  58. iopmp_aud: IOPMP_AUD {
  59. is_default_region;
  60. };
  61. iopmp_chip_dbg: IOPMP_CHIP_DBG {
  62. is_default_region;
  63. };
  64. iopmp_eip120i: IOPMP_EIP120I {
  65. is_default_region;
  66. };
  67. iopmp_eip120ii: IOPMP_EIP120II {
  68. is_default_region;
  69. };
  70. iopmp_eip120iii: IOPMP_EIP120III {
  71. is_default_region;
  72. };
  73. iopmp_isp0: IOPMP_ISP0 {
  74. is_default_region;
  75. };
  76. iopmp_isp1: IOPMP_ISP1 {
  77. is_default_region;
  78. };
  79. iopmp_dw200: IOPMP_DW200 {
  80. is_default_region;
  81. };
  82. iopmp_vipre: IOPMP_VIPRE {
  83. is_default_region;
  84. };
  85. iopmp_venc: IOPMP_VENC {
  86. is_default_region;
  87. };
  88. iopmp_vdec: IOPMP_VDEC {
  89. is_default_region;
  90. };
  91. iopmp_g2d: IOPMP_G2D {
  92. is_default_region;
  93. };
  94. iopmp_fce: IOPMP_FCE {
  95. is_default_region;
  96. };
  97. iopmp_npu: IOPMP_NPU {
  98. is_default_region;
  99. };
  100. iopmp0_dpu: IOPMP0_DPU {
  101. bypass_en;
  102. };
  103. iopmp1_dpu: IOPMP1_DPU {
  104. bypass_en;
  105. };
  106. iopmp_gpu: IOPMP_GPU {
  107. is_default_region;
  108. };
  109. iopmp_gmac1: IOPMP_GMAC1 {
  110. is_default_region;
  111. };
  112. iopmp_gmac2: IOPMP_GMAC2 {
  113. is_default_region;
  114. };
  115. iopmp_dmac: IOPMP_DMAC {
  116. is_default_region;
  117. };
  118. iopmp_tee_dmac: IOPMP_TEE_DMAC {
  119. is_default_region;
  120. };
  121. iopmp_dsp0: IOPMP_DSP0 {
  122. is_default_region;
  123. };
  124. iopmp_dsp1: IOPMP_DSP1 {
  125. is_default_region;
  126. };
  127. };
  128. mbox_910t_client1: mbox_910t_client1 {
  129. compatible = "thead,light-mbox-client";
  130. mbox-names = "902";
  131. mboxes = <&mbox_910t 1 0>;
  132. status = "disabled";
  133. };
  134. mbox_910t_client2: mbox_910t_client2 {
  135. compatible = "thead,light-mbox-client";
  136. mbox-names = "906";
  137. mboxes = <&mbox_910t 2 0>;
  138. status = "disabled";
  139. };
  140. lightsound: lightsound@1 {
  141. compatible = "simple-audio-card";
  142. simple-audio-card,name = "Light-Sound-Card";
  143. #address-cells = <1>;
  144. #size-cells = <0>;
  145. status = "disabled";
  146. };
  147. dummy_codec: dummy_codec {
  148. #sound-dai-cells = <1>;
  149. compatible = "linux,bt-sco";
  150. status = "okay";
  151. };
  152. reg_vref_1v8: regulator-adc-verf {
  153. compatible = "regulator-fixed";
  154. regulator-name = "vref-1v8";
  155. regulator-min-microvolt = <1800000>;
  156. regulator-max-microvolt = <1800000>;
  157. status = "okay";
  158. };
  159. reg_tp_pwr_en: regulator-pwr-en {
  160. compatible = "regulator-fixed";
  161. regulator-name = "regulator-pwr-en";
  162. regulator-min-microvolt = <2800000>;
  163. regulator-max-microvolt = <2800000>;
  164. gpio = <&pcal6408ahk_d 4 1>;
  165. enable-active-high;
  166. regulator-always-on;
  167. };
  168. reg_usb_hub_vdd1v2: regulator-hub-vdd12-en {
  169. compatible = "regulator-fixed";
  170. regulator-name = "regulator-hub-vdd12-en";
  171. regulator-min-microvolt = <1200000>;
  172. regulator-max-microvolt = <1200000>;
  173. gpio = <&pcal6408ahk_d 2 1>;
  174. enable-active-high;
  175. regulator-always-on;
  176. };
  177. reg_usb_hub_vcc5v: regulator-hub-vcc5v-en {
  178. compatible = "regulator-fixed";
  179. regulator-name = "regulator-hub-vcc5v-en";
  180. regulator-min-microvolt = <5000000>;
  181. regulator-max-microvolt = <5000000>;
  182. gpio = <&pcal6408ahk_d 3 1>;
  183. enable-active-high;
  184. regulator-always-on;
  185. };
  186. wcn_wifi: wireless-wlan {
  187. compatible = "wlan-platdata";
  188. clock-names = "clk_wifi";
  189. ref-clock-frequency = <24000000>;
  190. keep_wifi_power_on;
  191. pinctrl-names = "default";
  192. wifi_chip_type = "rtl8723ds";
  193. WIFI,poweren_gpio = <&pcal6408ahk_c 5 0>;
  194. status = "okay";
  195. };
  196. wcn_bt: wireless-bluetooth {
  197. compatible = "bluetooth-platdata";
  198. pinctrl-names = "default", "rts_gpio";
  199. BT,power_gpio = <&pcal6408ahk_c 6 0>;
  200. status = "okay";
  201. };
  202. gpio-keys {
  203. compatible = "gpio-keys";
  204. pinctrl-0 = <&pinctrl_volume>;
  205. pinctrl-names = "default";
  206. key-volumedown {
  207. label = "Volume Down Key";
  208. linux,code = <KEY_VOLUMEDOWN>;
  209. debounce-interval = <1>;
  210. gpios = <&gpio1_porta 19 0x1>;
  211. };
  212. key-volumeup {
  213. label = "Volume Up Key";
  214. linux,code = <KEY_VOLUMEUP>;
  215. debounce-interval = <1>;
  216. gpios = <&gpio2_porta 25 0x1>;
  217. };
  218. };
  219. aon: aon {
  220. compatible = "thead,light-aon";
  221. mbox-names = "aon";
  222. mboxes = <&mbox_910t 1 0>;
  223. status = "okay";
  224. pd: light-aon-pd {
  225. compatible = "thead,light-aon-pd";
  226. #power-domain-cells = <1>;
  227. };
  228. soc_aud_3v3_en_reg: soc_aud_3v3_en {
  229. compatible = "regulator-fixed";
  230. regulator-name = "soc_aud_3v3_en";
  231. regulator-min-microvolt = <3300000>;
  232. regulator-max-microvolt = <3300000>;
  233. gpio = <&pcal6408ahk_a 1 1>;
  234. enable-active-high;
  235. regulator-always-on;
  236. };
  237. soc_aud_1v8_en_reg: soc_aud_1v8_en {
  238. compatible = "regulator-fixed";
  239. regulator-name = "soc_aud_1v8_en";
  240. regulator-min-microvolt = <1800000>;
  241. regulator-max-microvolt = <1800000>;
  242. gpio = <&pcal6408ahk_a 0 1>;
  243. enable-active-high;
  244. regulator-always-on;
  245. };
  246. soc_vdd_3v3_en_reg: soc_vdd_3v3_en {
  247. compatible = "regulator-fixed";
  248. regulator-name = "soc_vdd_3v3_en";
  249. regulator-min-microvolt = <3300000>;
  250. regulator-max-microvolt = <3300000>;
  251. gpio = <&gpio0_porta 30 1>;
  252. enable-active-high;
  253. regulator-always-on;
  254. };
  255. soc_vdd33_lcd0_en_reg: soc_lcd0_vdd33_en {
  256. compatible = "regulator-fixed";
  257. regulator-name = "soc_lcd0_vdd33_en";
  258. regulator-min-microvolt = <3300000>;
  259. regulator-max-microvolt = <3300000>;
  260. gpio = <&pcal6408ahk_d 5 1>;
  261. enable-active-high;
  262. };
  263. soc_vdd18_lcd0_en_reg: soc_lcd0_vdd18_en {
  264. compatible = "regulator-fixed";
  265. regulator-name = "soc_lcd0_vdd18_en";
  266. regulator-min-microvolt = <1800000>;
  267. regulator-max-microvolt = <1800000>;
  268. gpio = <&pcal6408ahk_d 6 1>;
  269. enable-active-high;
  270. };
  271. soc_vdd5v_se_en_reg: soc_vdd5v_se_en {
  272. compatible = "regulator-fixed";
  273. regulator-name = "soc_vdd5v_se_en";
  274. regulator-min-microvolt = <5000000>;
  275. regulator-max-microvolt = <5000000>;
  276. gpio = <&gpio2_porta 14 1>;
  277. enable-active-high;
  278. regulator-always-on;
  279. };
  280. soc_wcn33_en_reg: soc_wcn33_en {
  281. compatible = "regulator-fixed";
  282. regulator-name = "soc_wcn33_en";
  283. regulator-min-microvolt = <3300000>;
  284. regulator-max-microvolt = <3300000>;
  285. gpio = <&gpio2_porta 29 1>;
  286. enable-active-high;
  287. regulator-always-on;
  288. };
  289. soc_vbus_en_reg: soc_vbus_en {
  290. compatible = "regulator-fixed";
  291. regulator-name = "soc_vbus_en";
  292. regulator-min-microvolt = <3300000>;
  293. regulator-max-microvolt = <3300000>;
  294. gpio = <&gpio1_porta 22 1>;
  295. enable-active-high;
  296. regulator-always-on;
  297. };
  298. soc_avdd28_rgb_reg: soc_avdd28_rgb {
  299. compatible = "regulator-fixed";
  300. regulator-name = "soc_avdd28_rgb";
  301. regulator-min-microvolt = <2800000>;
  302. regulator-max-microvolt = <2800000>;
  303. gpio = <&pcal6408ahk_b 1 1>;
  304. enable-active-high;
  305. };
  306. soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
  307. compatible = "regulator-fixed";
  308. regulator-name = "soc_dovdd18_rgb";
  309. regulator-min-microvolt = <2800000>;
  310. regulator-max-microvolt = <2800000>;
  311. gpio = <&pcal6408ahk_b 2 1>;
  312. enable-active-high;
  313. };
  314. soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
  315. compatible = "regulator-fixed";
  316. regulator-name = "soc_dvdd12_rgb";
  317. regulator-min-microvolt = <2800000>;
  318. regulator-max-microvolt = <2800000>;
  319. gpio = <&pcal6408ahk_b 0 1>;
  320. enable-active-high;
  321. };
  322. soc_avdd25_ir_reg: soc_avdd25_ir {
  323. compatible = "regulator-fixed";
  324. regulator-name = "soc_avdd25_ir";
  325. regulator-min-microvolt = <2500000>;
  326. regulator-max-microvolt = <2500000>;
  327. gpio = <&pcal6408ahk_b 5 1>;
  328. enable-active-high;
  329. };
  330. soc_dovdd18_ir_reg: soc_dovdd18_ir {
  331. compatible = "regulator-fixed";
  332. regulator-name = "soc_dovdd18_ir";
  333. regulator-min-microvolt = <1800000>;
  334. regulator-max-microvolt = <1800000>;
  335. gpio = <&pcal6408ahk_b 3 1>;
  336. enable-active-high;
  337. };
  338. soc_dvdd12_ir_reg: soc_dvdd12_ir {
  339. compatible = "regulator-fixed";
  340. regulator-name = "soc_dvdd12_ir";
  341. regulator-min-microvolt = <1200000>;
  342. regulator-max-microvolt = <1200000>;
  343. gpio = <&pcal6408ahk_b 4 1>;
  344. enable-active-high;
  345. };
  346. soc_cam2_avdd25_ir_reg: soc_cam2_avdd25_ir {
  347. compatible = "regulator-fixed";
  348. regulator-name = "soc_cam2_avdd25_ir";
  349. regulator-min-microvolt = <2500000>;
  350. regulator-max-microvolt = <2500000>;
  351. gpio = <&pcal6408ahk_b 7 1>;
  352. enable-active-high;
  353. };
  354. soc_cam2_dovdd18_ir_reg: soc_cam2_dovdd18_ir {
  355. compatible = "regulator-fixed";
  356. regulator-name = "soc_cam2_dovdd18_ir";
  357. regulator-min-microvolt = <1800000>;
  358. regulator-max-microvolt = <1800000>;
  359. gpio = <&pcal6408ahk_b 6 1>;
  360. enable-active-high;
  361. };
  362. soc_cam2_dvdd12_ir_reg: soc_cam2_dvdd12_ir {
  363. compatible = "regulator-fixed";
  364. regulator-name = "soc_cam2_dvdd12_ir";
  365. regulator-min-microvolt = <1200000>;
  366. regulator-max-microvolt = <1200000>;
  367. gpio = <&pcal6408ahk_c 0 1>;
  368. enable-active-high;
  369. };
  370. aon_reg_dialog: light-dialog-reg {
  371. compatible = "thead,light-dialog-pmic-ant";
  372. status = "okay";
  373. dvdd_cpu_reg: appcpu_dvdd {
  374. regulator-name = "appcpu_dvdd";
  375. regulator-min-microvolt = <300000>;
  376. regulator-max-microvolt = <1570000>;
  377. regulator-boot-on;
  378. regulator-always-on;
  379. };
  380. dvddm_cpu_reg: appcpu_dvddm {
  381. regulator-name = "appcpu_dvddm";
  382. regulator-min-microvolt = <300000>;
  383. regulator-max-microvolt = <1570000>;
  384. regulator-boot-on;
  385. regulator-always-on;
  386. };
  387. soc_dvdd18_aon_reg: soc_dvdd18_aon {
  388. regulator-name = "soc_dvdd18_aon";
  389. regulator-boot-on;
  390. regulator-always-on;
  391. };
  392. soc_avdd33_usb3_reg: soc_avdd33_usb3 {
  393. regulator-name = "soc_avdd33_usb3";
  394. regulator-boot-on;
  395. regulator-always-on;
  396. };
  397. soc_dvdd08_aon_reg: soc_dvdd08_aon {
  398. regulator-name = "soc_dvdd08_aon";
  399. regulator-boot-on;
  400. regulator-always-on;
  401. };
  402. soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
  403. regulator-name = "soc_dvdd08_ddr";
  404. regulator-boot-on;
  405. regulator-always-on;
  406. };
  407. soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
  408. regulator-name = "soc_vdd_ddr_1v8";
  409. regulator-boot-on;
  410. regulator-always-on;
  411. };
  412. soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
  413. regulator-name = "soc_vdd_ddr_1v1";
  414. regulator-boot-on;
  415. regulator-always-on;
  416. };
  417. soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
  418. regulator-name = "soc_vdd_ddr_0v6";
  419. regulator-boot-on;
  420. regulator-always-on;
  421. };
  422. soc_dvdd18_ap_reg: soc_dvdd18_ap {
  423. regulator-name = "soc_dvdd18_ap";
  424. regulator-boot-on;
  425. regulator-always-on;
  426. };
  427. soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
  428. regulator-name = "soc_avdd08_mipi_hdmi";
  429. regulator-boot-on;
  430. regulator-always-on;
  431. };
  432. soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
  433. regulator-name = "soc_avdd18_mipi_hdmi";
  434. regulator-boot-on;
  435. regulator-always-on;
  436. };
  437. soc_vdd33_emmc_reg: soc_vdd33_emmc {
  438. regulator-name = "soc_vdd33_emmc";
  439. regulator-boot-on;
  440. regulator-always-on;
  441. };
  442. soc_vdd18_emmc_reg: soc_vdd18_emmc {
  443. regulator-name = "soc_vdd18_emmc";
  444. regulator-boot-on;
  445. regulator-always-on;
  446. };
  447. soc_dovdd18_scan_reg: soc_dovdd18_scan {
  448. regulator-name = "soc_dovdd18_scan";
  449. regulator-min-microvolt = <900000>;
  450. regulator-max-microvolt = <3600000>;
  451. };
  452. soc_dvdd12_scan_reg: soc_dvdd12_scan {
  453. regulator-name = "soc_dvdd12_scan";
  454. regulator-min-microvolt = <900000>;
  455. regulator-max-microvolt = <3600000>;
  456. };
  457. soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
  458. regulator-name = "soc_avdd28_scan_en";
  459. regulator-min-microvolt = <900000>;
  460. regulator-max-microvolt = <3600000>;
  461. };
  462. };
  463. c910_cpufreq {
  464. compatible = "thead,light-mpw-cpufreq";
  465. status = "okay";
  466. };
  467. test: light-aon-test {
  468. compatible = "thead,light-aon-test";
  469. };
  470. };
  471. };
  472. &resmem {
  473. #address-cells = <2>;
  474. #size-cells = <2>;
  475. ranges;
  476. tee_mem: memory@1c000000 {
  477. reg = <0x0 0x1c000000 0 0x2000000>;
  478. no-map;
  479. };
  480. dsp0_mem: memory@20000000 { /**0x2000_0000~0x2040_0000 4M**/
  481. reg = <0x0 0x20000000 0x0 0x00280000 /* DSP FW code&data section 2.5M*/
  482. 0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/
  483. 0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */
  484. 0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/
  485. no-map;
  486. };
  487. dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/
  488. reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */
  489. 0x0 0x20680000 0x0 0x00001000 /* DSP communication area */
  490. 0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/
  491. 0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */
  492. no-map;
  493. };
  494. vi_mem: framebuffer@10000000 {
  495. reg = <0x0 0x10000000 0x0 0x02C00000 /* vi_mem_pool_region[0] 44 MB (default) */
  496. 0x0 0x12C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */
  497. 0x0 0x14900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */
  498. no-map;
  499. };
  500. facelib_mem: memory@17000000 {
  501. reg = <0x0 0x17000000 0 0x02000000>;
  502. no-map;
  503. };
  504. };
  505. &adc {
  506. vref-supply = <&reg_vref_1v8>;
  507. #io-channel-cells = <1>;
  508. status = "okay";
  509. };
  510. &audio_i2c0 {
  511. clock-frequency = <100000>;
  512. status = "okay";
  513. es8156_audio_codec: es8156@8 {
  514. #sound-dai-cells = <0>;
  515. compatible = "everest,es8156";
  516. reg = <0x08>;
  517. };
  518. es7210_audio_codec: es7210@40 {
  519. #sound-dai-cells = <0>;
  520. compatible = "MicArray_0";
  521. reg = <0x40>;
  522. };
  523. audio_aw87519_pa@58 {
  524. compatible = "awinic,aw87519_pa";
  525. reg = <0x58>;
  526. reset-gpio = <&pcal6408ahk_a 2 0x1>;
  527. status = "okay";
  528. };
  529. audio_aw87519_pa1@5b {
  530. compatible = "awinic,aw87519_pa";
  531. reg = <0x5b>;
  532. reset-gpio = <&pcal6408ahk_a 3 0x1>;
  533. status = "disabled";
  534. };
  535. pcal6408ahk_a: gpio@20 {
  536. compatible = "nxp,pcal9554b";
  537. reg = <0x20>;
  538. gpio-controller;
  539. #gpio-cells = <2>;
  540. };
  541. };
  542. &audio_i2c1 {
  543. clock-frequency = <100000>;
  544. status = "okay";
  545. es8156_audio_codec_1: es8156@8 {
  546. #sound-dai-cells = <0>;
  547. compatible = "everest,es8156";
  548. reg = <0x08>;
  549. status = "disabled";
  550. };
  551. es7210_audio_codec_1: es7210@40 {
  552. #sound-dai-cells = <0>;
  553. compatible = "MicArray_0";
  554. reg = <0x40>;
  555. status = "disabled";
  556. };
  557. audio_aw87519_pa2@58 {
  558. compatible = "awinic,aw87519_pa";
  559. reg = <0x58>;
  560. reset-gpio = <&pcal6408ahk_a 4 0x1>;
  561. status = "disabled";
  562. };
  563. audio_aw87519_pa3@5b {
  564. compatible = "awinic,aw87519_pa";
  565. reg = <0x5b>;
  566. reset-gpio = <&pcal6408ahk_a 5 0x1>;
  567. status = "disabled";
  568. };
  569. };
  570. &spi0 {
  571. num-cs = <1>;
  572. cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0
  573. rx-sample-delay-ns = <10>;
  574. status = "okay";
  575. spi_norflash@0 {
  576. #address-cells = <1>;
  577. #size-cells = <1>;
  578. compatible = "winbond,w25q64jwm", "jedec,spi-nor";
  579. reg = <0>;
  580. spi-max-frequency = <50000000>;
  581. w25q,fast-read;
  582. };
  583. spidev@1 {
  584. compatible = "spidev";
  585. #address-cells = <0x1>;
  586. #size-cells = <0x1>;
  587. reg = <0x1>;
  588. spi-max-frequency = <50000000>;
  589. };
  590. };
  591. &uart0 {
  592. clock-frequency = <100000000>;
  593. };
  594. &qspi0 {
  595. num-cs = <1>;
  596. cs-gpios = <&gpio2_porta 3 0>;
  597. rx-sample-dly = <4>;
  598. status = "okay";
  599. spi-flash@0 {
  600. #address-cells = <1>;
  601. #size-cells = <1>;
  602. compatible = "spi-nand";
  603. spi-max-frequency = <100000000>;
  604. spi-tx-bus-width = <4>;
  605. spi-rx-bus-width = <4>;
  606. reg = <0>;
  607. partition@0 {
  608. label = "ubi1";
  609. reg = <0x00000000 0x08000000>;
  610. };
  611. };
  612. };
  613. &qspi1 {
  614. compatible = "snps,dw-apb-ssi";
  615. num-cs = <1>;
  616. cs-gpios = <&gpio0_porta 1 0>;
  617. status = "okay";
  618. spidev@0 {
  619. compatible = "spidev";
  620. #address-cells = <0x1>;
  621. #size-cells = <0x1>;
  622. reg = <0x0>;
  623. spi-max-frequency = <50000000>;
  624. };
  625. };
  626. &gmac0 {
  627. phy-mode = "rgmii-id";
  628. rx-clk-delay = <0x00>; /* for RGMII */
  629. tx-clk-delay = <0x00>; /* for RGMII */
  630. phy-handle = <&phy_88E1111_0>;
  631. status = "okay";
  632. mdio0 {
  633. #address-cells = <1>;
  634. #size-cells = <0>;
  635. compatible = "snps,dwmac-mdio";
  636. phy_88E1111_0: ethernet-phy@0 {
  637. reg = <0x1>;
  638. };
  639. phy_88E1111_1: ethernet-phy@1 {
  640. reg = <0x2>;
  641. };
  642. };
  643. };
  644. &gmac1 {
  645. phy-mode = "rgmii-id";
  646. rx-clk-delay = <0x00>; /* for RGMII */
  647. tx-clk-delay = <0x00>; /* for RGMII */
  648. phy-handle = <&phy_88E1111_1>;
  649. status = "okay";
  650. };
  651. &emmc {
  652. max-frequency = <198000000>;
  653. non-removable;
  654. mmc-hs400-1_8v;
  655. io_fixed_1v8;
  656. is_emmc;
  657. no-sdio;
  658. no-sd;
  659. pull_up;
  660. bus-width = <8>;
  661. status = "okay";
  662. };
  663. &sdhci0 {
  664. max-frequency = <198000000>;
  665. bus-width = <4>;
  666. pull_up;
  667. wprtn_ignore;
  668. status = "okay";
  669. };
  670. &sdhci1 {
  671. max-frequency = <100000000>;
  672. bus-width = <4>;
  673. pull_up;
  674. no-sd;
  675. no-mmc;
  676. non-removable;
  677. io_fixed_1v8;
  678. post-power-on-delay-ms = <50>;
  679. wprtn_ignore;
  680. cap-sd-highspeed;
  681. keep-power-in-suspend;
  682. wakeup-source;
  683. status = "okay";
  684. };
  685. &padctrl0_apsys { /* right-pinctrl */
  686. light-evb-padctrl0 {
  687. /*
  688. * Pin Configuration Node:
  689. * Format: <pin_id mux_node config>
  690. */
  691. pinctrl_uart0: uart0grp {
  692. thead,pins = <
  693. FM_UART0_TXD 0x0 0x72
  694. FM_UART0_RXD 0x0 0x72
  695. >;
  696. };
  697. pinctrl_spi0: spi0grp {
  698. thead,pins = <
  699. FM_SPI_CSN 0x3 0x20a
  700. FM_SPI_SCLK 0x0 0x20a
  701. FM_SPI_MISO 0x0 0x23a
  702. FM_SPI_MOSI 0x0 0x23a
  703. >;
  704. };
  705. pinctrl_qspi0: qspi0grp {
  706. thead,pins = <
  707. FM_QSPI0_SCLK 0x0 0x20f
  708. FM_QSPI0_CSN0 0x3 0x20f
  709. FM_QSPI0_CSN1 0x0 0x20f
  710. FM_QSPI0_D0_MOSI 0x0 0x23f
  711. FM_QSPI0_D1_MISO 0x0 0x23f
  712. FM_QSPI0_D2_WP 0x0 0x23f
  713. FM_QSPI0_D3_HOLD 0x0 0x23f
  714. >;
  715. };
  716. pinctrl_audio_i2s0: i2s0grp {
  717. thead,pins = <
  718. FM_QSPI0_SCLK 0x2 0x208
  719. FM_QSPI0_CSN0 0x2 0x238
  720. FM_QSPI0_CSN1 0x2 0x208
  721. FM_QSPI0_D0_MOSI 0x2 0x238
  722. FM_QSPI0_D1_MISO 0x2 0x238
  723. FM_QSPI0_D2_WP 0x2 0x238
  724. FM_QSPI0_D3_HOLD 0x2 0x238
  725. >;
  726. };
  727. pinctrl_pwm: pwmgrp {
  728. thead,pins = <
  729. FM_GPIO3_2 0x1 0x208 /* pwm0 */
  730. >;
  731. };
  732. };
  733. };
  734. &padctrl1_apsys { /* left-pinctrl */
  735. light-evb-padctrl1 {
  736. /*
  737. * Pin Configuration Node:
  738. * Format: <pin_id mux_node config>
  739. */
  740. pinctrl_uart3: uart3grp {
  741. thead,pins = <
  742. FM_UART3_TXD 0x0 0x72
  743. FM_UART3_RXD 0x0 0x72
  744. >;
  745. };
  746. pinctrl_uart4: uart4grp {
  747. thead,pins = <
  748. FM_UART4_TXD 0x0 0x72
  749. FM_UART4_RXD 0x0 0x72
  750. FM_UART4_CTSN 0x0 0x72
  751. FM_UART4_RTSN 0x0 0x72
  752. >;
  753. };
  754. pinctrl_qspi1: qspi1grp {
  755. thead,pins = <
  756. FM_QSPI1_SCLK 0x0 0x20a
  757. FM_QSPI1_CSN0 0x3 0x20a
  758. FM_QSPI1_D0_MOSI 0x0 0x23a
  759. FM_QSPI1_D1_MISO 0x0 0x23a
  760. >;
  761. };
  762. pinctrl_iso7816: iso7816grp {
  763. thead,pins = <
  764. FM_QSPI1_SCLK 0x1 0x208
  765. FM_QSPI1_D0_MOSI 0x1 0x238
  766. FM_QSPI1_D1_MISO 0x1 0x238
  767. FM_QSPI1_D2_WP 0x1 0x238
  768. FM_QSPI1_D3_HOLD 0x1 0x238
  769. >;
  770. };
  771. pinctrl_volume: volume_grp {
  772. thead,pins = <
  773. FM_CLK_OUT_2 0x3 0x208
  774. >;
  775. };
  776. };
  777. };
  778. &padctrl_aosys {
  779. light-aon-padctrl {
  780. /*
  781. * Pin Configuration Node:
  782. * Format: <pin_id mux_node config>
  783. */
  784. pinctrl_audiopa1: audiopa1_grp {
  785. thead,pins = <
  786. FM_AUDIO_PA1 0x3 0x72
  787. >;
  788. };
  789. pinctrl_audiopa2: audiopa2_grp {
  790. thead,pins = <
  791. FM_AUDIO_PA2 0x0 0x72
  792. >;
  793. };
  794. };
  795. };
  796. &i2c0 {
  797. clock-frequency = <400000>;
  798. status = "okay";
  799. pcal6408ahk_b: gpio@20 {
  800. compatible = "nxp,pcal9554b";
  801. reg = <0x20>;
  802. gpio-controller;
  803. #gpio-cells = <2>;
  804. };
  805. };
  806. &i2c1 {
  807. clock-frequency = <400000>;
  808. status = "okay";
  809. pcal6408ahk_c: gpio@20 {
  810. compatible = "nxp,pcal9554b";
  811. reg = <0x20>;
  812. gpio-controller;
  813. #gpio-cells = <2>;
  814. };
  815. };
  816. &i2c2 {
  817. clock-frequency = <400000>;
  818. status = "okay";
  819. };
  820. &i2c3 {
  821. clock-frequency = <400000>;
  822. status = "okay";
  823. pcal6408ahk_d: gpio@20 {
  824. compatible = "nxp,pcal9554b";
  825. reg = <0x20>;
  826. gpio-controller;
  827. #gpio-cells = <2>;
  828. };
  829. };
  830. &i2c4 {
  831. clock-frequency = <400000>;
  832. status = "okay";
  833. };
  834. &isp0 {
  835. status = "okay";
  836. };
  837. &isp1 {
  838. status = "okay";
  839. };
  840. &isp_ry0 {
  841. status = "okay";
  842. };
  843. &dewarp {
  844. status = "okay";
  845. };
  846. &dec400_isp0 {
  847. status = "okay";
  848. };
  849. &dec400_isp1 {
  850. status = "okay";
  851. };
  852. &dec400_isp2 {
  853. status = "okay";
  854. };
  855. &bm_visys {
  856. status = "okay";
  857. };
  858. &bm_csi0 {
  859. status = "okay";
  860. };
  861. &bm_csi1 {
  862. status = "okay";
  863. };
  864. &bm_csi2 {
  865. status = "okay";
  866. };
  867. &vi_pre {
  868. //vi_pre_irq_en = <1>;
  869. status = "okay";
  870. };
  871. &xtensa_dsp {
  872. status = "okay";
  873. };
  874. &xtensa_dsp0 {
  875. status = "okay";
  876. memory-region = <&dsp0_mem>;
  877. };
  878. &xtensa_dsp1 {
  879. status = "okay";
  880. memory-region = <&dsp1_mem>;
  881. };
  882. &vvcam_sensor0 {
  883. sensor_name = "OV12870";
  884. sensor_regulators = "soc_dovdd18_rgb", "soc_dvdd12_rgb", "soc_avdd28_rgb";
  885. sensor_regulator_timing_us = <70 50 20>;
  886. sensor_pdn = <&gpio1_porta 28 0>; //powerdown pin / shutdown pin
  887. sensor_rst = <&pcal6408ahk_c 1 0>;
  888. sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready
  889. DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
  890. DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
  891. AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>;
  892. i2c_reg_width = /bits/ 8 <2>;
  893. i2c_data_width = /bits/ 8 <1>;
  894. i2c_addr = /bits/ 8 <0x10>;
  895. i2c_bus = /bits/ 8 <0>;
  896. status = "okay";
  897. };
  898. &vvcam_sensor1 {//cam1 csia
  899. sensor_name = "SC132GS";
  900. sensor_regulators = "soc_dovdd18_ir", "soc_dvdd12_ir", "soc_avdd25_ir";
  901. sensor_regulator_timing_us = <70 1000 2000>;
  902. i2c_addr = /bits/ 8 <0x30>;
  903. sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin
  904. sensor_rst = <&pcal6408ahk_c 2 0>;
  905. sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready
  906. DOVDD18_IR-supply = <&soc_dovdd18_ir_reg>;
  907. DVDD12_IR-supply = <&soc_dvdd12_ir_reg>;
  908. AVDD25_IR-supply = <&soc_avdd25_ir_reg>;
  909. i2c_reg_width = /bits/ 8 <2>;
  910. i2c_data_width = /bits/ 8 <1>;
  911. i2c_bus = /bits/ 8 <1>;
  912. status = "okay";
  913. };
  914. &vvcam_sensor2 {//cam2 csib
  915. sensor_name = "SC132GS";
  916. sensor_regulators = "soc_cam2_dovdd18_ir", "soc_cam2_dvdd12_ir", "soc_cam2_avdd25_ir";
  917. sensor_regulator_timing_us = <70 1000 2000>;
  918. i2c_addr = /bits/ 8 <0x30>;
  919. sensor_pdn = <&gpio2_porta 13 0>; //powerdown pin / shutdown pin
  920. sensor_rst = <&pcal6408ahk_c 3 0>;
  921. sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready
  922. DOVDD18_IR-supply = <&soc_cam2_dovdd18_ir_reg>;
  923. DVDD12_IR-supply = <&soc_cam2_dvdd12_ir_reg>;
  924. AVDD25_IR-supply = <&soc_cam2_avdd25_ir_reg>;
  925. i2c_reg_width = /bits/ 8 <2>;
  926. i2c_data_width = /bits/ 8 <1>;
  927. i2c_bus = /bits/ 8 <2>;
  928. status = "okay";
  929. };
  930. &video2 {
  931. vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
  932. status = "okay";
  933. channel0 {
  934. channel_id = <0>;
  935. status = "okay";
  936. sensor0 {
  937. subdev_name = "vivcam";
  938. idx = <0>;
  939. csi_idx = <0>;
  940. mode_idx = <0>;
  941. path_type = "SENSOR_VGA_RAW12_LINER";
  942. };
  943. dma {
  944. subdev_name = "vipre";
  945. idx = <0>;
  946. path_type = "VIPRE_CSI0_ISP1";
  947. };
  948. isp {
  949. subdev_name = "isp";
  950. idx = <1>;
  951. path_type = "ISP_MI_PATH_MP";
  952. output {
  953. max_width = <1920>;
  954. max_height = <1088>;
  955. bit_per_pixel = <12>;
  956. frame_count = <3>;
  957. };
  958. };
  959. };
  960. };
  961. &video3{
  962. vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
  963. status = "okay";
  964. channel0 {
  965. sensor0 {
  966. subdev_name = "vivcam";
  967. idx = <0>;
  968. csi_idx = <0>;
  969. mode_idx = <0>;
  970. path_type = "SENSOR_VGA_RAW12_LINER";
  971. };
  972. dma {
  973. subdev_name = "vipre";
  974. idx = <0>;
  975. path_type = "VIPRE_CSI0_ISP1";
  976. };
  977. isp {
  978. subdev_name = "isp";
  979. idx = <1>;
  980. path_type = "ISP_MI_PATH_MP";
  981. output {
  982. max_width = <1920>;
  983. max_height = <1088>;
  984. bit_per_pixel = <12>;
  985. frame_count = <3>;
  986. };
  987. };
  988. dw {
  989. subdev_name = "dw";
  990. idx = <0>;
  991. path_type = "DW_DWE_VSE0";
  992. dw_dst_depth = <2>;
  993. };
  994. };
  995. channel1 {
  996. sensor0 {
  997. subdev_name = "vivcam";
  998. idx = <0>;
  999. csi_idx = <0>;
  1000. mode_idx = <0>;
  1001. path_type = "SENSOR_VGA_RAW12_LINER";
  1002. };
  1003. dma {
  1004. subdev_name = "vipre";
  1005. idx = <0>;
  1006. path_type = "VIPRE_CSI0_ISP1";
  1007. };
  1008. isp {
  1009. subdev_name = "isp";
  1010. idx = <1>;
  1011. path_type = "ISP_MI_PATH_MP";
  1012. output {
  1013. max_width = <1920>;
  1014. max_height = <1088>;
  1015. bit_per_pixel = <12>;
  1016. frame_count = <3>;
  1017. };
  1018. };
  1019. dw {
  1020. subdev_name = "dw";
  1021. idx = <0>;
  1022. path_type = "DW_DWE_VSE1";
  1023. dw_dst_depth = <2>;
  1024. };
  1025. };
  1026. channel2 {
  1027. sensor0 {
  1028. subdev_name = "vivcam";
  1029. idx = <0>;
  1030. csi_idx = <0>;
  1031. mode_idx = <0>;
  1032. path_type = "SENSOR_VGA_RAW12_LINER";
  1033. };
  1034. dma {
  1035. subdev_name = "vipre";
  1036. idx = <0>;
  1037. path_type = "VIPRE_CSI0_ISP1";
  1038. };
  1039. isp {
  1040. subdev_name = "isp";
  1041. idx = <1>;
  1042. path_type = "ISP_MI_PATH_MP";
  1043. output {
  1044. max_width = <1920>;
  1045. max_height = <1088>;
  1046. bit_per_pixel = <12>;
  1047. frame_count = <3>;
  1048. };
  1049. };
  1050. dw {
  1051. subdev_name = "dw";
  1052. idx = <0>;
  1053. path_type = "DW_DWE_VSE2";
  1054. dw_dst_depth = <2>;
  1055. };
  1056. };
  1057. };
  1058. &video9{
  1059. status = "okay";
  1060. channel0 {
  1061. sensor0 {
  1062. subdev_name = "vivcam";
  1063. idx = <1>; //vivcam1 sc132gs
  1064. csi_idx = <2>; //<2>=CSI2X2_A
  1065. mode_idx = <0>;
  1066. path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
  1067. };
  1068. dsp{
  1069. output {
  1070. max_width = <1080>;
  1071. max_height = <1280>;
  1072. bit_per_pixel = <16>;
  1073. frame_count = <3>;
  1074. };
  1075. };
  1076. };
  1077. };
  1078. &video10{ // TUNINGTOOL
  1079. status = "okay";
  1080. channel0 {
  1081. sensor0 {
  1082. subdev_name = "vivcam";
  1083. idx = <0>; //<0>=vivcam0 : ov12870
  1084. csi_idx = <0>; //<0>=CSI2
  1085. mode_idx = <1>;
  1086. path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
  1087. skip_init = <1>;
  1088. };
  1089. dma {
  1090. path_type = "VIPRE_CSI0_ISP0";
  1091. };
  1092. };
  1093. };
  1094. &video15{
  1095. status = "okay";
  1096. channel0 {
  1097. status = "okay";
  1098. sensor0 {
  1099. subdev_name = "vivcam";
  1100. idx = <2>;
  1101. csi_idx = <1>; //csi_b
  1102. mode_idx = <0>;
  1103. path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
  1104. };
  1105. dma {
  1106. subdev_name = "vipre";
  1107. idx = <0>;
  1108. path_type = "VIPRE_CSI1_DDR";
  1109. };
  1110. };
  1111. };
  1112. &trng {
  1113. status = "disabled";
  1114. };
  1115. &eip_28 {
  1116. status = "okay";
  1117. };
  1118. &vdec {
  1119. status = "okay";
  1120. };
  1121. &venc {
  1122. status = "okay";
  1123. };
  1124. &isp_venc_shake {
  1125. status = "okay";
  1126. };
  1127. &vidmem {
  1128. status = "okay";
  1129. memory-region = <&vi_mem>;
  1130. };
  1131. &gpu {
  1132. status = "okay";
  1133. };
  1134. &npu {
  1135. vha_clk_rate = <1000000000>;
  1136. status = "okay";
  1137. };
  1138. &fce {
  1139. memory-region = <&facelib_mem>;
  1140. status = "okay";
  1141. };
  1142. &dpu_enc0 {
  1143. status = "okay";
  1144. ports {
  1145. /* output */
  1146. port@1 {
  1147. reg = <1>;
  1148. enc0_out: endpoint {
  1149. remote-endpoint = <&dsi0_in>;
  1150. };
  1151. };
  1152. };
  1153. };
  1154. &dpu_enc1 {
  1155. ports {
  1156. /delete-node/ port@0;
  1157. };
  1158. };
  1159. &dpu {
  1160. status = "okay";
  1161. };
  1162. &dsi0 {
  1163. status = "okay";
  1164. };
  1165. &dhost_0 {
  1166. ports {
  1167. #address-cells = <1>;
  1168. #size-cells = <0>;
  1169. port@0 {
  1170. reg = <0>;
  1171. dsi0_in: endpoint {
  1172. remote-endpoint = <&enc0_out>;
  1173. };
  1174. };
  1175. port@1 {
  1176. reg = <1>;
  1177. dsi0_out: endpoint {
  1178. remote-endpoint = <&panel0_in>;
  1179. };
  1180. };
  1181. };
  1182. panel0@0 {
  1183. compatible = "himax,hx8394";
  1184. reg = <0>;
  1185. backlight = <&lcd0_backlight>;
  1186. reset-gpio = <&pcal6408ahk_d 7 1>; /* active low */
  1187. hsvcc-supply = <&soc_vdd18_lcd0_en_reg>;
  1188. vspn3v3-supply = <&soc_vdd33_lcd0_en_reg>;
  1189. port {
  1190. panel0_in: endpoint {
  1191. remote-endpoint = <&dsi0_out>;
  1192. };
  1193. };
  1194. };
  1195. };
  1196. &disp1_out {
  1197. remote-endpoint = <&hdmi_tx_in>;
  1198. };
  1199. &hdmi_tx {
  1200. status = "okay";
  1201. port@0 {
  1202. /* input */
  1203. hdmi_tx_in: endpoint {
  1204. remote-endpoint = <&disp1_out>;
  1205. };
  1206. };
  1207. };
  1208. &lightsound {
  1209. status = "okay";
  1210. simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/
  1211. reg = <0>;
  1212. format = "i2s";
  1213. cpu {
  1214. sound-dai = <&i2s1 0>;
  1215. };
  1216. codec {
  1217. sound-dai = <&es8156_audio_codec>;
  1218. };
  1219. };
  1220. simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/
  1221. reg = <1>;
  1222. format = "i2s";
  1223. cpu {
  1224. sound-dai = <&i2s1 1>;
  1225. };
  1226. codec {
  1227. sound-dai = <&es7210_audio_codec>;
  1228. };
  1229. };
  1230. };
  1231. &light_i2s {
  1232. status = "okay";
  1233. };
  1234. &i2s0 {
  1235. status = "okay";
  1236. };
  1237. &i2s1 {
  1238. status = "okay";
  1239. dmas = <&dmac2 11>, <&dmac2 10>;
  1240. };
  1241. &i2s2 {
  1242. status = "okay";
  1243. };
  1244. &i2s3 {
  1245. status = "okay";
  1246. };
  1247. &cpus {
  1248. c910_0: cpu@0 {
  1249. operating-points = <
  1250. /* kHz uV */
  1251. 300000 650000
  1252. 800000 700000
  1253. 1500000 800000
  1254. >;
  1255. light,dvddm-operating-points = <
  1256. /* kHz uV */
  1257. 300000 800000
  1258. 800000 800000
  1259. 1500000 800000
  1260. >;
  1261. };
  1262. c910_1: cpu@1 {
  1263. operating-points = <
  1264. /* kHz uV */
  1265. 300000 650000
  1266. 800000 700000
  1267. 1500000 800000
  1268. >;
  1269. light,dvddm-operating-points = <
  1270. /* kHz uV */
  1271. 300000 800000
  1272. 800000 800000
  1273. 1500000 800000
  1274. >;
  1275. };
  1276. c910_2: cpu@2 {
  1277. operating-points = <
  1278. /* kHz uV */
  1279. 300000 650000
  1280. 800000 700000
  1281. 1500000 800000
  1282. >;
  1283. light,dvddm-operating-points = <
  1284. /* kHz uV */
  1285. 300000 800000
  1286. 800000 800000
  1287. 1500000 800000
  1288. >;
  1289. };
  1290. c910_3: cpu@3 {
  1291. operating-points = <
  1292. /* kHz uV */
  1293. 300000 650000
  1294. 800000 700000
  1295. 1500000 800000
  1296. >;
  1297. light,dvddm-operating-points = <
  1298. /* kHz uV */
  1299. 300000 800000
  1300. 800000 800000
  1301. 1500000 800000
  1302. >;
  1303. };
  1304. };