light-ant-discrete.dts 43 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2021 Alibaba Group Holding Limited.
  4. */
  5. /dts-v1/;
  6. #include "light.dtsi"
  7. #include <dt-bindings/input/linux-event-codes.h>
  8. #include <dt-bindings/gpio/gpio.h>
  9. #include "light-vi-devices.dtsi"
  10. / {
  11. model = "T-HEAD Light val board";
  12. compatible = "thead,light-val", "thead,light";
  13. memory@0 {
  14. device_type = "memory";
  15. reg = <0x0 0x00000000 0x0 0x80000000>;
  16. };
  17. chosen {
  18. bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000";
  19. stdout-path = "serial0:115200n8";
  20. };
  21. leds {
  22. compatible = "gpio-leds";
  23. status = "disabled";
  24. led0 {
  25. label = "SYS_STATUS";
  26. gpios = <&gpio1_porta 15 0>; /* GPIO_ACTIVE_HIGH: 0 */
  27. default-state = "off";
  28. };
  29. };
  30. display-subsystem {
  31. status = "okay";
  32. };
  33. lcd0_backlight: pwm-backlight@0 {
  34. compatible = "pwm-backlight";
  35. pwms = <&pwm 0 5000000>;
  36. brightness-levels = <0 4 8 16 32 64 128 255>;
  37. default-brightness-level = <7>;
  38. };
  39. light_iopmp: iopmp {
  40. compatible = "thead,light-iopmp";
  41. /* config#1: multiple valid regions */
  42. iopmp_emmc: IOPMP_EMMC {
  43. regions = <0x000000 0x100000>,
  44. <0x100000 0x200000>;
  45. attr = <0xFFFFFFFF>;
  46. dummy_slave= <0x800000>;
  47. };
  48. /* config#2: iopmp bypass */
  49. iopmp_sdio0: IOPMP_SDIO0 {
  50. bypass_en;
  51. };
  52. /* config#3: iopmp default region set */
  53. iopmp_sdio1: IOPMP_SDIO1 {
  54. attr = <0xFFFFFFFF>;
  55. is_default_region;
  56. };
  57. iopmp_usb0: IOPMP_USB0 {
  58. attr = <0xFFFFFFFF>;
  59. is_default_region;
  60. };
  61. iopmp_ao: IOPMP_AO {
  62. is_default_region;
  63. };
  64. iopmp_aud: IOPMP_AUD {
  65. is_default_region;
  66. };
  67. iopmp_chip_dbg: IOPMP_CHIP_DBG {
  68. is_default_region;
  69. };
  70. iopmp_eip120i: IOPMP_EIP120I {
  71. is_default_region;
  72. };
  73. iopmp_eip120ii: IOPMP_EIP120II {
  74. is_default_region;
  75. };
  76. iopmp_eip120iii: IOPMP_EIP120III {
  77. is_default_region;
  78. };
  79. iopmp_isp0: IOPMP_ISP0 {
  80. is_default_region;
  81. };
  82. iopmp_isp1: IOPMP_ISP1 {
  83. is_default_region;
  84. };
  85. iopmp_dw200: IOPMP_DW200 {
  86. is_default_region;
  87. };
  88. iopmp_vipre: IOPMP_VIPRE {
  89. is_default_region;
  90. };
  91. iopmp_venc: IOPMP_VENC {
  92. is_default_region;
  93. };
  94. iopmp_vdec: IOPMP_VDEC {
  95. is_default_region;
  96. };
  97. iopmp_g2d: IOPMP_G2D {
  98. is_default_region;
  99. };
  100. iopmp_fce: IOPMP_FCE {
  101. is_default_region;
  102. };
  103. iopmp_npu: IOPMP_NPU {
  104. is_default_region;
  105. };
  106. iopmp0_dpu: IOPMP0_DPU {
  107. bypass_en;
  108. };
  109. iopmp1_dpu: IOPMP1_DPU {
  110. bypass_en;
  111. };
  112. iopmp_gpu: IOPMP_GPU {
  113. is_default_region;
  114. };
  115. iopmp_gmac1: IOPMP_GMAC1 {
  116. is_default_region;
  117. };
  118. iopmp_gmac2: IOPMP_GMAC2 {
  119. is_default_region;
  120. };
  121. iopmp_dmac: IOPMP_DMAC {
  122. is_default_region;
  123. };
  124. iopmp_tee_dmac: IOPMP_TEE_DMAC {
  125. is_default_region;
  126. };
  127. iopmp_dsp0: IOPMP_DSP0 {
  128. is_default_region;
  129. };
  130. iopmp_dsp1: IOPMP_DSP1 {
  131. is_default_region;
  132. };
  133. };
  134. mbox_910t_client1: mbox_910t_client1 {
  135. compatible = "thead,light-mbox-client";
  136. mbox-names = "902";
  137. mboxes = <&mbox_910t 1 0>;
  138. status = "disabled";
  139. };
  140. mbox_910t_client2: mbox_910t_client2 {
  141. compatible = "thead,light-mbox-client";
  142. mbox-names = "906";
  143. mboxes = <&mbox_910t 2 0>;
  144. status = "disabled";
  145. };
  146. lightsound: lightsound@1 {
  147. compatible = "simple-audio-card";
  148. simple-audio-card,name = "Light-Sound-Card";
  149. #address-cells = <1>;
  150. #size-cells = <0>;
  151. status = "disabled";
  152. };
  153. dummy_codec: dummy_codec {
  154. #sound-dai-cells = <1>;
  155. compatible = "linux,bt-sco";
  156. status = "okay";
  157. };
  158. reg_vref_1v8: regulator-adc-verf {
  159. compatible = "regulator-fixed";
  160. regulator-name = "vref-1v8";
  161. regulator-min-microvolt = <1800000>;
  162. regulator-max-microvolt = <1800000>;
  163. status = "okay";
  164. };
  165. reg_tp_pwr_en: regulator-pwr-en {
  166. compatible = "regulator-fixed";
  167. regulator-name = "PWR_EN";
  168. regulator-min-microvolt = <2800000>;
  169. regulator-max-microvolt = <2800000>;
  170. gpio = <&gpio1_porta 12 1>;
  171. enable-active-high;
  172. regulator-always-on;
  173. };
  174. wcn_wifi: wireless-wlan {
  175. compatible = "wlan-platdata";
  176. clock-names = "clk_wifi";
  177. ref-clock-frequency = <24000000>;
  178. keep_wifi_power_on;
  179. pinctrl-names = "default";
  180. wifi_chip_type = "rtl8723ds";
  181. WIFI,poweren_gpio = <&gpio2_porta 29 0>;
  182. WIFI,reset_n = <&gpio2_porta 22 0>;
  183. status = "okay";
  184. };
  185. wcn_bt: wireless-bluetooth {
  186. compatible = "bluetooth-platdata";
  187. pinctrl-names = "default", "rts_gpio";
  188. BT,power_gpio = <&gpio2_porta 29 0>;
  189. status = "okay";
  190. };
  191. gpio-keys {
  192. compatible = "gpio-keys";
  193. pinctrl-0 = <&pinctrl_volume>;
  194. pinctrl-names = "default";
  195. key-volumedown {
  196. label = "Volume Down Key";
  197. linux,code = <KEY_VOLUMEDOWN>;
  198. debounce-interval = <1>;
  199. gpios = <&gpio1_porta 19 0x1>;
  200. };
  201. key-volumeup {
  202. label = "Volume Up Key";
  203. linux,code = <KEY_VOLUMEUP>;
  204. debounce-interval = <1>;
  205. gpios = <&gpio2_porta 25 0x1>;
  206. };
  207. };
  208. aon {
  209. compatible = "thead,light-aon";
  210. mbox-names = "aon";
  211. mboxes = <&mbox_910t 1 0>;
  212. status = "okay";
  213. pd: light-aon-pd {
  214. compatible = "thead,light-aon-pd";
  215. #power-domain-cells = <1>;
  216. };
  217. soc_aud_3v3_en_reg: soc_aud_3v3_en {
  218. compatible = "regulator-fixed";
  219. regulator-name = "soc_aud_3v3_en";
  220. regulator-min-microvolt = <3300000>;
  221. regulator-max-microvolt = <3300000>;
  222. gpio = <&ao_gpio_porta 7 1>;
  223. enable-active-high;
  224. regulator-always-on;
  225. };
  226. soc_aud_1v8_en_reg: soc_aud_1v8_en {
  227. compatible = "regulator-fixed";
  228. regulator-name = "soc_aud_1v8_en";
  229. regulator-min-microvolt = <1800000>;
  230. regulator-max-microvolt = <1800000>;
  231. gpio = <&ao_gpio_porta 8 1>;
  232. enable-active-high;
  233. regulator-always-on;
  234. };
  235. soc_vdd_3v3_en_reg: soc_vdd_3v3_en {
  236. compatible = "regulator-fixed";
  237. regulator-name = "soc_vdd_3v3_en";
  238. regulator-min-microvolt = <3300000>;
  239. regulator-max-microvolt = <3300000>;
  240. gpio = <&gpio0_porta 30 1>;
  241. enable-active-high;
  242. regulator-always-on;
  243. };
  244. soc_lcd0_bias_en_reg: soc_lcd0_bias_en {
  245. compatible = "regulator-fixed";
  246. regulator-name = "soc_lcd0_bias_en";
  247. regulator-min-microvolt = <5700000>;
  248. regulator-max-microvolt = <5700000>;
  249. gpio = <&gpio1_porta 10 1>;
  250. enable-active-high;
  251. };
  252. soc_vdd18_lcd0_en_reg: soc_lcd0_en {
  253. compatible = "regulator-fixed";
  254. regulator-name = "soc_lcd0_en";
  255. regulator-min-microvolt = <1800000>;
  256. regulator-max-microvolt = <1800000>;
  257. gpio = <&gpio1_porta 9 1>;
  258. enable-active-high;
  259. };
  260. soc_vdd5v_se_en_reg: soc_vdd5v_se_en {
  261. compatible = "regulator-fixed";
  262. regulator-name = "soc_vdd5v_se_en";
  263. regulator-min-microvolt = <5000000>;
  264. regulator-max-microvolt = <5000000>;
  265. gpio = <&gpio2_porta 14 1>;
  266. enable-active-high;
  267. regulator-always-on;
  268. };
  269. soc_wcn33_en_reg: soc_wcn33_en {
  270. compatible = "regulator-fixed";
  271. regulator-name = "soc_wcn33_en";
  272. regulator-min-microvolt = <3300000>;
  273. regulator-max-microvolt = <3300000>;
  274. gpio = <&gpio2_porta 29 1>;
  275. enable-active-high;
  276. regulator-always-on;
  277. };
  278. soc_vbus_en_reg: soc_vbus_en {
  279. compatible = "regulator-fixed";
  280. regulator-name = "soc_vbus_en";
  281. regulator-min-microvolt = <3300000>;
  282. regulator-max-microvolt = <3300000>;
  283. gpio = <&gpio2_porta 28 1>;
  284. enable-active-high;
  285. regulator-always-on;
  286. };
  287. soc_avdd28_rgb_reg: soc_avdd28_rgb {
  288. compatible = "regulator-fixed";
  289. regulator-name = "soc_avdd28_rgb";
  290. regulator-min-microvolt = <2800000>;
  291. regulator-max-microvolt = <2800000>;
  292. gpio = <&gpio1_porta 15 1>;
  293. enable-active-high;
  294. };
  295. soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
  296. compatible = "regulator-fixed";
  297. regulator-name = "soc_dovdd18_rgb";
  298. regulator-min-microvolt = <2800000>;
  299. regulator-max-microvolt = <2800000>;
  300. gpio = <&gpio1_porta 13 1>;
  301. enable-active-high;
  302. };
  303. soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
  304. compatible = "regulator-fixed";
  305. regulator-name = "soc_dvdd12_rgb";
  306. regulator-min-microvolt = <2800000>;
  307. regulator-max-microvolt = <2800000>;
  308. gpio = <&gpio1_porta 14 1>;
  309. enable-active-high;
  310. };
  311. soc_avdd25_ir_reg: soc_avdd25_ir {
  312. compatible = "regulator-fixed";
  313. regulator-name = "soc_avdd25_ir";
  314. regulator-min-microvolt = <2500000>;
  315. regulator-max-microvolt = <2500000>;
  316. gpio = <&gpio0_porta 28 1>;
  317. enable-active-high;
  318. };
  319. soc_dovdd18_ir_reg: soc_dovdd18_ir {
  320. compatible = "regulator-fixed";
  321. regulator-name = "soc_dovdd18_ir";
  322. regulator-min-microvolt = <1800000>;
  323. regulator-max-microvolt = <1800000>;
  324. gpio = <&gpio1_porta 13 1>;
  325. enable-active-high;
  326. };
  327. soc_dvdd12_ir_reg: soc_dvdd12_ir {
  328. compatible = "regulator-fixed";
  329. regulator-name = "soc_dvdd12_ir";
  330. regulator-min-microvolt = <1200000>;
  331. regulator-max-microvolt = <1200000>;
  332. gpio = <&gpio0_porta 29 1>;
  333. enable-active-high;
  334. };
  335. aon_reg_dialog: light-dialog-reg {
  336. compatible = "thead,light-dialog-pmic-ant";
  337. status = "okay";
  338. dvdd_cpu_reg: appcpu_dvdd {
  339. regulator-name = "appcpu_dvdd";
  340. regulator-min-microvolt = <300000>;
  341. regulator-max-microvolt = <1570000>;
  342. regulator-boot-on;
  343. regulator-always-on;
  344. };
  345. dvddm_cpu_reg: appcpu_dvddm {
  346. regulator-name = "appcpu_dvddm";
  347. regulator-min-microvolt = <300000>;
  348. regulator-max-microvolt = <1570000>;
  349. regulator-boot-on;
  350. regulator-always-on;
  351. };
  352. soc_dvdd18_aon_reg: soc_dvdd18_aon {
  353. regulator-name = "soc_dvdd18_aon";
  354. regulator-boot-on;
  355. regulator-always-on;
  356. };
  357. soc_avdd33_usb3_reg: soc_avdd33_usb3 {
  358. regulator-name = "soc_avdd33_usb3";
  359. regulator-boot-on;
  360. regulator-always-on;
  361. };
  362. soc_dvdd08_aon_reg: soc_dvdd08_aon {
  363. regulator-name = "soc_dvdd08_aon";
  364. regulator-boot-on;
  365. regulator-always-on;
  366. };
  367. soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
  368. regulator-name = "soc_dvdd08_ddr";
  369. regulator-boot-on;
  370. regulator-always-on;
  371. };
  372. soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
  373. regulator-name = "soc_vdd_ddr_1v8";
  374. regulator-boot-on;
  375. regulator-always-on;
  376. };
  377. soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
  378. regulator-name = "soc_vdd_ddr_1v1";
  379. regulator-boot-on;
  380. regulator-always-on;
  381. };
  382. soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
  383. regulator-name = "soc_vdd_ddr_0v6";
  384. regulator-boot-on;
  385. regulator-always-on;
  386. };
  387. soc_dvdd18_ap_reg: soc_dvdd18_ap {
  388. regulator-name = "soc_dvdd18_ap";
  389. regulator-boot-on;
  390. regulator-always-on;
  391. };
  392. soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
  393. regulator-name = "soc_avdd08_mipi_hdmi";
  394. regulator-boot-on;
  395. regulator-always-on;
  396. };
  397. soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
  398. regulator-name = "soc_avdd18_mipi_hdmi";
  399. regulator-boot-on;
  400. regulator-always-on;
  401. };
  402. soc_vdd33_emmc_reg: soc_vdd33_emmc {
  403. regulator-name = "soc_vdd33_emmc";
  404. regulator-boot-on;
  405. regulator-always-on;
  406. };
  407. soc_vdd18_emmc_reg: soc_vdd18_emmc {
  408. regulator-name = "soc_vdd18_emmc";
  409. regulator-boot-on;
  410. regulator-always-on;
  411. };
  412. soc_dovdd18_scan_reg: soc_dovdd18_scan {
  413. regulator-name = "soc_dovdd18_scan";
  414. };
  415. soc_dvdd12_scan_reg: soc_dvdd12_scan {
  416. regulator-name = "soc_dvdd12_scan";
  417. };
  418. soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
  419. regulator-name = "soc_avdd28_scan_en";
  420. };
  421. };
  422. c910_cpufreq {
  423. compatible = "thead,light-mpw-cpufreq";
  424. status = "okay";
  425. };
  426. test: light-aon-test {
  427. compatible = "thead,light-aon-test";
  428. };
  429. };
  430. };
  431. &resmem {
  432. #address-cells = <2>;
  433. #size-cells = <2>;
  434. ranges;
  435. tee_mem: memory@1c000000 {
  436. reg = <0x0 0x1c000000 0 0x2000000>;
  437. no-map;
  438. };
  439. dsp0_mem: memory@20000000 { /**0x2000_0000~0x2040_0000 4M**/
  440. reg = <0x0 0x20000000 0x0 0x00280000 /* DSP FW code&data section 2.5M*/
  441. 0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/
  442. 0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */
  443. 0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/
  444. no-map;
  445. };
  446. dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/
  447. reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */
  448. 0x0 0x20680000 0x0 0x00001000 /* DSP communication area */
  449. 0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/
  450. 0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */
  451. no-map;
  452. };
  453. vi_mem: framebuffer@10000000 {
  454. reg = <0x0 0x10000000 0x0 0x02C00000 /* vi_mem_pool_region[0] 44 MB (default) */
  455. 0x0 0x12C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */
  456. 0x0 0x14900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */
  457. no-map;
  458. };
  459. facelib_mem: memory@17000000 {
  460. reg = <0x0 0x17000000 0 0x02000000>;
  461. no-map;
  462. };
  463. };
  464. &adc {
  465. vref-supply = <&reg_vref_1v8>;
  466. #io-channel-cells = <1>;
  467. status = "okay";
  468. };
  469. &i2c0 {
  470. clock-frequency = <100000>;
  471. status = "okay";
  472. touch@5d {
  473. #gpio-cells = <2>;
  474. compatible = "goodix,gt911";
  475. reg = <0x5d>;
  476. interrupt-parent = <&gpio1_porta>;
  477. interrupts = <8 0>;
  478. irq-gpios = <&gpio1_porta 8 0>;
  479. reset-gpios = <&gpio1_porta 7 0>;
  480. AVDD28-supply = <&reg_tp_pwr_en>;
  481. touchscreen-size-x = <800>;
  482. touchscreen-size-y = <1280>;
  483. };
  484. };
  485. &audio_i2c0 {
  486. clock-frequency = <100000>;
  487. status = "okay";
  488. es8156_audio_codec: es8156@8 {
  489. #sound-dai-cells = <0>;
  490. compatible = "everest,es8156";
  491. reg = <0x08>;
  492. };
  493. es7210_audio_codec: es7210@40 {
  494. #sound-dai-cells = <0>;
  495. compatible = "MicArray_0";
  496. reg = <0x40>;
  497. };
  498. audio_aw87519_pa@58 {
  499. compatible = "awinic,aw87519_pa";
  500. reg = <0x58>;
  501. reset-gpio = <&ao_gpio4_porta 9 0x1>;
  502. status = "okay";
  503. };
  504. };
  505. &i2c1 {
  506. clock-frequency = <100000>;
  507. status = "okay";
  508. };
  509. &spi0 {
  510. num-cs = <1>;
  511. cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0
  512. rx-sample-delay-ns = <10>;
  513. status = "disabled";
  514. spi_norflash@0 {
  515. #address-cells = <1>;
  516. #size-cells = <1>;
  517. compatible = "winbond,w25q64jwm", "jedec,spi-nor";
  518. reg = <0>;
  519. spi-max-frequency = <50000000>;
  520. w25q,fast-read;
  521. };
  522. spidev@1 {
  523. compatible = "spidev";
  524. #address-cells = <0x1>;
  525. #size-cells = <0x1>;
  526. reg = <0x1>;
  527. spi-max-frequency = <50000000>;
  528. };
  529. };
  530. &uart0 {
  531. clock-frequency = <100000000>;
  532. };
  533. &qspi0 {
  534. num-cs = <1>;
  535. cs-gpios = <&gpio2_porta 3 0>;
  536. rx-sample-dly = <4>;
  537. status = "disabled";
  538. spi-flash@0 {
  539. #address-cells = <1>;
  540. #size-cells = <1>;
  541. compatible = "spi-nand";
  542. spi-max-frequency = <100000000>;
  543. spi-tx-bus-width = <4>;
  544. spi-rx-bus-width = <4>;
  545. reg = <0>;
  546. partition@0 {
  547. label = "ubi1";
  548. reg = <0x00000000 0x08000000>;
  549. };
  550. };
  551. };
  552. &qspi1 {
  553. compatible = "snps,dw-apb-ssi";
  554. num-cs = <1>;
  555. cs-gpios = <&gpio0_porta 1 0>;
  556. status = "okay";
  557. spidev@0 {
  558. compatible = "spidev";
  559. #address-cells = <0x1>;
  560. #size-cells = <0x1>;
  561. reg = <0x0>;
  562. spi-max-frequency = <50000000>;
  563. };
  564. };
  565. &gmac0 {
  566. phy-mode = "rgmii-id";
  567. rx-clk-delay = <0x00>; /* for RGMII */
  568. tx-clk-delay = <0x00>; /* for RGMII */
  569. phy-handle = <&phy_88E1111_0>;
  570. status = "okay";
  571. mdio0 {
  572. #address-cells = <1>;
  573. #size-cells = <0>;
  574. compatible = "snps,dwmac-mdio";
  575. phy_88E1111_0: ethernet-phy@0 {
  576. reg = <0x1>;
  577. };
  578. phy_88E1111_1: ethernet-phy@1 {
  579. reg = <0x2>;
  580. };
  581. };
  582. };
  583. &gmac1 {
  584. phy-mode = "rgmii-id";
  585. rx-clk-delay = <0x00>; /* for RGMII */
  586. tx-clk-delay = <0x00>; /* for RGMII */
  587. phy-handle = <&phy_88E1111_1>;
  588. status = "disabled";
  589. };
  590. &emmc {
  591. max-frequency = <198000000>;
  592. non-removable;
  593. mmc-hs400-1_8v;
  594. io_fixed_1v8;
  595. is_emmc;
  596. no-sdio;
  597. no-sd;
  598. pull_up;
  599. bus-width = <8>;
  600. status = "okay";
  601. };
  602. &sdhci0 {
  603. max-frequency = <198000000>;
  604. bus-width = <4>;
  605. pull_up;
  606. wprtn_ignore;
  607. status = "okay";
  608. };
  609. &sdhci1 {
  610. max-frequency = <100000000>;
  611. bus-width = <4>;
  612. pull_up;
  613. no-sd;
  614. no-mmc;
  615. non-removable;
  616. io_fixed_1v8;
  617. post-power-on-delay-ms = <50>;
  618. wprtn_ignore;
  619. cap-sd-highspeed;
  620. keep-power-in-suspend;
  621. wakeup-source;
  622. status = "okay";
  623. };
  624. &padctrl0_apsys { /* right-pinctrl */
  625. light-evb-padctrl0 {
  626. /*
  627. * Pin Configuration Node:
  628. * Format: <pin_id mux_node config>
  629. */
  630. pinctrl_uart0: uart0grp {
  631. thead,pins = <
  632. FM_UART0_TXD 0x0 0x72
  633. FM_UART0_RXD 0x0 0x72
  634. >;
  635. };
  636. pinctrl_spi0: spi0grp {
  637. thead,pins = <
  638. FM_SPI_CSN 0x3 0x20a
  639. FM_SPI_SCLK 0x0 0x20a
  640. FM_SPI_MISO 0x0 0x23a
  641. FM_SPI_MOSI 0x0 0x23a
  642. >;
  643. };
  644. pinctrl_qspi0: qspi0grp {
  645. thead,pins = <
  646. FM_QSPI0_SCLK 0x0 0x20f
  647. FM_QSPI0_CSN0 0x3 0x20f
  648. FM_QSPI0_CSN1 0x0 0x20f
  649. FM_QSPI0_D0_MOSI 0x0 0x23f
  650. FM_QSPI0_D1_MISO 0x0 0x23f
  651. FM_QSPI0_D2_WP 0x0 0x23f
  652. FM_QSPI0_D3_HOLD 0x0 0x23f
  653. >;
  654. };
  655. pinctrl_audio_i2s0: i2s0grp {
  656. thead,pins = <
  657. FM_QSPI0_SCLK 0x2 0x208
  658. FM_QSPI0_CSN0 0x2 0x238
  659. FM_QSPI0_CSN1 0x2 0x208
  660. FM_QSPI0_D0_MOSI 0x2 0x238
  661. FM_QSPI0_D1_MISO 0x2 0x238
  662. FM_QSPI0_D2_WP 0x2 0x238
  663. FM_QSPI0_D3_HOLD 0x2 0x238
  664. >;
  665. };
  666. pinctrl_pwm: pwmgrp {
  667. thead,pins = <
  668. FM_GPIO3_2 0x1 0x208 /* pwm0 */
  669. >;
  670. };
  671. };
  672. };
  673. &padctrl1_apsys { /* left-pinctrl */
  674. light-evb-padctrl1 {
  675. /*
  676. * Pin Configuration Node:
  677. * Format: <pin_id mux_node config>
  678. */
  679. pinctrl_uart3: uart3grp {
  680. thead,pins = <
  681. FM_UART3_TXD 0x0 0x72
  682. FM_UART3_RXD 0x0 0x72
  683. >;
  684. };
  685. pinctrl_uart4: uart4grp {
  686. thead,pins = <
  687. FM_UART4_TXD 0x0 0x72
  688. FM_UART4_RXD 0x0 0x72
  689. FM_UART4_CTSN 0x0 0x72
  690. FM_UART4_RTSN 0x0 0x72
  691. >;
  692. };
  693. pinctrl_qspi1: qspi1grp {
  694. thead,pins = <
  695. FM_QSPI1_SCLK 0x0 0x20a
  696. FM_QSPI1_CSN0 0x3 0x20a
  697. FM_QSPI1_D0_MOSI 0x0 0x23a
  698. FM_QSPI1_D1_MISO 0x0 0x23a
  699. >;
  700. };
  701. pinctrl_iso7816: iso7816grp {
  702. thead,pins = <
  703. FM_QSPI1_SCLK 0x1 0x208
  704. FM_QSPI1_D0_MOSI 0x1 0x238
  705. FM_QSPI1_D1_MISO 0x1 0x238
  706. FM_QSPI1_D2_WP 0x1 0x238
  707. FM_QSPI1_D3_HOLD 0x1 0x238
  708. >;
  709. };
  710. pinctrl_volume: volume_grp {
  711. thead,pins = <
  712. FM_CLK_OUT_2 0x3 0x208
  713. >;
  714. };
  715. };
  716. };
  717. &padctrl_aosys {
  718. light-aon-padctrl {
  719. /*
  720. * Pin Configuration Node:
  721. * Format: <pin_id mux_node config>
  722. */
  723. pinctrl_audiopa1: audiopa1_grp {
  724. thead,pins = <
  725. FM_AUDIO_PA1 0x3 0x72
  726. >;
  727. };
  728. pinctrl_audiopa2: audiopa2_grp {
  729. thead,pins = <
  730. FM_AUDIO_PA2 0x0 0x72
  731. >;
  732. };
  733. };
  734. };
  735. &i2c0 {
  736. clock-frequency = <400000>;
  737. status = "okay";
  738. };
  739. &i2c1 {
  740. clock-frequency = <400000>;
  741. status = "okay";
  742. };
  743. &i2c2 {
  744. clock-frequency = <400000>;
  745. status = "okay";
  746. };
  747. &i2c3 {
  748. clock-frequency = <400000>;
  749. status = "okay";
  750. };
  751. &i2c4 {
  752. clock-frequency = <400000>;
  753. status = "okay";
  754. };
  755. &isp0 {
  756. status = "okay";
  757. };
  758. &isp1 {
  759. status = "okay";
  760. };
  761. &isp_ry0 {
  762. status = "okay";
  763. };
  764. &dewarp {
  765. status = "okay";
  766. };
  767. &dec400_isp0 {
  768. status = "okay";
  769. };
  770. &dec400_isp1 {
  771. status = "okay";
  772. };
  773. &dec400_isp2 {
  774. status = "okay";
  775. };
  776. &bm_visys {
  777. status = "okay";
  778. };
  779. &bm_csi0 {
  780. status = "okay";
  781. };
  782. &bm_csi1 {
  783. status = "okay";
  784. };
  785. &bm_csi2 {
  786. status = "okay";
  787. };
  788. &vi_pre {
  789. //vi_pre_irq_en = <1>;
  790. status = "okay";
  791. };
  792. &xtensa_dsp {
  793. status = "okay";
  794. };
  795. &xtensa_dsp0 {
  796. status = "okay";
  797. memory-region = <&dsp0_mem>;
  798. };
  799. &xtensa_dsp1 {
  800. status = "okay";
  801. memory-region = <&dsp1_mem>;
  802. };
  803. &vvcam_flash_led0{
  804. flash_led_name = "aw36413_aw36515";
  805. floodlight_i2c_bus = /bits/ 8 <0>;
  806. floodlight_en_pin = <&gpio1_porta 26 0>;
  807. projection_i2c_bus = /bits/ 8 <1>;
  808. flash_led_touch_pin = <&gpio1_porta 27 0>; //flash led touch pin
  809. io-channels = <&adc 2>;
  810. io-channel-names = "projection_adc";
  811. status = "okay";
  812. };
  813. &vvcam_sensor0 {
  814. sensor_name = "SC2310";
  815. sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB";
  816. sensor_regulator_timing_us = <70 50 20>;
  817. sensor_pdn = <&gpio1_porta 21 0>; //powerdown pin / shutdown pin
  818. sensor_rst = <&gpio1_porta 16 0>;
  819. sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready
  820. DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
  821. DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
  822. AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>;
  823. i2c_reg_width = /bits/ 8 <2>;
  824. i2c_data_width = /bits/ 8 <1>;
  825. i2c_addr = /bits/ 8 <0x30>;
  826. i2c_bus = /bits/ 8 <3>;
  827. status = "okay";
  828. };
  829. &vvcam_sensor1 {
  830. sensor_name = "SC132GS";
  831. sensor_regulators = "DOVDD18_IR", "DVDD12_IR", "AVDD25_IR";
  832. sensor_regulator_timing_us = <70 1000 2000>;
  833. i2c_addr = /bits/ 8 <0x31>;
  834. sensor_pdn = <&gpio1_porta 28 0>; //powerdown pin / shutdown pin
  835. sensor_rst = <&gpio1_porta 24 0>;
  836. sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready
  837. DOVDD18_IR-supply = <&soc_dovdd18_ir_reg>;
  838. DVDD12_IR-supply = <&soc_dvdd12_ir_reg>;
  839. AVDD25_IR-supply = <&soc_avdd25_ir_reg>;
  840. i2c_reg_width = /bits/ 8 <2>;
  841. i2c_data_width = /bits/ 8 <1>;
  842. i2c_bus = /bits/ 8 <2>;
  843. status = "okay";
  844. };
  845. &vvcam_sensor2 {
  846. sensor_name = "GC5035";
  847. sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN";
  848. sensor_regulator_timing_us = <100 50 0>;
  849. sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin
  850. sensor_rst = <&gpio1_porta 29 0>;
  851. sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready
  852. DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>;
  853. DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>;
  854. AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>;
  855. i2c_addr = /bits/ 8 <0x37>;
  856. i2c_bus = /bits/ 8 <4>;
  857. i2c_reg_width = /bits/ 8 <1>;
  858. i2c_data_width = /bits/ 8 <1>;
  859. status = "okay";
  860. };
  861. &vvcam_sensor3 {
  862. sensor_name = "GC02M1B";
  863. sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN";
  864. sensor_regulator_timing_us = <100 50 0>;
  865. sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin
  866. sensor_rst = <&gpio1_porta 29 0>;
  867. sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready
  868. DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>;
  869. DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>;
  870. AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>;
  871. i2c_addr = /bits/ 8 <0x37>;
  872. i2c_bus = /bits/ 8 <4>;
  873. i2c_reg_width = /bits/ 8 <1>;
  874. i2c_data_width = /bits/ 8 <1>;
  875. status = "okay";
  876. };
  877. &video0{
  878. vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2]
  879. channel0 {
  880. sensor0 {
  881. subdev_name = "vivcam";
  882. idx = <2>; //<2>=vivcam2 : gc5035
  883. csi_idx = <1>; //<1>=CSI2X2_B
  884. mode_idx = <3>;
  885. path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
  886. };
  887. sensor1 {
  888. subdev_name = "vivcam";
  889. idx = <3>; //<3>=vivcam3 : gc02m1b
  890. csi_idx = <1>; //<1>=CSI2X2_B
  891. mode_idx = <0>;
  892. path_type = "SENSOR_1600x1200_RAW10_LINER";
  893. };
  894. isp {
  895. subdev_name = "isp";
  896. idx = <0>;
  897. path_type = "ISP_MI_PATH_MP";
  898. output {
  899. max_width = <1920>;
  900. max_height = <1088>;
  901. bit_per_pixel = <12>;
  902. frame_count = <3>;
  903. };
  904. };
  905. };
  906. channel1 {
  907. sensor0 {
  908. subdev_name = "vivcam";
  909. idx = <2>; //<2>=vivcam2 : gc5035
  910. csi_idx = <1>; //<1>=CSI2X2_B
  911. mode_idx = <3>;
  912. path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
  913. };
  914. sensor1 {
  915. subdev_name = "vivcam";
  916. idx = <3>; //<3>=vivcam3 : gc02m1b
  917. csi_idx = <1>; //<1>=CSI2X2_B
  918. mode_idx = <0>;
  919. path_type = "SENSOR_1600x1200_RAW10_LINER";
  920. };
  921. isp {
  922. subdev_name = "isp";
  923. idx = <0>;
  924. path_type = "ISP_MI_PATH_SP";
  925. output {
  926. max_width = <1920>;
  927. max_height = <1088>;
  928. bit_per_pixel = <12>;
  929. frame_count = <3>;
  930. };
  931. };
  932. };
  933. channel2 {
  934. sensor0 {
  935. subdev_name = "vivcam";
  936. idx = <2>; //<2>=vivcam2 : gc5035
  937. csi_idx = <1>; //<1>=CSI2X2_B
  938. mode_idx = <3>;
  939. path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
  940. };
  941. sensor1 {
  942. subdev_name = "vivcam";
  943. idx = <3>; //<3>=vivcam3 : gc02m1b
  944. csi_idx = <1>; //<1>=CSI2X2_B
  945. mode_idx = <0>;
  946. path_type = "SENSOR_1600x1200_RAW10_LINER";
  947. };
  948. isp {
  949. subdev_name = "isp";
  950. idx = <0>;
  951. path_type = "ISP_MI_PATH_SP2_BP";
  952. output {
  953. max_width = <1920>;
  954. max_height = <1088>;
  955. bit_per_pixel = <12>;
  956. frame_count = <3>;
  957. };
  958. };
  959. };
  960. };
  961. &video1{
  962. vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2]
  963. channel0 {
  964. sensor0 {
  965. subdev_name = "vivcam";
  966. idx = <2>; //<2>=vivcam2 : gc5035
  967. csi_idx = <1>; //<1>=CSI2X2_B
  968. mode_idx = <3>;
  969. path_type = "SENSOR_1296x972_RAW10_LINER";
  970. };
  971. sensor1 {
  972. subdev_name = "vivcam";
  973. idx = <3>; //<3>=vivcam3 : gc02m1b
  974. csi_idx = <1>; //<1>=CSI2X2_B
  975. mode_idx = <0>;
  976. path_type = "SENSOR_1600x1200_RAW10_LINER";
  977. };
  978. isp {
  979. subdev_name = "isp";
  980. idx = <0>;
  981. path_type = "ISP_MI_PATH_MP";
  982. output {
  983. max_width = <1920>;
  984. max_height = <1088>;
  985. bit_per_pixel = <12>;
  986. frame_count = <3>;
  987. };
  988. };
  989. dw {
  990. subdev_name = "dw";
  991. idx = <0>;
  992. path_type = "DW_DWE_VSE0";
  993. dw_dst_depth = <2>;
  994. };
  995. };
  996. channel1 {
  997. sensor0 {
  998. subdev_name = "vivcam";
  999. idx = <2>; //<2>=vivcam2 : gc5035
  1000. csi_idx = <1>; //<1>=CSI2X2_B
  1001. mode_idx = <3>;
  1002. path_type = "SENSOR_1296x972_RAW10_LINER";
  1003. };
  1004. sensor1 {
  1005. subdev_name = "vivcam";
  1006. idx = <3>; //<3>=vivcam3 : gc02m1b
  1007. csi_idx = <1>; //<1>=CSI2X2_B
  1008. mode_idx = <0>;
  1009. path_type = "SENSOR_1600x1200_RAW10_LINER";
  1010. };
  1011. isp {
  1012. subdev_name = "isp";
  1013. idx = <0>;
  1014. path_type = "ISP_MI_PATH_MP";
  1015. output {
  1016. max_width = <1920>;
  1017. max_height = <1088>;
  1018. bit_per_pixel = <12>;
  1019. frame_count = <3>;
  1020. };
  1021. };
  1022. dw {
  1023. subdev_name = "dw";
  1024. idx = <0>;
  1025. path_type = "DW_DWE_VSE1";
  1026. dw_dst_depth = <2>;
  1027. };
  1028. };
  1029. channel2 {
  1030. sensor0 {
  1031. subdev_name = "vivcam";
  1032. idx = <2>; //<2>=vivcam2 : gc5035
  1033. csi_idx = <1>; //<1>=CSI2X2_B
  1034. mode_idx = <3>;
  1035. path_type = "SENSOR_1296x972_RAW10_LINER";
  1036. };
  1037. sensor1 {
  1038. subdev_name = "vivcam";
  1039. idx = <3>; //<3>=vivcam3 : gc02m1b
  1040. csi_idx = <1>; //<1>=CSI2X2_B
  1041. mode_idx = <0>;
  1042. path_type = "SENSOR_1600x1200_RAW10_LINER";
  1043. };
  1044. isp {
  1045. subdev_name = "isp";
  1046. idx = <0>;
  1047. path_type = "ISP_MI_PATH_MP";
  1048. output {
  1049. max_width = <1920>;
  1050. max_height = <1088>;
  1051. bit_per_pixel = <12>;
  1052. frame_count = <3>;
  1053. };
  1054. };
  1055. dw {
  1056. subdev_name = "dw";
  1057. idx = <0>;
  1058. path_type = "DW_DWE_VSE2";
  1059. dw_dst_depth = <2>;
  1060. };
  1061. };
  1062. };
  1063. &video2{
  1064. vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
  1065. channel0 {
  1066. sensor0 {
  1067. subdev_name = "vivcam";
  1068. idx = <0>; //vivcam0 sc2310
  1069. csi_idx = <0>; //<0>=CSI2
  1070. mode_idx = <1>;
  1071. path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
  1072. };
  1073. isp {
  1074. subdev_name = "isp";
  1075. idx = <1>;
  1076. path_type = "ISP_MI_PATH_MP";
  1077. output {
  1078. max_width = <1920>;
  1079. max_height = <1088>;
  1080. bit_per_pixel = <12>;
  1081. frame_count = <3>;
  1082. };
  1083. };
  1084. };
  1085. channel1 {
  1086. sensor0 {
  1087. subdev_name = "vivcam";
  1088. idx = <0>; //vivcam0 sc2310
  1089. csi_idx = <0>; //<0>=CSI2
  1090. mode_idx = <1>;
  1091. path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
  1092. };
  1093. isp {
  1094. subdev_name = "isp";
  1095. idx = <1>;
  1096. path_type = "ISP_MI_PATH_SP";
  1097. output {
  1098. max_width = <1920>;
  1099. max_height = <1088>;
  1100. bit_per_pixel = <12>;
  1101. frame_count = <3>;
  1102. };
  1103. };
  1104. };
  1105. channel2 {
  1106. sensor0 {
  1107. subdev_name = "vivcam";
  1108. idx = <0>; //vivcam0 sc2310
  1109. csi_idx = <0>; //<0>=CSI2
  1110. mode_idx = <1>;
  1111. path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
  1112. };
  1113. isp {
  1114. subdev_name = "isp";
  1115. idx = <1>;
  1116. path_type = "ISP_MI_PATH_SP2_BP";
  1117. output {
  1118. max_width = <1920>;
  1119. max_height = <1088>;
  1120. bit_per_pixel = <12>;
  1121. frame_count = <3>;
  1122. };
  1123. };
  1124. };
  1125. };
  1126. &video3{
  1127. vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
  1128. channel0 {
  1129. sensor0 {
  1130. subdev_name = "vivcam";
  1131. idx = <0>; //vivcam0 sc2310
  1132. csi_idx = <0>; //<0>=CSI2
  1133. mode_idx = <1>;
  1134. path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
  1135. };
  1136. isp {
  1137. subdev_name = "isp";
  1138. idx = <1>;
  1139. path_type = "ISP_MI_PATH_MP";
  1140. output {
  1141. max_width = <1920>;
  1142. max_height = <1088>;
  1143. bit_per_pixel = <12>;
  1144. frame_count = <3>;
  1145. };
  1146. };
  1147. dw {
  1148. subdev_name = "dw";
  1149. idx = <0>;
  1150. path_type = "DW_DWE_VSE0";
  1151. dw_dst_depth = <2>;
  1152. };
  1153. };
  1154. channel1 {
  1155. sensor0 {
  1156. subdev_name = "vivcam";
  1157. idx = <0>; //vivcam0 sc2310
  1158. csi_idx = <0>; //<0>=CSI2
  1159. mode_idx = <1>;
  1160. path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
  1161. };
  1162. isp {
  1163. subdev_name = "isp";
  1164. idx = <1>;
  1165. path_type = "ISP_MI_PATH_MP";
  1166. output {
  1167. max_width = <1920>;
  1168. max_height = <1088>;
  1169. bit_per_pixel = <12>;
  1170. frame_count = <3>;
  1171. };
  1172. };
  1173. dw {
  1174. subdev_name = "dw";
  1175. idx = <0>;
  1176. path_type = "DW_DWE_VSE1";
  1177. dw_dst_depth = <2>;
  1178. };
  1179. };
  1180. channel2 {
  1181. sensor0 {
  1182. subdev_name = "vivcam";
  1183. idx = <0>; //vivcam0 sc2310
  1184. csi_idx = <0>; //<0>=CSI2
  1185. mode_idx = <1>;
  1186. path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
  1187. };
  1188. isp {
  1189. subdev_name = "isp";
  1190. idx = <1>;
  1191. path_type = "ISP_MI_PATH_MP";
  1192. output {
  1193. max_width = <1920>;
  1194. max_height = <1088>;
  1195. bit_per_pixel = <12>;
  1196. frame_count = <3>;
  1197. };
  1198. };
  1199. dw {
  1200. subdev_name = "dw";
  1201. idx = <0>;
  1202. path_type = "DW_DWE_VSE2";
  1203. dw_dst_depth = <2>;
  1204. };
  1205. };
  1206. };
  1207. &video4{
  1208. vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
  1209. channel0 {
  1210. sensor0 {
  1211. subdev_name = "vivcam";
  1212. idx = <0>; //vivcam0 sc2310
  1213. csi_idx = <0>; //<0>=CSI2
  1214. mode_idx = <1>;
  1215. path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
  1216. };
  1217. isp {
  1218. subdev_name = "isp";
  1219. idx = <1>;
  1220. path_type = "ISP_MI_PATH_PP";
  1221. output {
  1222. max_width = <1920>;
  1223. max_height = <1088>;
  1224. bit_per_pixel = <12>;
  1225. frame_count = <3>;
  1226. };
  1227. };
  1228. dsp {
  1229. subdev_name = "dsp";
  1230. idx = <0>;
  1231. path_type = "DSP_PATH_ISP_RY";
  1232. output {
  1233. max_width = <1920>;
  1234. max_height = <1088>;
  1235. bit_per_pixel = <12>;
  1236. frame_count = <3>;
  1237. };
  1238. };
  1239. ry {
  1240. subdev_name = "ry";
  1241. idx = <0>;
  1242. path_type = "ISP_RY_MI_PATH_MP";
  1243. output {
  1244. max_width = <1920>;
  1245. max_height = <1088>;
  1246. bit_per_pixel = <12>;
  1247. frame_count = <3>;
  1248. };
  1249. };
  1250. };
  1251. channel1 {
  1252. sensor0 {
  1253. subdev_name = "vivcam";
  1254. idx = <0>; //vivcam0 sc2310
  1255. csi_idx = <0>; //<0>=CSI2
  1256. mode_idx = <1>;
  1257. path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
  1258. };
  1259. isp {
  1260. subdev_name = "isp";
  1261. idx = <1>;
  1262. path_type = "ISP_MI_PATH_PP";
  1263. output {
  1264. max_width = <1920>;
  1265. max_height = <1088>;
  1266. bit_per_pixel = <12>;
  1267. frame_count = <3>;
  1268. };
  1269. };
  1270. dsp {
  1271. subdev_name = "dsp";
  1272. idx = <0>;
  1273. path_type = "DSP_PATH_ISP_RY";
  1274. output {
  1275. max_width = <1920>;
  1276. max_height = <1088>;
  1277. bit_per_pixel = <12>;
  1278. frame_count = <3>;
  1279. };
  1280. };
  1281. ry {
  1282. subdev_name = "ry";
  1283. idx = <0>;
  1284. path_type = "ISP_RY_MI_PATH_SP";
  1285. output {
  1286. max_width = <1920>;
  1287. max_height = <1088>;
  1288. bit_per_pixel = <12>;
  1289. frame_count = <3>;
  1290. };
  1291. };
  1292. };
  1293. channel2 {
  1294. sensor0 {
  1295. subdev_name = "vivcam";
  1296. idx = <0>; //vivcam0 sc2310
  1297. csi_idx = <0>; //<0>=CSI2
  1298. mode_idx = <1>;
  1299. path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
  1300. };
  1301. isp {
  1302. subdev_name = "isp";
  1303. idx = <1>;
  1304. path_type = "ISP_MI_PATH_PP";
  1305. output {
  1306. max_width = <1920>;
  1307. max_height = <1088>;
  1308. bit_per_pixel = <12>;
  1309. frame_count = <3>;
  1310. };
  1311. };
  1312. dsp {
  1313. subdev_name = "dsp";
  1314. idx = <0>;
  1315. path_type = "DSP_PATH_ISP_RY";
  1316. output {
  1317. max_width = <1920>;
  1318. max_height = <1088>;
  1319. bit_per_pixel = <12>;
  1320. frame_count = <3>;
  1321. };
  1322. };
  1323. ry {
  1324. subdev_name = "ry";
  1325. idx = <0>;
  1326. path_type = "ISP_RY_MI_PATH_SP2_BP";
  1327. output {
  1328. max_width = <1920>;
  1329. max_height = <1088>;
  1330. bit_per_pixel = <12>;
  1331. frame_count = <3>;
  1332. };
  1333. };
  1334. };
  1335. };
  1336. &video5{
  1337. vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
  1338. channel0 {
  1339. sensor0 {
  1340. subdev_name = "vivcam";
  1341. idx = <0>; //vivcam0 sc2310
  1342. csi_idx = <0>; //<0>=CSI2
  1343. mode_idx = <1>;
  1344. path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
  1345. };
  1346. isp {
  1347. subdev_name = "isp";
  1348. idx = <1>;
  1349. path_type = "ISP_MI_PATH_PP";
  1350. output {
  1351. max_width = <1920>;
  1352. max_height = <1088>;
  1353. bit_per_pixel = <12>;
  1354. frame_count = <3>;
  1355. };
  1356. };
  1357. dsp {
  1358. subdev_name = "dsp";
  1359. idx = <0>;
  1360. path_type = "DSP_PATH_ISP_RY";
  1361. output {
  1362. max_width = <1920>;
  1363. max_height = <1088>;
  1364. bit_per_pixel = <12>;
  1365. frame_count = <3>;
  1366. };
  1367. };
  1368. ry {
  1369. subdev_name = "ry";
  1370. idx = <0>;
  1371. path_type = "ISP_RY_MI_PATH_MP";
  1372. output {
  1373. max_width = <1920>;
  1374. max_height = <1088>;
  1375. bit_per_pixel = <12>;
  1376. frame_count = <3>;
  1377. };
  1378. };
  1379. dw {
  1380. subdev_name = "dw";
  1381. idx = <0>;
  1382. path_type = "DW_DWE_VSE0";
  1383. dw_dst_depth = <2>;
  1384. };
  1385. };
  1386. channel1 {
  1387. sensor0 {
  1388. subdev_name = "vivcam";
  1389. idx = <0>; //vivcam0 sc2310
  1390. csi_idx = <0>; //<0>=CSI2
  1391. mode_idx = <1>;
  1392. path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
  1393. };
  1394. isp {
  1395. subdev_name = "isp";
  1396. idx = <1>;
  1397. path_type = "ISP_MI_PATH_PP";
  1398. output {
  1399. max_width = <1920>;
  1400. max_height = <1088>;
  1401. bit_per_pixel = <12>;
  1402. frame_count = <3>;
  1403. };
  1404. };
  1405. dsp {
  1406. subdev_name = "dsp";
  1407. idx = <0>;
  1408. path_type = "DSP_PATH_ISP_RY";
  1409. output {
  1410. max_width = <1920>;
  1411. max_height = <1088>;
  1412. bit_per_pixel = <12>;
  1413. frame_count = <3>;
  1414. };
  1415. };
  1416. ry {
  1417. subdev_name = "ry";
  1418. idx = <0>;
  1419. path_type = "ISP_RY_MI_PATH_MP";
  1420. output {
  1421. max_width = <1920>;
  1422. max_height = <1088>;
  1423. bit_per_pixel = <12>;
  1424. frame_count = <3>;
  1425. };
  1426. };
  1427. dw {
  1428. subdev_name = "dw";
  1429. idx = <0>;
  1430. path_type = "DW_DWE_VSE1";
  1431. dw_dst_depth = <2>;
  1432. };
  1433. };
  1434. channel2 {
  1435. sensor0 {
  1436. subdev_name = "vivcam";
  1437. idx = <0>; //vivcam0 sc2310
  1438. csi_idx = <0>; //<0>=CSI2
  1439. mode_idx = <1>;
  1440. path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
  1441. };
  1442. isp {
  1443. subdev_name = "isp";
  1444. idx = <1>;
  1445. path_type = "ISP_MI_PATH_PP";
  1446. output {
  1447. max_width = <1920>;
  1448. max_height = <1088>;
  1449. bit_per_pixel = <12>;
  1450. frame_count = <3>;
  1451. };
  1452. };
  1453. dsp {
  1454. subdev_name = "dsp";
  1455. idx = <0>;
  1456. path_type = "DSP_PATH_ISP_RY";
  1457. output {
  1458. max_width = <1920>;
  1459. max_height = <1088>;
  1460. bit_per_pixel = <12>;
  1461. frame_count = <3>;
  1462. };
  1463. };
  1464. ry {
  1465. subdev_name = "ry";
  1466. idx = <0>;
  1467. path_type = "ISP_RY_MI_PATH_MP";
  1468. output {
  1469. max_width = <1920>;
  1470. max_height = <1088>;
  1471. bit_per_pixel = <12>;
  1472. frame_count = <3>;
  1473. };
  1474. };
  1475. dw {
  1476. subdev_name = "dw";
  1477. idx = <0>;
  1478. path_type = "DW_DWE_VSE2";
  1479. dw_dst_depth = <2>;
  1480. };
  1481. };
  1482. };
  1483. &video6{
  1484. vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1]
  1485. channel0 {
  1486. sensor0 {
  1487. subdev_name = "vivcam";
  1488. idx = <1>; // vivcam1 sc132gs
  1489. csi_idx = <2>; //<2>=CSI2X2_A
  1490. flash_led_idx = <0>;
  1491. mode_idx= <0>;
  1492. path_type = "SENSOR_1080X1280_RAW10_LINER";
  1493. };
  1494. dsp{
  1495. output {
  1496. max_width = <1080>;
  1497. max_height = <1280>;
  1498. bit_per_pixel = <16>;
  1499. frame_count = <3>;
  1500. };
  1501. };
  1502. };
  1503. channel1 {
  1504. sensor0 {
  1505. subdev_name = "vivcam";
  1506. idx = <1>; //vivcam1 sc132gs
  1507. csi_idx = <2>; //<2>=CSI2X2_A
  1508. flash_led_idx = <0>;
  1509. mode_idx= <0>;
  1510. path_type = "SENSOR_1080X1280_RAW10_LINER";
  1511. };
  1512. dsp{
  1513. output {
  1514. max_width = <1080>;
  1515. max_height = <1280>;
  1516. bit_per_pixel = <16>;
  1517. frame_count = <3>;
  1518. };
  1519. };
  1520. };
  1521. };
  1522. &video7{
  1523. channel0 {
  1524. sensor0 {
  1525. subdev_name = "vivcam";
  1526. idx = <2>; //<2>=vivcam2 : gc5035
  1527. csi_idx = <1>; //<1>=CSI2X2_B
  1528. mode_idx = <3>;
  1529. path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
  1530. };
  1531. sensor1 {
  1532. subdev_name = "vivcam";
  1533. idx = <3>; //<3>=vivcam3 : gc02m1b
  1534. csi_idx = <1>; //<1>=CSI2X2_B
  1535. mode_idx = <0>;
  1536. path_type = "SENSOR_1600x1200_RAW10_LINER";
  1537. };
  1538. isp {
  1539. subdev_name = "isp";
  1540. idx = <0>;
  1541. path_type = "ISP_MI_PATH_PP";
  1542. output {
  1543. max_width = <1920>;
  1544. max_height = <1088>;
  1545. bit_per_pixel = <12>;
  1546. frame_count = <3>;
  1547. };
  1548. };
  1549. dsp {
  1550. subdev_name = "dsp";
  1551. idx = <1>;
  1552. path_type = "DSP_PATH_ISP_RY";
  1553. output {
  1554. max_width = <1920>;
  1555. max_height = <1088>;
  1556. bit_per_pixel = <12>;
  1557. frame_count = <3>;
  1558. };
  1559. };
  1560. ry {
  1561. subdev_name = "ry";
  1562. idx = <0>;
  1563. path_type = "ISP_RY_MI_PATH_MP";
  1564. output {
  1565. max_width = <1920>;
  1566. max_height = <1088>;
  1567. bit_per_pixel = <12>;
  1568. frame_count = <3>;
  1569. };
  1570. };
  1571. dw {
  1572. subdev_name = "dw";
  1573. idx = <0>;
  1574. path_type = "DW_DWE_VSE0";
  1575. dw_dst_depth = <2>;
  1576. };
  1577. };
  1578. channel1 {
  1579. sensor0 {
  1580. subdev_name = "vivcam";
  1581. idx = <2>; //<2>=vivcam2 : gc5035
  1582. csi_idx = <1>; //<1>=CSI2X2_B
  1583. mode_idx = <3>;
  1584. path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
  1585. };
  1586. sensor1 {
  1587. subdev_name = "vivcam";
  1588. idx = <3>; //<3>=vivcam3 : gc02m1b
  1589. csi_idx = <1>; //<1>=CSI2X2_B
  1590. mode_idx = <0>;
  1591. path_type = "SENSOR_1600x1200_RAW10_LINER";
  1592. };
  1593. isp {
  1594. subdev_name = "isp";
  1595. idx = <0>;
  1596. path_type = "ISP_MI_PATH_PP";
  1597. output {
  1598. max_width = <1920>;
  1599. max_height = <1088>;
  1600. bit_per_pixel = <12>;
  1601. frame_count = <3>;
  1602. };
  1603. };
  1604. dsp {
  1605. subdev_name = "dsp";
  1606. idx = <1>;
  1607. path_type = "DSP_PATH_ISP_RY";
  1608. output {
  1609. max_width = <1920>;
  1610. max_height = <1088>;
  1611. bit_per_pixel = <12>;
  1612. frame_count = <3>;
  1613. };
  1614. };
  1615. ry {
  1616. subdev_name = "ry";
  1617. idx = <0>;
  1618. path_type = "ISP_RY_MI_PATH_MP";
  1619. output {
  1620. max_width = <1920>;
  1621. max_height = <1088>;
  1622. bit_per_pixel = <12>;
  1623. frame_count = <3>;
  1624. };
  1625. };
  1626. dw {
  1627. subdev_name = "dw";
  1628. idx = <0>;
  1629. path_type = "DW_DWE_VSE1";
  1630. dw_dst_depth = <2>;
  1631. };
  1632. };
  1633. channel2 {
  1634. sensor0 {
  1635. subdev_name = "vivcam";
  1636. idx = <2>; //<2>=vivcam2 : gc5035
  1637. csi_idx = <1>; //<1>=CSI2X2_B
  1638. mode_idx = <3>;
  1639. path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
  1640. };
  1641. sensor1 {
  1642. subdev_name = "vivcam";
  1643. idx = <3>; //<3>=vivcam3 : gc02m1b
  1644. csi_idx = <1>; //<1>=CSI2X2_B
  1645. mode_idx = <0>;
  1646. path_type = "SENSOR_1600x1200_RAW10_LINER";
  1647. };
  1648. isp {
  1649. subdev_name = "isp";
  1650. idx = <0>;
  1651. path_type = "ISP_MI_PATH_PP";
  1652. output {
  1653. max_width = <1920>;
  1654. max_height = <1088>;
  1655. bit_per_pixel = <12>;
  1656. frame_count = <3>;
  1657. };
  1658. };
  1659. dsp {
  1660. subdev_name = "dsp";
  1661. idx = <1>;
  1662. path_type = "DSP_PATH_ISP_RY";
  1663. output {
  1664. max_width = <1920>;
  1665. max_height = <1088>;
  1666. bit_per_pixel = <12>;
  1667. frame_count = <3>;
  1668. };
  1669. };
  1670. ry {
  1671. subdev_name = "ry";
  1672. idx = <0>;
  1673. path_type = "ISP_RY_MI_PATH_MP";
  1674. output {
  1675. max_width = <1920>;
  1676. max_height = <1088>;
  1677. bit_per_pixel = <12>;
  1678. frame_count = <3>;
  1679. };
  1680. };
  1681. dw {
  1682. subdev_name = "dw";
  1683. idx = <0>;
  1684. path_type = "DW_DWE_VSE2";
  1685. dw_dst_depth = <2>;
  1686. };
  1687. };
  1688. };
  1689. &video8{
  1690. vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1]
  1691. channel0 {
  1692. sensor0 {
  1693. subdev_name = "vivcam";
  1694. idx = <2>; //<2>=vivcam2 : gc5035
  1695. csi_idx = <1>; //<1>=CSI2X2_B
  1696. mode_idx = <3>;
  1697. path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
  1698. };
  1699. sensor1 {
  1700. subdev_name = "vivcam";
  1701. idx = <3>; //<3>=vivcam3 : gc02m1b
  1702. csi_idx = <1>; //<1>=CSI2X2_B
  1703. mode_idx = <0>;
  1704. path_type = "SENSOR_1600x1200_RAW10_LINER";
  1705. };
  1706. dsp {
  1707. subdev_name = "dsp";
  1708. idx = <0>;
  1709. path_type = "DSP_PATH_VIPRE_DDR";
  1710. output {
  1711. max_width = <1920>;
  1712. max_height = <1088>;
  1713. bit_per_pixel = <12>;
  1714. frame_count = <3>;
  1715. };
  1716. };
  1717. };
  1718. };
  1719. &video9{
  1720. channel0 {
  1721. sensor0 {
  1722. subdev_name = "vivcam";
  1723. idx = <1>; //vivcam1 sc132gs
  1724. csi_idx = <2>; //<2>=CSI2X2_A
  1725. mode_idx= <0>;
  1726. path_type = "SENSOR_1080X1280_RAW10_LINER";
  1727. };
  1728. dsp{
  1729. output {
  1730. max_width = <1080>;
  1731. max_height = <1280>;
  1732. bit_per_pixel = <16>;
  1733. frame_count = <3>;
  1734. };
  1735. };
  1736. };
  1737. };
  1738. &video10{ // TUNINGTOOL
  1739. channel0 {
  1740. sensor0 {
  1741. subdev_name = "vivcam";
  1742. idx = <2>; //<2>=vivcam2 : gc5035
  1743. csi_idx = <1>; //<1>=CSI2X2_B
  1744. mode_idx= <1>;
  1745. path_type = "SENSOR_1920X1080_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
  1746. skip_init = <1>;
  1747. };
  1748. sensor1 {
  1749. subdev_name = "vivcam";
  1750. idx = <3>; //<3>=vivcam3 : gc02m1b
  1751. csi_idx = <1>; //<1>=CSI2X2_B
  1752. mode_idx = <0>;
  1753. path_type = "SENSOR_1600x1200_RAW10_LINER";
  1754. skip_init = <1>;
  1755. };
  1756. };
  1757. };
  1758. &video11{
  1759. channel0 {
  1760. channel_id = <0>;
  1761. status = "okay";
  1762. sensor0 {
  1763. subdev_name = "vivcam";
  1764. idx = <1>; //sc132gs
  1765. csi_idx = <2>; //<2>=CSI2X2_A
  1766. flash_led_idx = <0>;
  1767. mode_idx= <0>;
  1768. path_type = "SENSOR_1080X1280_RAW10_LINER";
  1769. };
  1770. isp {
  1771. subdev_name = "isp";
  1772. idx = <0>;
  1773. path_type = "ISP_MI_PATH_MP";
  1774. output {
  1775. max_width = <1920>;
  1776. max_height = <1088>;
  1777. bit_per_pixel = <12>;
  1778. frame_count = <3>;
  1779. };
  1780. };
  1781. };
  1782. };
  1783. &video12{ // TUNINGTOOL
  1784. channel0 { // CSI2
  1785. sensor0 {
  1786. subdev_name = "vivcam";
  1787. idx = <0>; //sc2310
  1788. csi_idx = <0>; //<0>=CSI2
  1789. mode_idx = <1>;
  1790. path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
  1791. skip_init = <1>;
  1792. };
  1793. };
  1794. };
  1795. &trng {
  1796. status = "disabled";
  1797. };
  1798. &eip_28 {
  1799. status = "okay";
  1800. };
  1801. &vdec {
  1802. status = "okay";
  1803. };
  1804. &venc {
  1805. status = "okay";
  1806. };
  1807. &isp_venc_shake {
  1808. status = "okay";
  1809. };
  1810. &vidmem {
  1811. status = "okay";
  1812. memory-region = <&vi_mem>;
  1813. };
  1814. &gpu {
  1815. status = "okay";
  1816. };
  1817. &npu {
  1818. vha_clk_rate = <1000000000>;
  1819. status = "okay";
  1820. };
  1821. &fce {
  1822. memory-region = <&facelib_mem>;
  1823. status = "okay";
  1824. };
  1825. &dpu_enc0 {
  1826. status = "okay";
  1827. ports {
  1828. /* output */
  1829. port@1 {
  1830. reg = <1>;
  1831. enc0_out: endpoint {
  1832. remote-endpoint = <&dsi0_in>;
  1833. };
  1834. };
  1835. };
  1836. };
  1837. &dpu_enc1 {
  1838. ports {
  1839. /delete-node/ port@0;
  1840. };
  1841. };
  1842. &dpu {
  1843. status = "okay";
  1844. };
  1845. &dsi0 {
  1846. status = "okay";
  1847. };
  1848. &dhost_0 {
  1849. ports {
  1850. #address-cells = <1>;
  1851. #size-cells = <0>;
  1852. port@0 {
  1853. reg = <0>;
  1854. dsi0_in: endpoint {
  1855. remote-endpoint = <&enc0_out>;
  1856. };
  1857. };
  1858. port@1 {
  1859. reg = <1>;
  1860. dsi0_out: endpoint {
  1861. remote-endpoint = <&panel0_in>;
  1862. };
  1863. };
  1864. };
  1865. panel0@0 {
  1866. compatible = "txd,dy800qwxpab";
  1867. reg = <0>;
  1868. backlight = <&lcd0_backlight>;
  1869. reset-gpio = <&gpio1_porta 5 1>; /* active low */
  1870. vdd1v8-supply = <&soc_vdd18_lcd0_en_reg>;
  1871. vspn5v7-supply = <&soc_lcd0_bias_en_reg>;
  1872. port {
  1873. panel0_in: endpoint {
  1874. remote-endpoint = <&dsi0_out>;
  1875. };
  1876. };
  1877. };
  1878. };
  1879. &disp1_out {
  1880. remote-endpoint = <&hdmi_tx_in>;
  1881. };
  1882. &hdmi_tx {
  1883. status = "okay";
  1884. port@0 {
  1885. /* input */
  1886. hdmi_tx_in: endpoint {
  1887. remote-endpoint = <&disp1_out>;
  1888. };
  1889. };
  1890. };
  1891. &lightsound {
  1892. status = "okay";
  1893. simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/
  1894. reg = <0>;
  1895. format = "i2s";
  1896. cpu {
  1897. sound-dai = <&i2s1 0>;
  1898. };
  1899. codec {
  1900. sound-dai = <&es8156_audio_codec>;
  1901. };
  1902. };
  1903. simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/
  1904. reg = <1>;
  1905. format = "i2s";
  1906. cpu {
  1907. sound-dai = <&i2s3 0>;
  1908. };
  1909. codec {
  1910. sound-dai = <&es7210_audio_codec>;
  1911. };
  1912. };
  1913. simple-audio-card,dai-link@2 { /* I2S - HDMI */
  1914. reg = <2>;
  1915. format = "i2s";
  1916. cpu {
  1917. sound-dai = <&light_i2s 1>;
  1918. };
  1919. codec {
  1920. sound-dai = <&dummy_codec 2>;
  1921. };
  1922. };
  1923. };
  1924. &light_i2s {
  1925. status = "okay";
  1926. };
  1927. &i2s0 {
  1928. status = "okay";
  1929. };
  1930. &i2s1 {
  1931. status = "okay";
  1932. };
  1933. &i2s3 {
  1934. status = "okay";
  1935. };
  1936. &cpus {
  1937. c910_0: cpu@0 {
  1938. operating-points = <
  1939. /* kHz uV */
  1940. 300000 720000
  1941. 800000 720000
  1942. 1500000 820000
  1943. >;
  1944. light,dvddm-operating-points = <
  1945. /* kHz uV */
  1946. 300000 770000
  1947. 800000 820000
  1948. 1500000 820000
  1949. >;
  1950. };
  1951. c910_1: cpu@1 {
  1952. operating-points = <
  1953. /* kHz uV */
  1954. 300000 720000
  1955. 800000 720000
  1956. 1500000 820000
  1957. >;
  1958. light,dvddm-operating-points = <
  1959. /* kHz uV */
  1960. 300000 770000
  1961. 800000 820000
  1962. 1500000 820000
  1963. >;
  1964. };
  1965. c910_2: cpu@2 {
  1966. operating-points = <
  1967. /* kHz uV */
  1968. 300000 720000
  1969. 800000 720000
  1970. 1500000 820000
  1971. >;
  1972. light,dvddm-operating-points = <
  1973. /* kHz uV */
  1974. 300000 770000
  1975. 800000 820000
  1976. 1500000 820000
  1977. >;
  1978. };
  1979. c910_3: cpu@3 {
  1980. operating-points = <
  1981. /* kHz uV */
  1982. 300000 720000
  1983. 800000 720000
  1984. 1500000 820000
  1985. >;
  1986. light,dvddm-operating-points = <
  1987. /* kHz uV */
  1988. 300000 770000
  1989. 800000 820000
  1990. 1500000 820000
  1991. >;
  1992. };
  1993. };