fire.dtsi 53 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2021 Alibaba Group Holding Limited.
  4. */
  5. #include <dt-bindings/pinctrl/light-fm-left-pinctrl.h>
  6. #include <dt-bindings/pinctrl/light-fm-right-pinctrl.h>
  7. #include <dt-bindings/pinctrl/light-fm-aon-pinctrl.h>
  8. #include <dt-bindings/clock/light-fm-ap-clock.h>
  9. #include <dt-bindings/clock/light-vpsys.h>
  10. #include <dt-bindings/clock/light-vosys.h>
  11. #include <dt-bindings/clock/light-visys.h>
  12. #include <dt-bindings/clock/light-dspsys.h>
  13. #include <dt-bindings/firmware/thead/rsrc.h>
  14. #include <dt-bindings/soc/thead,light-iopmp.h>
  15. #include <dt-bindings/thermal/thermal.h>
  16. #include <dt-bindings/reset/light-reset.h>
  17. / {
  18. compatible = "thead,fire";
  19. #address-cells = <2>;
  20. #size-cells = <2>;
  21. aliases {
  22. ethernet0 = &gmac0;
  23. gpio0 = &gpio0;
  24. gpio1 = &gpio1;
  25. gpio2 = &gpio2;
  26. gpio3 = &gpio3;
  27. i2c0 = &i2c0;
  28. i2c1 = &i2c1;
  29. i2c2 = &i2c2;
  30. i2c3 = &i2c3;
  31. i2c4 = &i2c4;
  32. audio_i2c0 = &audio_i2c0;
  33. mmc0 = &emmc;
  34. mmc1 = &sdhci0;
  35. serial0 = &uart0;
  36. serial1 = &uart1;
  37. serial2 = &uart2;
  38. serial3 = &uart3;
  39. serial4 = &uart4;
  40. serial5 = &uart5;
  41. spi0 = &spi0;
  42. spi1 = &qspi0;
  43. spi2 = &qspi1;
  44. flash_led0 = &vvcam_flash_led0;
  45. vivcam0 = &vvcam_sensor0;
  46. vivcam1 = &vvcam_sensor1;
  47. vivcam2 = &vvcam_sensor2;
  48. vivcam3 = &vvcam_sensor3;
  49. vivcam4 = &vvcam_sensor4;
  50. vivcam5 = &vvcam_sensor5;
  51. vivcam6 = &vvcam_sensor6;
  52. viv_video0 = &video0;
  53. viv_video1 = &video1;
  54. viv_video2 = &video2;
  55. viv_video3 = &video3;
  56. viv_video4 = &video4;
  57. viv_video5 = &video5;
  58. viv_video6 = &video6;
  59. viv_video7 = &video7;
  60. viv_video8 = &video8;
  61. viv_video9 = &video9;
  62. viv_video10 = &video10;
  63. viv_video11 = &video11;
  64. viv_video12 = &video12;
  65. viv_video13 = &video13;
  66. viv_video14 = &video14;
  67. viv_video15 = &video15;
  68. };
  69. memory@0 {
  70. device_type = "memory";
  71. reg = <0x0 0x200000 0x0 0xffe00000>;
  72. };
  73. resmem: reserved-memory {
  74. #address-cells = <2>;
  75. #size-cells = <2>;
  76. ranges;
  77. /* global autoconfigured region for contiguous allocations */
  78. cmamem: linux,cma {
  79. compatible = "shared-dma-pool";
  80. reusable;
  81. size = <0 0x14000000>; // 320MB by default
  82. alloc-ranges = <0 0x64000000 0 0x14000000>; // [0x6400_0000 ~ 0x7800_0000]
  83. linux,cma-default;
  84. };
  85. };
  86. thermal_zones: thermal-zones {
  87. cpu-thermal-zone {
  88. polling-delay-passive = <250>;
  89. polling-delay = <2000>;
  90. thermal-sensors = <&pvt 0>;
  91. trips {
  92. cpu_config0: trip0 {
  93. temperature = <85000>;
  94. hysteresis = <2000>;
  95. type = "passive";
  96. };
  97. cpu_config1: trip1 {
  98. temperature = <110000>;
  99. hysteresis = <2000>;
  100. type = "critical";
  101. };
  102. };
  103. cooling-maps {
  104. cpu_cdev {
  105. trip = <&cpu_config0>;
  106. cooling-device =
  107. <&c910_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  108. <&c910_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  109. <&c910_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  110. <&c910_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  111. };
  112. };
  113. };
  114. };
  115. cpus: cpus {
  116. #address-cells = <1>;
  117. #size-cells = <0>;
  118. timebase-frequency = <3000000>;
  119. c910_0: cpu@0 {
  120. device_type = "cpu";
  121. reg = <0>;
  122. status = "okay";
  123. compatible = "riscv";
  124. riscv,isa = "rv64imafdcvsu";
  125. mmu-type = "riscv,sv39";
  126. cpu-freq = "1.848Ghz";
  127. cpu-icache = "64KB";
  128. cpu-dcache = "64KB";
  129. cpu-l2cache = "1MB";
  130. cpu-tlb = "1024 4-ways";
  131. cpu-cacheline = "64Bytes";
  132. cpu-vector = "0.7.1";
  133. #cooling-cells = <2>;
  134. operating-points = <
  135. /* kHz uV */
  136. 300000 600000
  137. 800000 700000
  138. 1500000 800000
  139. 1848000 1000000
  140. >;
  141. light,dvddm-operating-points = <
  142. /* kHz uV */
  143. 300000 750000
  144. 800000 800000
  145. 1500000 800000
  146. 1848000 1000000
  147. >;
  148. clock-latency = <61036>;
  149. clocks = <&clk C910_CCLK>,
  150. <&clk C910_CCLK_I0>,
  151. <&clk CPU_PLL1_FOUTPOSTDIV>,
  152. <&clk CPU_PLL0_FOUTPOSTDIV>;
  153. clock-names = "c910_cclk", "c910_cclk_i0",
  154. "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
  155. cpu0_intc: interrupt-controller {
  156. #interrupt-cells = <1>;
  157. compatible = "riscv,cpu-intc";
  158. interrupt-controller;
  159. };
  160. };
  161. c910_1: cpu@1 {
  162. device_type = "cpu";
  163. reg = <1>;
  164. status = "disabled";
  165. compatible = "riscv";
  166. riscv,isa = "rv64imafdcvsu";
  167. mmu-type = "riscv,sv39";
  168. cpu-freq = "1.848Ghz";
  169. cpu-icache = "64KB";
  170. cpu-dcache = "64KB";
  171. cpu-l2cache = "1MB";
  172. cpu-tlb = "1024 4-ways";
  173. cpu-cacheline = "64Bytes";
  174. cpu-vector = "0.7.1";
  175. #cooling-cells = <2>;
  176. operating-points = <
  177. /* kHz uV */
  178. 300000 600000
  179. 800000 700000
  180. 1500000 800000
  181. 1848000 1000000
  182. >;
  183. light,dvddm-operating-points = <
  184. /* kHz uV */
  185. 300000 750000
  186. 800000 800000
  187. 1500000 800000
  188. 1848000 1000000
  189. >;
  190. clock-latency = <61036>;
  191. clocks = <&clk C910_CCLK>,
  192. <&clk C910_CCLK_I0>,
  193. <&clk CPU_PLL1_FOUTPOSTDIV>,
  194. <&clk CPU_PLL0_FOUTPOSTDIV>;
  195. clock-names = "c910_cclk", "c910_cclk_i0",
  196. "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
  197. cpu1_intc: interrupt-controller {
  198. #interrupt-cells = <1>;
  199. compatible = "riscv,cpu-intc";
  200. interrupt-controller;
  201. };
  202. };
  203. c910_2: cpu@2 {
  204. device_type = "cpu";
  205. reg = <2>;
  206. status = "disabled";
  207. compatible = "riscv";
  208. riscv,isa = "rv64imafdcvsu";
  209. mmu-type = "riscv,sv39";
  210. cpu-freq = "1.848Ghz";
  211. cpu-icache = "64KB";
  212. cpu-dcache = "64KB";
  213. cpu-l2cache = "1MB";
  214. cpu-tlb = "1024 4-ways";
  215. cpu-cacheline = "64Bytes";
  216. cpu-vector = "0.7.1";
  217. #cooling-cells = <2>;
  218. operating-points = <
  219. /* kHz uV */
  220. 300000 600000
  221. 800000 700000
  222. 1500000 800000
  223. 1848000 1000000
  224. >;
  225. light,dvddm-operating-points = <
  226. /* kHz uV */
  227. 300000 750000
  228. 800000 800000
  229. 1500000 800000
  230. 1848000 1000000
  231. >;
  232. clock-latency = <61036>;
  233. clocks = <&clk C910_CCLK>,
  234. <&clk C910_CCLK_I0>,
  235. <&clk CPU_PLL1_FOUTPOSTDIV>,
  236. <&clk CPU_PLL0_FOUTPOSTDIV>;
  237. clock-names = "c910_cclk", "c910_cclk_i0",
  238. "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
  239. cpu2_intc: interrupt-controller {
  240. #interrupt-cells = <1>;
  241. compatible = "riscv,cpu-intc";
  242. interrupt-controller;
  243. };
  244. };
  245. c910_3: cpu@3 {
  246. device_type = "cpu";
  247. reg = <3>;
  248. status = "disabled";
  249. compatible = "riscv";
  250. riscv,isa = "rv64imafdcvsu";
  251. mmu-type = "riscv,sv39";
  252. cpu-freq = "1.848Ghz";
  253. cpu-icache = "64KB";
  254. cpu-dcache = "64KB";
  255. cpu-l2cache = "1MB";
  256. cpu-tlb = "1024 4-ways";
  257. cpu-cacheline = "64Bytes";
  258. cpu-vector = "0.7.1";
  259. #cooling-cells = <2>;
  260. operating-points = <
  261. /* kHz uV */
  262. 300000 600000
  263. 800000 700000
  264. 1500000 800000
  265. 1848000 1000000
  266. >;
  267. light,dvddm-operating-points = <
  268. /* kHz uV */
  269. 300000 750000
  270. 800000 800000
  271. 1500000 800000
  272. 1848000 1000000
  273. >;
  274. clock-latency = <61036>;
  275. clocks = <&clk C910_CCLK>,
  276. <&clk C910_CCLK_I0>,
  277. <&clk CPU_PLL1_FOUTPOSTDIV>,
  278. <&clk CPU_PLL0_FOUTPOSTDIV>;
  279. clock-names = "c910_cclk", "c910_cclk_i0",
  280. "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
  281. cpu3_intc: interrupt-controller {
  282. #interrupt-cells = <1>;
  283. compatible = "riscv,cpu-intc";
  284. interrupt-controller;
  285. };
  286. };
  287. };
  288. display_subsystem: display-subsystem {
  289. compatible = "verisilicon,display-subsystem";
  290. ports = <&dpu_disp0>, <&dpu_disp1>;
  291. status = "disabled";
  292. };
  293. dpu-encoders {
  294. compatible = "simple-bus";
  295. #address-cells = <1>;
  296. #size-cells = <0>;
  297. dpu_enc0: dpu-encoder@0 {
  298. /* default encoder is DSI */
  299. compatible = "verisilicon,dsi-encoder";
  300. reg = <0>;
  301. status = "disabled";
  302. ports {
  303. #address-cells = <1>;
  304. #size-cells = <0>;
  305. /* input */
  306. port@0 {
  307. reg = <0>;
  308. enc0_in: endpoint {
  309. remote-endpoint = <&disp0_out>;
  310. };
  311. };
  312. };
  313. };
  314. dpu_enc1: dpu-encoder@1 {
  315. /* default encoder is DSI */
  316. compatible = "verisilicon,dsi-encoder";
  317. reg = <1>;
  318. status = "disabled";
  319. ports {
  320. #address-cells = <1>;
  321. #size-cells = <0>;
  322. /* input */
  323. port@0 {
  324. reg = <0>;
  325. enc1_in: endpoint {
  326. remote-endpoint = <&disp1_out>;
  327. };
  328. };
  329. };
  330. };
  331. };
  332. soc {
  333. compatible = "simple-bus";
  334. #address-cells = <2>;
  335. #size-cells = <2>;
  336. ranges;
  337. reset: reset-sample {
  338. compatible = "thead,reset-sample";
  339. plic-delegate = <0xff 0xd81ffffc>;
  340. entry-reg = <0xff 0xff019050>;
  341. entry-cnt = <4>;
  342. control-reg = <0xff 0xff015004>;
  343. control-val = <0x1c>;
  344. csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
  345. };
  346. clint0: clint@ffdc000000 {
  347. compatible = "riscv,clint0";
  348. interrupts-extended = <
  349. &cpu0_intc 3 &cpu0_intc 7
  350. &cpu1_intc 3 &cpu1_intc 7
  351. &cpu2_intc 3 &cpu2_intc 7
  352. &cpu3_intc 3 &cpu3_intc 7
  353. >;
  354. reg = <0xff 0xdc000000 0x0 0x04000000>;
  355. clint,has-no-64bit-mmio;
  356. };
  357. intc: interrupt-controller@ffd8000000 {
  358. #interrupt-cells = <1>;
  359. compatible = "riscv,plic0";
  360. interrupt-controller;
  361. interrupts-extended = <
  362. &cpu0_intc 0xffffffff &cpu0_intc 9
  363. &cpu1_intc 0xffffffff &cpu1_intc 9
  364. &cpu2_intc 0xffffffff &cpu2_intc 9
  365. &cpu3_intc 0xffffffff &cpu3_intc 9
  366. >;
  367. reg = <0xff 0xd8000000 0x0 0x04000000>;
  368. reg-names = "control";
  369. riscv,max-priority = <7>;
  370. riscv,ndev = <240>;
  371. };
  372. clocks {
  373. compatible = "simple-bus";
  374. #address-cells = <1>;
  375. #size-cells = <0>;
  376. dummy_clock_apb: apb-clock@0 {
  377. compatible = "fixed-clock";
  378. reg = <0>; /* Not address, just for index */
  379. clock-frequency = <50000000>;
  380. clock-output-names = "dummy_clock_apb";
  381. #clock-cells = <0>;
  382. };
  383. dummy_clock_ref: ref-clock@1 {
  384. compatible = "fixed-clock";
  385. reg = <1>; /* Not address, just for index */
  386. clock-frequency = <50000000>;
  387. clock-output-names = "dummy_clock_ref";
  388. #clock-cells = <0>;
  389. };
  390. dummy_clock_suspend: suspend-clock@2 {
  391. compatible = "fixed-clock";
  392. reg = <2>; /* Not address, just for index */
  393. clock-frequency = <50000000>;
  394. clock-output-names = "dummy_clock_suspend";
  395. #clock-cells = <0>;
  396. };
  397. dummy_clock_rtc: rtc-clock@3 {
  398. compatible = "fixed-clock";
  399. reg = <3>; /* Not address, just for index */
  400. clock-frequency = <32768>;
  401. clock-output-names = "dummy_clock_rtc";
  402. #clock-cells = <0>;
  403. };
  404. dummy_clock_ahb: ahb-clock@4 {
  405. compatible = "fixed-clock";
  406. reg = <4>; /* Not address, just for index */
  407. clock-frequency = <50000000>;
  408. clock-output-names = "dummy_clock_ahb";
  409. #clock-cells = <0>;
  410. };
  411. dummy_clock_gpu: gpu-clock@6 {
  412. compatible = "fixed-clock";
  413. reg = <6>; /* Not address, just for index */
  414. clock-frequency = <18000000>;
  415. clock-output-names = "dummy_clock_gpu";
  416. #clock-cells = <0>;
  417. };
  418. dummy_clock_dphy_ref: dphy-ref-clock@7 {
  419. compatible = "fixed-clock";
  420. reg = <7>; /* Not address, just for index */
  421. clock-frequency = <40000000>;
  422. clock-output-names = "dummy_clock_dphy_ref";
  423. #clock-cells = <0>;
  424. };
  425. dummy_clock_dphy_cfg: dphy-cfg-clock@8 {
  426. compatible = "fixed-clock";
  427. reg = <8>; /* Not address, just for index */
  428. clock-frequency = <40000000>;
  429. clock-output-names = "dummy_clock_dphy_cfg";
  430. #clock-cells = <0>;
  431. };
  432. dummy_clock_dpu_pixel0: dpu-pixel-clock@9 {
  433. compatible = "fixed-clock";
  434. reg = <9>;
  435. clock-frequency = <25200000>;
  436. clock-output-names = "dummy_clock_dpu_pixel0";
  437. #clock-cells = <0>;
  438. };
  439. dummy_clock_dpu_pixel1: dpu-pixel-clock@10 {
  440. compatible = "fixed-clock";
  441. reg = <10>;
  442. clock-frequency = <25200000>;
  443. clock-output-names = "dummy_clock_dpu_pixel1";
  444. #clock-cells = <0>;
  445. };
  446. osc_32k: clock-osc-32k@11 {
  447. compatible = "fixed-clock";
  448. reg = <11>;
  449. #clock-cells = <0>;
  450. clock-frequency = <32768>;
  451. clock-output-names = "osc_32k";
  452. };
  453. osc_24m: clock-osc-24m@12 {
  454. compatible = "fixed-clock";
  455. reg = <12>;
  456. #clock-cells = <0>;
  457. clock-frequency = <24000000>;
  458. clock-output-names = "osc_24m";
  459. };
  460. rc_24m: clock-rc-24m@13 {
  461. compatible = "fixed-clock";
  462. reg = <13>;
  463. #clock-cells = <0>;
  464. clock-frequency = <24000000>;
  465. clock-output-names = "rc_24m";
  466. };
  467. dummy_clock_eip: eip-clock@14 {
  468. compatible = "fixed-clock";
  469. reg = <14>; /* Not address, just for index */
  470. clock-frequency = <30000000>;
  471. clock-output-names = "dummy_clock_eip";
  472. #clock-cells = <0>;
  473. };
  474. dummy_clock_spi: spi-clock@15 {
  475. compatible = "fixed-clock";
  476. reg = <15>; /* Not address, just for index */
  477. clock-frequency = <50000000>;
  478. clock-output-names = "dummy_clock_spi";
  479. #clock-cells = <0>;
  480. };
  481. dummy_clock_qspi: spi-clock@16 {
  482. compatible = "fixed-clock";
  483. reg = <15>; /* Not address, just for index */
  484. clock-frequency = <50000000>;
  485. clock-output-names = "dummy_clock_qspi";
  486. #clock-cells = <0>;
  487. };
  488. dummy_gmac_ahb: gmac-ahb-clock@16 {
  489. compatible = "fixed-clock";
  490. reg = <16>;
  491. clock-frequency = <50000000>;
  492. clock-output-names = "dummy_gmac_ahb";
  493. #clock-cells = <0>;
  494. };
  495. dummy_clock_gmac: gmac-clock@17 {
  496. compatible = "fixed-clock";
  497. reg = <17>;
  498. clock-frequency = <50000000>;
  499. clock-output-names = "dummy_clock_gmac";
  500. #clock-cells = <0>;
  501. };
  502. dummy_clock_sdhci: sdhci-clock@18 {
  503. compatible = "fixed-clock";
  504. reg = <18>; /* Not address, just for index */
  505. clock-frequency = <50000000>;
  506. clock-output-names = "dummy_clock_sdhci";
  507. #clock-cells = <0>;
  508. };
  509. dummy_clock_aonsys_clk: aonsys-clk-clock@19 {
  510. compatible = "fixed-clock";
  511. reg = <19>; /* Not address, just for index */
  512. clock-frequency = <24000000>;
  513. clock-output-names = "dummy_clock_aonsys_clk";
  514. #clock-cells = <0>;
  515. };
  516. dummy_clock_uart: uart-sclk-clock@20 {
  517. compatible = "fixed-clock";
  518. reg = <20>; /* Not address, just for index */
  519. clock-frequency = <50000000>;
  520. clock-output-names = "dummy_clock_uart";
  521. #clock-cells = <0>;
  522. };
  523. dummy_clock_visys: visys-dummy-clock@21 {
  524. compatible = "fixed-clock";
  525. reg = <21>;
  526. clock-frequency = <24000000>;
  527. #clock-cells = <0>;
  528. };
  529. dummy_clock_vipre: vipre-dummy-clock@22 {
  530. compatible = "fixed-clock";
  531. reg = <22>;
  532. clock-frequency = <13000000>;
  533. #clock-cells = <0>;
  534. };
  535. dummy_clock_vpsys: vpsys-dummy-clock@23 {
  536. compatible = "fixed-clock";
  537. reg = <23>;
  538. clock-frequency = <24000000>;
  539. #clock-cells = <0>;
  540. };
  541. };
  542. iso7816: iso7816-card@fff7f30000 {
  543. compatible = "thead,light-iso7816-card";
  544. reg = <0xff 0xf7f30000 0x0 0x4000>;
  545. pinctrl-names = "default";
  546. pinctrl-0 = <&pinctrl_iso7816>;
  547. interrupts = <69>;
  548. interrupt-parent = <&intc>;
  549. status = "disabled";
  550. };
  551. teesys_syscon: teesys-reg@ffff200000 {
  552. compatible = "syscon";
  553. reg = <0xff 0xff200000 0x0 0x10000>;
  554. };
  555. visys_reg: visys-reg@ffe4040000 {
  556. compatible = "thead,light-visys-reg", "syscon";
  557. reg = <0xff 0xe4040000 0x0 0x1000>;
  558. status = "disabled";
  559. };
  560. dspsys_reg: dspsys-reg@ffef040000 {
  561. compatible = "thead,light-dspsys-reg", "syscon";
  562. reg = <0xff 0xef040000 0x0 0x1000>;
  563. status = "okay";
  564. };
  565. audio_ioctrl: audio_ioctrl@ffcb01d000 {
  566. compatible = "thead,light-audio-ioctrl-reg", "syscon";
  567. reg = <0xff 0xcb01d000 0x0 0x1000>;
  568. status = "okay";
  569. };
  570. audio_cpr: audio_cpr@ffcb000000 {
  571. compatible = "thead,light-audio-cpr-reg", "syscon";
  572. reg = <0xff 0xcb000000 0x0 0x1000>;
  573. status = "okay";
  574. };
  575. nvmem_controller: efuse@ffff210000 {
  576. compatible = "thead,light-fm-efuse", "syscon";
  577. reg = <0xff 0xff210000 0x0 0x10000>;
  578. thead,teesys = <&teesys_syscon>;
  579. #address-cells = <1>;
  580. #size-cells = <1>;
  581. gmac0_mac_address: mac-address@176 {
  582. reg = <0xb0 6>;
  583. };
  584. };
  585. misc_sysreg: misc_sysreg@ffec02c000 {
  586. compatible = "thead,light-misc-sysreg", "syscon";
  587. reg = <0xff 0xec02c000 0x0 0x1000>;
  588. status = "okay";
  589. };
  590. usb3_drd: usb3_drd@ffec03f000 {
  591. compatible = "thead,light-usb3-drd", "syscon";
  592. reg = <0xff 0xec03f000 0x0 0x1000>;
  593. status = "okay";
  594. };
  595. gpio0: gpio@ffec005000 {
  596. compatible = "snps,dw-apb-gpio";
  597. reg = <0xff 0xec005000 0x0 0x1000>;
  598. #address-cells = <1>;
  599. #size-cells = <0>;
  600. gpio0_porta: gpio0-controller@0 {
  601. compatible = "snps,dw-apb-gpio-port";
  602. gpio-controller;
  603. #gpio-cells = <2>;
  604. nr-gpios-snps = <32>;
  605. reg = <0>;
  606. interrupt-controller;
  607. #interrupt-cells = <2>;
  608. interrupt-parent = <&intc>;
  609. interrupts = <56>;
  610. };
  611. };
  612. gpio1: gpio@ffec006000 {
  613. compatible = "snps,dw-apb-gpio";
  614. reg = <0xff 0xec006000 0x0 0x1000>;
  615. #address-cells = <1>;
  616. #size-cells = <0>;
  617. gpio1_porta: gpio1-controller@0 {
  618. compatible = "snps,dw-apb-gpio-port";
  619. gpio-controller;
  620. #gpio-cells = <2>;
  621. nr-gpios-snps = <32>;
  622. reg = <0>;
  623. interrupt-controller;
  624. #interrupt-cells = <2>;
  625. interrupt-parent = <&intc>;
  626. interrupts = <57>;
  627. };
  628. };
  629. gpio2: gpio@ffe7f34000 {
  630. compatible = "snps,dw-apb-gpio";
  631. reg = <0xff 0xe7f34000 0x0 0x1000>;
  632. #address-cells = <1>;
  633. #size-cells = <0>;
  634. gpio2_porta: gpio2-controller@0 {
  635. compatible = "snps,dw-apb-gpio-port";
  636. gpio-controller;
  637. #gpio-cells = <2>;
  638. nr-gpios-snps = <32>;
  639. reg = <0>;
  640. interrupt-controller;
  641. #interrupt-cells = <2>;
  642. interrupt-parent = <&intc>;
  643. interrupts = <58>;
  644. };
  645. };
  646. gpio3: gpio@ffe7f38000 {
  647. compatible = "snps,dw-apb-gpio";
  648. reg = <0xff 0xe7f38000 0x0 0x1000>;
  649. #address-cells = <1>;
  650. #size-cells = <0>;
  651. gpio3_porta: gpio3-controller@0 {
  652. compatible = "snps,dw-apb-gpio-port";
  653. gpio-controller;
  654. #gpio-cells = <2>;
  655. nr-gpios-snps = <32>;
  656. reg = <0>;
  657. interrupt-controller;
  658. #interrupt-cells = <2>;
  659. interrupt-parent = <&intc>;
  660. interrupts = <59>;
  661. };
  662. };
  663. ao_gpio: gpio@fffff41000 {
  664. compatible = "snps,dw-apb-gpio";
  665. reg = <0xff 0xfff41000 0x0 0x1000>;
  666. #address-cells = <1>;
  667. #size-cells = <0>;
  668. ao_gpio_porta: ao_gpio-controller@0 {
  669. compatible = "snps,dw-apb-gpio-port";
  670. gpio-controller;
  671. #gpio-cells = <2>;
  672. nr-gpios-snps = <32>;
  673. reg = <0>;
  674. interrupt-controller;
  675. #interrupt-cells = <2>;
  676. interrupt-parent = <&intc>;
  677. interrupts = <76>;
  678. };
  679. };
  680. ao_gpio4: gpio@fffff52000 {
  681. compatible = "snps,dw-apb-gpio";
  682. reg = <0xff 0xfff52000 0x0 0x1000>;
  683. #address-cells = <1>;
  684. #size-cells = <0>;
  685. ao_gpio4_porta: ao_gpio4-controller@0 {
  686. compatible = "snps,dw-apb-gpio-port";
  687. gpio-controller;
  688. #gpio-cells = <2>;
  689. nr-gpios-snps = <32>;
  690. reg = <0>;
  691. interrupt-controller;
  692. #interrupt-cells = <2>;
  693. interrupt-parent = <&intc>;
  694. interrupts = <55>;
  695. };
  696. };
  697. padctrl1_apsys: pinctrl1-apsys@ffe7f3c000 {
  698. compatible = "thead,light-fm-left-pinctrl";
  699. reg = <0xff 0xe7f3c000 0x0 0x1000>;
  700. status = "okay";
  701. };
  702. padctrl0_apsys: padctrl0-apsys@ffec007000 {
  703. compatible = "thead,light-fm-right-pinctrl";
  704. reg = <0xff 0xec007000 0x0 0x1000>;
  705. status = "okay";
  706. };
  707. pwm: pwm@ffec01c000 {
  708. compatible = "thead,pwm-light";
  709. reg = <0xff 0xec01c000 0x0 0x4000>;
  710. #pwm-cells = <2>;
  711. clocks = <&dummy_clock_apb>;
  712. clock-names = "pwm";
  713. pinctrl-names = "default";
  714. pinctrl-0 = <&pinctrl_pwm>;
  715. };
  716. timer0: timer@ffefc32000 {
  717. compatible = "snps,dw-apb-timer";
  718. reg = <0xff 0xefc32000 0x0 0x14>;
  719. clocks = <&dummy_clock_apb>;
  720. clock-names = "timer";
  721. clock-frequency = <50000000>;
  722. interrupts = <16>;
  723. interrupt-parent = <&intc>;
  724. status = "okay";
  725. };
  726. timer1: timer@ffefc32014 {
  727. compatible = "snps,dw-apb-timer";
  728. reg = <0xff 0xefc32014 0x0 0x14>;
  729. clocks = <&dummy_clock_apb>;
  730. clock-names = "timer";
  731. clock-frequency = <50000000>;
  732. interrupts = <17>;
  733. interrupt-parent = <&intc>;
  734. status = "okay";
  735. };
  736. timer2: timer@ffefc32028 {
  737. compatible = "snps,dw-apb-timer";
  738. reg = <0xff 0xefc32028 0x0 0x14>;
  739. clocks = <&dummy_clock_apb>;
  740. clock-names = "timer";
  741. clock-frequency = <50000000>;
  742. interrupts = <18>;
  743. interrupt-parent = <&intc>;
  744. status = "disabled";
  745. };
  746. timer3: timer@ffefc3203c {
  747. compatible = "snps,dw-apb-timer";
  748. reg = <0xff 0xefc3203c 0x0 0x14>;
  749. clocks = <&dummy_clock_apb>;
  750. clock-names = "timer";
  751. clock-frequency = <50000000>;
  752. interrupts = <19>;
  753. interrupt-parent = <&intc>;
  754. status = "disabled";
  755. };
  756. padctrl_aosys: padctrl-aosys@fffff4a000 {
  757. compatible = "thead,light-fm-aon-pinctrl";
  758. reg = <0xff 0xfff4a000 0x0 0x2000>;
  759. status = "disabled";
  760. };
  761. timer4: timer@ffffc33000 {
  762. compatible = "snps,dw-apb-timer";
  763. reg = <0xff 0xffc33000 0x0 0x14>;
  764. clocks = <&dummy_clock_apb>;
  765. clock-names = "timer";
  766. clock-frequency = <50000000>;
  767. interrupts = <20>;
  768. interrupt-parent = <&intc>;
  769. status = "disabled";
  770. };
  771. timer5: timer@ffffc33014 {
  772. compatible = "snps,dw-apb-timer";
  773. reg = <0xff 0xffc33014 0x0 0x14>;
  774. clocks = <&dummy_clock_apb>;
  775. clock-names = "timer";
  776. clock-frequency = <50000000>;
  777. interrupts = <21>;
  778. interrupt-parent = <&intc>;
  779. status = "disabled";
  780. };
  781. timer6: timer@ffffc33028 {
  782. compatible = "snps,dw-apb-timer";
  783. reg = <0xff 0xffc33028 0x0 0x14>;
  784. clocks = <&dummy_clock_apb>;
  785. clock-names = "timer";
  786. clock-frequency = <50000000>;
  787. interrupts = <22>;
  788. interrupt-parent = <&intc>;
  789. status = "disabled";
  790. };
  791. timer7: timer@ffffc3303c {
  792. compatible = "snps,dw-apb-timer";
  793. reg = <0xff 0xffc3303c 0x0 0x14>;
  794. clocks = <&dummy_clock_apb>;
  795. clock-names = "timer";
  796. clock-frequency = <50000000>;
  797. interrupts = <23>;
  798. interrupt-parent = <&intc>;
  799. status = "disabled";
  800. };
  801. uart0: serial@ffe7014000 { /* Normal serial, for C910 log */
  802. compatible = "snps,dw-apb-uart";
  803. reg = <0xff 0xe7014000 0x0 0x4000>;
  804. interrupt-parent = <&intc>;
  805. interrupts = <36>;
  806. clocks = <&dummy_clock_uart>;
  807. clock-names = "baudclk";
  808. reg-shift = <2>;
  809. reg-io-width = <4>;
  810. hw-flow-control = "unsupport";
  811. status = "okay";
  812. };
  813. uart1: serial@ffe7f00000 { /* Normal serial, for C902 log */
  814. compatible = "snps,dw-apb-uart";
  815. reg = <0xff 0xe7f00000 0x0 0x4000>;
  816. interrupt-parent = <&intc>;
  817. interrupts = <37>;
  818. clocks = <&dummy_clock_uart>;
  819. clock-names = "baudclk";
  820. reg-shift = <2>;
  821. reg-io-width = <4>;
  822. hw-flow-control = "unsupport";
  823. status = "okay";
  824. };
  825. uart2: serial@ffec010000 { /* IRDA supported serial, not in 85P bit */
  826. compatible = "snps,dw-apb-uart";
  827. reg = <0xff 0xec010000 0x0 0x4000>;
  828. interrupt-parent = <&intc>;
  829. interrupts = <38>;
  830. clocks = <&dummy_clock_uart>;
  831. clock-names = "baudclk";
  832. reg-shift = <2>;
  833. reg-io-width = <4>;
  834. hw-flow-control = "unsupport";
  835. status = "disabled";
  836. };
  837. uart3: serial@ffe7f04000 { /* IRDA supported serial, not in 85P bit */
  838. compatible = "snps,dw-apb-uart";
  839. reg = <0xff 0xe7f04000 0x0 0x4000>;
  840. interrupt-parent = <&intc>;
  841. interrupts = <39>;
  842. clocks = <&dummy_clock_uart>;
  843. clock-names = "baudclk";
  844. reg-shift = <2>;
  845. reg-io-width = <4>;
  846. hw-flow-control = "unsupport";
  847. status = "disabled";
  848. };
  849. uart4: serial@fff7f08000 { /* High Speed with Flow Ctrol serial */
  850. compatible = "snps,dw-apb-uart";
  851. reg = <0xff 0xf7f08000 0x0 0x4000>;
  852. interrupt-parent = <&intc>;
  853. interrupts = <40>;
  854. clocks = <&dummy_clock_uart>;
  855. clock-names = "baudclk";
  856. reg-shift = <2>;
  857. reg-io-width = <4>;
  858. hw-flow-control = "support";
  859. status = "okay";
  860. };
  861. uart5: serial@fff7f0c000 { /* Normal serial, for external SE, not in 85P bit */
  862. compatible = "snps,dw-apb-uart";
  863. reg = <0xff 0xf7f0c000 0x0 0x4000>;
  864. interrupt-parent = <&intc>;
  865. interrupts = <41>;
  866. clocks = <&dummy_clock_uart>;
  867. clock-names = "baudclk";
  868. reg-shift = <2>;
  869. reg-io-width = <4>;
  870. hw-flow-control = "unsupport";
  871. status = "disabled";
  872. };
  873. adc: adc@0xfffff51000 {
  874. compatible = "thead,light-adc";
  875. reg = <0xff 0xfff51000 0x0 0x1000>;
  876. interrupt-parent = <&intc>;
  877. interrupts = <61>;
  878. clocks = <&dummy_clock_aonsys_clk>;
  879. clock-names = "adc";
  880. /* ADC pin is proprietary,no need to config pinctrl */
  881. status = "disabled";
  882. };
  883. spi0: spi@ffe700c000 {
  884. compatible = "snps,dw-apb-ssi";
  885. reg = <0xff 0xe700c000 0x0 0x1000>;
  886. pinctrl-names = "default";
  887. pinctrl-0 = <&pinctrl_spi0>;
  888. interrupt-parent = <&intc>;
  889. interrupts = <54>;
  890. clocks = <&dummy_clock_spi>;
  891. num-cs = <2>;
  892. #address-cells = <1>;
  893. #size-cells = <0>;
  894. };
  895. qspi0: spi@ffea000000 {
  896. compatible = "snps,dw-apb-ssi-quad";
  897. reg = <0xff 0xea000000 0x0 0x1000>;
  898. pinctrl-names = "default";
  899. pinctrl-0 = <&pinctrl_qspi0>;
  900. interrupt-parent = <&intc>;
  901. interrupts = <52>;
  902. clocks = <&dummy_clock_qspi>;
  903. #address-cells = <1>;
  904. #size-cells = <0>;
  905. };
  906. qspi1: spi@fff8000000 {
  907. compatible = "snps,dw-apb-ssi-quad";
  908. reg = <0xff 0xf8000000 0x0 0x1000>;
  909. pinctrl-names = "default";
  910. pinctrl-0 = <&pinctrl_qspi1>;
  911. interrupt-parent = <&intc>;
  912. interrupts = <53>;
  913. clocks = <&dummy_clock_spi>;
  914. #address-cells = <1>;
  915. #size-cells = <0>;
  916. };
  917. g2d: gc620@ffecc80000 {
  918. compatible = "thead,c910-gc620";
  919. reg = <0xff 0xecc80000 0x0 0x40000>;
  920. interrupt-parent = <&intc>;
  921. interrupts = <101>;
  922. interrupt-names = "irq_2d";
  923. clocks = <&dummy_clock_vpsys>,
  924. <&dummy_clock_vpsys>,
  925. <&dummy_clock_vpsys>;
  926. clock-names = "pclk", "aclk", "cclk";
  927. status = "okay";
  928. };
  929. dsi0: dw-mipi-dsi0@ffef500000 {
  930. compatible = "thead,light-mipi-dsi", "simple-bus", "syscon";
  931. reg = <0xff 0xef500000 0x0 0x10000>;
  932. status = "disabled";
  933. dphy_0: dsi0-dphy {
  934. compatible = "thead,light-mipi-dphy";
  935. regmap = <&dsi0>;
  936. vosys-regmap = <&vosys_reg>;
  937. clocks = <&dummy_clock_dphy_ref>,
  938. <&dummy_clock_dphy_cfg>,
  939. <&dummy_clock_dphy_ref>,
  940. <&dummy_clock_dpu_pixel0>,
  941. <&dummy_clock_dphy_cfg>;
  942. clock-names = "refclk", "cfgclk", "pclk", "prefclk", "pcfgclk";
  943. #phy-cells = <0>;
  944. };
  945. dhost_0: dsi0-host {
  946. compatible = "verisilicon,dw-mipi-dsi";
  947. regmap = <&dsi0>;
  948. interrupt-parent = <&intc>;
  949. interrupts = <129>;
  950. clocks = <&dummy_clock_dphy_cfg>,
  951. <&dummy_clock_dpu_pixel0>;
  952. clock-names = "pclk", "pixclk";
  953. phys = <&dphy_0>;
  954. phy-names = "dphy";
  955. #address-cells = <1>;
  956. #size-cells = <0>;
  957. };
  958. };
  959. dsi1: dw-mipi-dsi1@ffef510000 {
  960. compatible = "thead,light-mipi-dsi", "simple-bus", "syscon";
  961. reg = <0xff 0xef510000 0x0 0x10000>;
  962. status = "disabled";
  963. dphy_1: dsi1-dphy {
  964. compatible = "thead,light-mipi-dphy";
  965. regmap = <&dsi1>;
  966. vosys-regmap = <&vosys_reg>;
  967. clocks = <&dummy_clock_dphy_ref>,
  968. <&dummy_clock_dphy_cfg>,
  969. <&dummy_clock_dphy_ref>,
  970. <&dummy_clock_dpu_pixel1>,
  971. <&dummy_clock_dphy_cfg>;
  972. clock-names = "refclk", "cfgclk", "pclk", "prefclk", "pcfgclk";
  973. #phy-cells = <0>;
  974. };
  975. dhost_1: dsi1-host {
  976. compatible = "verisilicon,dw-mipi-dsi";
  977. regmap = <&dsi1>;
  978. interrupt-parent = <&intc>;
  979. interrupts = <129>;
  980. clocks = <&dummy_clock_dphy_cfg>,
  981. <&dummy_clock_dpu_pixel1>;
  982. clock-names = "pclk", "pixclk";
  983. phys = <&dphy_1>;
  984. phy-names = "dphy";
  985. #address-cells = <1>;
  986. #size-cells = <0>;
  987. };
  988. };
  989. vosys_reg: vosys@ffef528000 {
  990. compatible = "thead,light-vo-subsys", "syscon";
  991. reg = <0xff 0xef528000 0x0 0x1000>;
  992. status = "okay";
  993. };
  994. hdmi_tx: dw-hdmi-tx@ffef540000 {
  995. compatible = "thead,light-hdmi-tx";
  996. reg = <0xff 0xef540000 0x0 0x40000>;
  997. interrupt-parent = <&intc>;
  998. interrupts = <111>;
  999. clocks = <&dummy_clock_dpu_pixel0>,
  1000. <&dummy_clock_dpu_pixel0>,
  1001. <&dummy_clock_dpu_pixel0>,
  1002. <&dummy_clock_dpu_pixel0>,
  1003. <&dummy_clock_dpu_pixel0>;
  1004. clock-names = "iahb", "isfr", "cec", "pixclk", "i2s";
  1005. reg-io-width = <4>;
  1006. phy_version = <301>;
  1007. /* TODO: add phy property */
  1008. status = "disabled";
  1009. };
  1010. dpu: dc8200@ffef600000 {
  1011. compatible = "verisilicon,dc8200";
  1012. #address-cells = <1>;
  1013. #size-cells = <0>;
  1014. reg = <0xff 0xef600000 0x0 0x100>,
  1015. <0xff 0xef600800 0x0 0x2000>,
  1016. <0xff 0xef630010 0x0 0x60>;
  1017. interrupt-parent = <&intc>;
  1018. interrupts = <93>;
  1019. clocks = <&dummy_clock_dpu_pixel0>,
  1020. <&dummy_clock_dpu_pixel0>,
  1021. <&dummy_clock_dpu_pixel0>,
  1022. <&dummy_clock_dpu_pixel0>,
  1023. <&dummy_clock_dpu_pixel0>,
  1024. <&dummy_clock_dpu_pixel0>,
  1025. <&dummy_clock_dpu_pixel0>,
  1026. <&dummy_clock_dpu_pixel0>,
  1027. <&dummy_clock_dpu_pixel0>;
  1028. clock-names = "core_clk", "pix_clk0", "pix_clk1",
  1029. "axi_clk", "cfg_clk", "pixclk0",
  1030. "pixclk1", "dpu0_pll_foutpostdiv",
  1031. "dpu1_pll_foutpostdiv";
  1032. status = "disabled";
  1033. dpu_disp0: port@0 {
  1034. reg = <0>;
  1035. disp0_out: endpoint {
  1036. remote-endpoint = <&enc0_in>;
  1037. };
  1038. };
  1039. dpu_disp1: port@1 {
  1040. reg = <1>;
  1041. disp1_out: endpoint {
  1042. remote-endpoint = <&enc1_in>;
  1043. };
  1044. };
  1045. };
  1046. watchdog0: watchdog@ffefc30000 {
  1047. compatible = "snps,dw-wdt";
  1048. reg = <0xff 0xefc30000 0x0 0x1000>;
  1049. interrupt-parent = <&intc>;
  1050. interrupts = <24>;
  1051. clocks = <&dummy_clock_apb>;
  1052. clock-names = "tclk";
  1053. resets = <&rst LIGHT_RESET_WDT0>;
  1054. status = "okay";
  1055. };
  1056. watchdog1: watchdog@ffefc31000 {
  1057. compatible = "snps,dw-wdt";
  1058. reg = <0xff 0xefc31000 0x0 0x1000>;
  1059. interrupt-parent = <&intc>;
  1060. interrupts = <25>;
  1061. clocks = <&dummy_clock_apb>;
  1062. clock-names = "tclk";
  1063. resets = <&rst LIGHT_RESET_WDT1>;
  1064. status = "okay";
  1065. };
  1066. rtc: rtc@fffff40000 {
  1067. compatible = "apm,xgene-rtc";
  1068. reg = <0xff 0xfff40000 0x0 0x1000>;
  1069. interrupt-parent = <&intc>;
  1070. interrupts = <74>;
  1071. clocks = <&dummy_clock_rtc>;
  1072. clock-names = "rtc";
  1073. status = "okay";
  1074. };
  1075. usb_1: usb@ffec03f000 {
  1076. compatible = "thead,dwc3";
  1077. usb3-misc-regmap = <&misc_sysreg>;
  1078. usb3-drd-regmap = <&usb3_drd>;
  1079. #address-cells = <2>;
  1080. #size-cells = <2>;
  1081. ranges;
  1082. usb: dwc3@ffe7040000 {
  1083. compatible = "snps,dwc3";
  1084. reg = <0xff 0xe7040000 0x0 0x10000>;
  1085. interrupt-parent = <&intc>;
  1086. interrupts = <68>;
  1087. clocks = <&dummy_clock_ref>, <&dummy_clock_apb>, <&dummy_clock_suspend>;
  1088. clock-names = "ref", "bus_early", "suspend";
  1089. reg-shift = <2>;
  1090. reg-io-width = <4>;
  1091. maximum-speed = "super-speed";
  1092. dr_mode = "host";
  1093. dma-mask = <0xf 0xffffffff>;
  1094. snps,usb3_lpm_capable;
  1095. snps,usb_sofitpsync;
  1096. status = "disabled";
  1097. };
  1098. };
  1099. pmu: pmu {
  1100. interrupt-parent = <&cpu0_intc>;
  1101. interrupts = <17>;
  1102. compatible = "riscv,c910_pmu";
  1103. };
  1104. clk: clock-controller@ffef010000 {
  1105. compatible = "thead,light-fm-ree-clk";
  1106. reg = <0xff 0xef010000 0x0 0x1000>;
  1107. #clock-cells = <1>;
  1108. clocks = <&osc_32k>, <&osc_24m>, <&rc_24m>;
  1109. clock-names = "osc_32k", "osc_24m", "rc_24m";
  1110. status = "okay";
  1111. };
  1112. rst: reset-controller@ffef014000 {
  1113. compatible = "thead,light-reset-src","syscon";
  1114. reg = <0xff 0xef014000 0x0 0x1000>;
  1115. #reset-cells = <1>;
  1116. status = "okay";
  1117. };
  1118. sys_reg: sys_reg@ffef010100 {
  1119. compatible = "thead,light_sys_reg";
  1120. reg = <0xff 0xef010100 0x0 0x100>;
  1121. status = "okay";
  1122. };
  1123. dmac0: dmac@ffefc00000 {
  1124. compatible = "snps,axi-dma-1.01a";
  1125. reg = <0xff 0xefc00000 0x0 0x1000>;
  1126. interrupt-parent = <&intc>;
  1127. interrupts = <27>;
  1128. clocks = <&dummy_clock_apb>, <&dummy_clock_apb>;
  1129. clock-names = "core-clk", "cfgr-clk";
  1130. #dma-cells = <1>;
  1131. dma-channels = <4>;
  1132. snps,block-size = <65536 65536 65536 65536>;
  1133. snps,priority = <0 1 2 3>;
  1134. snps,dma-masters = <1>;
  1135. snps,data-width = <4>;
  1136. snps,axi-max-burst-len = <16>;
  1137. status = "okay";
  1138. };
  1139. dmac1: tee_dmac@ffff340000 {
  1140. compatible = "snps,axi-dma-1.01a";
  1141. reg = <0xff 0xff340000 0x0 0x1000>;
  1142. interrupt-parent = <&intc>;
  1143. interrupts = <150>;
  1144. clocks = <&dummy_clock_apb>, <&dummy_clock_apb>;
  1145. clock-names = "core-clk", "cfgr-clk";
  1146. #dma-cells = <1>;
  1147. dma-channels = <4>;
  1148. snps,block-size = <65536 65536 65536 65536>;
  1149. snps,priority = <0 1 2 3>;
  1150. snps,dma-masters = <1>;
  1151. snps,data-width = <4>;
  1152. snps,axi-max-burst-len = <16>;
  1153. status = "disabled";
  1154. };
  1155. dmac2: audio_dmac@0xFFC8000000 {
  1156. compatible = "snps,axi-dma-1.01a";
  1157. reg = <0xff 0xc8000000 0x0 0x2000>;
  1158. interrupt-parent = <&intc>;
  1159. interrupts = <167>;
  1160. clocks = <&dummy_clock_apb>, <&dummy_clock_apb>;
  1161. clock-names = "core-clk", "cfgr-clk";
  1162. #dma-cells = <1>;
  1163. dma-channels = <16>;
  1164. snps,block-size = <65536 65536 65536 65536
  1165. 65536 65536 65536 65536
  1166. 65536 65536 65536 65536
  1167. 65536 65536 65536 65536>;
  1168. snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
  1169. snps,dma-masters = <1>;
  1170. snps,data-width = <4>;
  1171. snps,axi-max-burst-len = <16>;
  1172. status = "okay";
  1173. };
  1174. stmmac_axi_setup: stmmac-axi-config {
  1175. snps,wr_osr_lmt = <3>;
  1176. snps,rd_osr_lmt = <3>;
  1177. snps,blen = <16 8 4 0 0 0 0>;
  1178. };
  1179. gmac0: ethernet@ffe7070000 {
  1180. compatible = "thead,light-dwmac";
  1181. reg = <0xff 0xe7070000 0x0 0x2000
  1182. 0xff 0xec00301c 0x0 0x4
  1183. 0xff 0xec003020 0x0 0x4
  1184. 0xff 0xec003000 0x0 0x1c>;
  1185. reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg";
  1186. interrupt-parent = <&intc>;
  1187. interrupts = <66>;
  1188. interrupt-names = "macirq";
  1189. clocks = <&dummy_clock_gmac>;
  1190. clock-names = "gmac_pll_clk";
  1191. snps,pbl = <32>;
  1192. snps,fixed-burst;
  1193. snps,axi-config = <&stmmac_axi_setup>;
  1194. nvmem-cells = <&gmac0_mac_address>;
  1195. nvmem-cell-names = "mac-address";
  1196. };
  1197. emmc: sdhci@ffe7080000 {
  1198. compatible = "snps,dwcmshc-sdhci";
  1199. reg = <0xff 0xe7080000 0x0 0x10000
  1200. 0xff 0xef014060 0x0 0x4>;
  1201. interrupt-parent = <&intc>;
  1202. interrupts = <62>;
  1203. interrupt-names = "sdhciirq";
  1204. clocks = <&dummy_clock_sdhci>;
  1205. clock-names = "core";
  1206. };
  1207. sdhci0: sd@ffe7090000 {
  1208. compatible = "snps,dwcmshc-sdhci";
  1209. reg = <0xff 0xe7090000 0x0 0x10000
  1210. 0xff 0xef014064 0x0 0x4>;
  1211. interrupt-parent = <&intc>;
  1212. interrupts = <64>;
  1213. interrupt-names = "sdhci0irq";
  1214. clocks = <&dummy_clock_sdhci>;
  1215. clock-names = "core";
  1216. };
  1217. sdhci1: sd@ffe70a0000 {
  1218. compatible = "snps,dwcmshc-sdhci";
  1219. reg = <0xff 0xe70a0000 0x0 0x10000
  1220. 0xff 0xef014064 0x0 0x4>;
  1221. interrupt-parent = <&intc>;
  1222. interrupts = <71>;
  1223. interrupt-names = "sdhci1irq";
  1224. clocks = <&dummy_clock_sdhci>;
  1225. clock-names = "core";
  1226. };
  1227. hwspinlock: hwspinlock@ffefc10000 {
  1228. compatible = "light,hwspinlock";
  1229. reg = <0xff 0xefc10000 0x0 0x10000>;
  1230. status = "disabled";
  1231. };
  1232. gpu: gpu@ffef400000 {
  1233. compatible = "img,gpu";
  1234. reg = <0xff 0xef400000 0x0 0x100000>;
  1235. interrupt-parent = <&intc>;
  1236. interrupts = <102>;
  1237. interrupt-names = "gpuirq";
  1238. vosys-regmap = <&vosys_reg>;
  1239. //power-domains = <&pd LIGHT_AON_GPU_PD>;
  1240. clocks = <&dummy_clock_gpu>,
  1241. <&dummy_clock_gpu>;
  1242. clock-names = "cclk", "aclk";
  1243. gpu_clk_rate = <18000000>;
  1244. dma-mask = <0xf 0xffffffff>;
  1245. status = "disabled";
  1246. };
  1247. vdec: vdec@ffecc00000 {
  1248. compatible = "thead,light-vc8000d";
  1249. reg = <0xff 0xecc00000 0x0 0x8000>;
  1250. interrupt-parent = <&intc>;
  1251. interrupts = <131>;
  1252. //power-domains = <&pd LIGHT_AON_VDEC_PD>;
  1253. clocks = <&dummy_clock_vpsys>,
  1254. <&dummy_clock_vpsys>,
  1255. <&dummy_clock_vpsys>;
  1256. clock-names = "aclk", "cclk", "pclk";
  1257. status = "disabled";
  1258. };
  1259. venc: venc@ffecc10000 {
  1260. compatible = "thead,light-vc8000e";
  1261. reg = <0xff 0xecc10000 0x0 0x8000>;
  1262. interrupt-parent = <&intc>;
  1263. interrupts = <133>;
  1264. //power-domains = <&pd LIGHT_AON_VENC_PD>;
  1265. clocks = <&dummy_clock_vpsys>,
  1266. <&dummy_clock_vpsys>,
  1267. <&dummy_clock_vpsys>;
  1268. clock-names = "aclk", "cclk", "pclk";
  1269. status = "disabled";
  1270. };
  1271. isp_venc_shake: shake@ffe4078000 {
  1272. compatible = "thead,light-ivs";
  1273. reg = <0xff 0xe4078000 0x0 0x1000>;
  1274. interrupt-parent = <&intc>;
  1275. interrupts = <158>;
  1276. status = "disabled";
  1277. };
  1278. vidmem: vidmem@ffecc08000 {
  1279. compatible = "thead,light-vidmem";
  1280. reg = <0xff 0xecc08000 0x0 0x1000>;
  1281. status = "okay";
  1282. };
  1283. light_i2s: light_i2s@ffe7034000 {
  1284. #sound-dai-cells = <1>;
  1285. compatible = "light,light-i2s";
  1286. reg = <0xff 0xe7034000 0x0 0x4000>;
  1287. pinctrl-names = "default";
  1288. pinctrl-0 = <&pinctrl_audio_i2s0>;
  1289. light,mode = "i2s-master";
  1290. light,sel = "ap_i2s";
  1291. interrupt-parent = <&intc>;
  1292. interrupts = <70>;
  1293. dmas = <&dmac0 35>, <&dmac0 40>;
  1294. dma-names = "tx", "rx";
  1295. light,dma_maxburst = <4>;
  1296. #dma-cells = <1>;
  1297. clocks = <&dummy_clock_apb>;
  1298. clock-names = "pclk";
  1299. status = "disabled";
  1300. };
  1301. i2s0: audio_i2s0@0xffcb014000 {
  1302. #sound-dai-cells = <1>;
  1303. compatible = "light,light-i2s";
  1304. reg = <0xff 0xcb014000 0x0 0x1000>;
  1305. audio-pin-regmap = <&audio_ioctrl>;
  1306. audio-cpr-regmap = <&audio_cpr>;
  1307. pinctrl-names = "default";
  1308. light,mode = "i2s-master";
  1309. light,sel = "i2s0";
  1310. interrupt-parent = <&intc>;
  1311. interrupts = <174>;
  1312. dmas = <&dmac2 9>, <&dmac2 16>;
  1313. dma-names = "tx", "rx";
  1314. light,dma_maxburst = <4>;
  1315. #dma-cells = <1>;
  1316. clocks = <&dummy_clock_apb>;
  1317. clock-names = "pclk";
  1318. status = "disabled";
  1319. };
  1320. i2s1: audio_i2s1@0xffcb015000 {
  1321. #sound-dai-cells = <1>;
  1322. compatible = "light,light-i2s";
  1323. reg = <0xff 0xcb015000 0x0 0x1000>;
  1324. audio-pin-regmap = <&audio_ioctrl>;
  1325. audio-cpr-regmap = <&audio_cpr>;
  1326. pinctrl-names = "default";
  1327. light,mode = "i2s-master";
  1328. light,sel = "i2s1";
  1329. interrupt-parent = <&intc>;
  1330. interrupts = <175>;
  1331. dmas = <&dmac2 11>, <&dmac2 17>;
  1332. dma-names = "tx", "rx";
  1333. light,dma_maxburst = <4>;
  1334. #dma-cells = <1>;
  1335. clocks = <&dummy_clock_apb>;
  1336. clock-names = "pclk";
  1337. status = "disabled";
  1338. };
  1339. i2s3: audio_i2s3@0xffcb017000 {
  1340. #sound-dai-cells = <1>;
  1341. compatible = "light,light-i2s";
  1342. reg = <0xff 0xcb017000 0x0 0x1000>;
  1343. pinctrl-names = "default";
  1344. light,mode = "i2s-master";
  1345. light,sel = "i2s3";
  1346. interrupt-parent = <&intc>;
  1347. interrupts = <177>;
  1348. dmas = <&dmac2 14>, <&dmac2 16>;
  1349. dma-names = "tx", "rx";
  1350. light,dma_maxburst = <4>;
  1351. #dma-cells = <1>;
  1352. clocks = <&dummy_clock_apb>;
  1353. clock-names = "pclk";
  1354. status = "disabled";
  1355. };
  1356. pvt: pvt@fffff4e000 {
  1357. compatible = "moortec,mr75203";
  1358. reg = <0xff 0xfff4e000 0x0 0x80>,
  1359. <0xff 0xfff4e080 0x0 0x100>,
  1360. <0xff 0xfff4e180 0x0 0x680>,
  1361. <0xff 0xfff4e800 0x0 0x600>;
  1362. reg-names = "common", "ts", "pd", "vm";
  1363. clocks = <&dummy_clock_aonsys_clk>;
  1364. #thermal-sensor-cells = <1>;
  1365. status = "disabled";
  1366. };
  1367. i2c0: i2c@ffe7f20000 {
  1368. compatible = "snps,designware-i2c";
  1369. reg = <0xff 0xe7f20000 0x0 0x4000>;
  1370. interrupt-parent = <&intc>;
  1371. interrupts = <44>;
  1372. clocks = <&dummy_clock_apb>;
  1373. clock-frequency = <100000>;
  1374. ss_hcnt = /bits/ 16 <0x104>;
  1375. ss_lcnt = /bits/ 16 <0xec>;
  1376. fs_hcnt = /bits/ 16 <0x37>;
  1377. fs_lcnt = /bits/ 16 <0x42>;
  1378. fp_hcnt = /bits/ 16 <0x14>;
  1379. fp_lcnt = /bits/ 16 <0x1a>;
  1380. hs_hcnt = /bits/ 16 <0x9>;
  1381. hs_lcnt = /bits/ 16 <0x11>;
  1382. #address-cells = <1>;
  1383. #size-cells = <0>;
  1384. };
  1385. i2c1: i2c@ffe7f24000 {
  1386. compatible = "snps,designware-i2c";
  1387. reg = <0xff 0xe7f24000 0x0 0x4000>;
  1388. interrupt-parent = <&intc>;
  1389. interrupts = <45>;
  1390. clocks = <&dummy_clock_apb>;
  1391. clock-frequency = <100000>;
  1392. ss_hcnt = /bits/ 16 <0x104>;
  1393. ss_lcnt = /bits/ 16 <0xec>;
  1394. fs_hcnt = /bits/ 16 <0x37>;
  1395. fs_lcnt = /bits/ 16 <0x42>;
  1396. fp_hcnt = /bits/ 16 <0x14>;
  1397. fp_lcnt = /bits/ 16 <0x1a>;
  1398. hs_hcnt = /bits/ 16 <0x9>;
  1399. hs_lcnt = /bits/ 16 <0x11>;
  1400. #address-cells = <1>;
  1401. #size-cells = <0>;
  1402. };
  1403. i2c2: i2c@ffec00c000{
  1404. compatible = "snps,designware-i2c";
  1405. reg = <0xff 0xec00c000 0x0 0x4000>;
  1406. interrupt-parent = <&intc>;
  1407. interrupts = <46>;
  1408. clocks = <&dummy_clock_apb>;
  1409. clock-frequency = <100000>;
  1410. ss_hcnt = /bits/ 16 <0x104>;
  1411. ss_lcnt = /bits/ 16 <0xec>;
  1412. fs_hcnt = /bits/ 16 <0x37>;
  1413. fs_lcnt = /bits/ 16 <0x42>;
  1414. fp_hcnt = /bits/ 16 <0x14>;
  1415. fp_lcnt = /bits/ 16 <0x1a>;
  1416. hs_hcnt = /bits/ 16 <0x9>;
  1417. hs_lcnt = /bits/ 16 <0x11>;
  1418. status = "disabled";
  1419. #address-cells = <1>;
  1420. #size-cells = <0>;
  1421. };
  1422. i2c3: i2c@ffec014000{
  1423. compatible = "snps,designware-i2c";
  1424. reg = <0xff 0xec014000 0x0 0x4000>;
  1425. interrupt-parent = <&intc>;
  1426. interrupts = <47>;
  1427. clocks = <&dummy_clock_apb>;
  1428. clock-frequency = <100000>;
  1429. ss_hcnt = /bits/ 16 <0x104>;
  1430. ss_lcnt = /bits/ 16 <0xec>;
  1431. fs_hcnt = /bits/ 16 <0x37>;
  1432. fs_lcnt = /bits/ 16 <0x42>;
  1433. fp_hcnt = /bits/ 16 <0x14>;
  1434. fp_lcnt = /bits/ 16 <0x1a>;
  1435. hs_hcnt = /bits/ 16 <0x9>;
  1436. hs_lcnt = /bits/ 16 <0x11>;
  1437. status = "disabled";
  1438. #address-cells = <1>;
  1439. #size-cells = <0>;
  1440. };
  1441. i2c4: i2c@ffe7f28000{
  1442. compatible = "snps,designware-i2c";
  1443. reg = <0xff 0xe7f28000 0x0 0x4000>;
  1444. interrupt-parent = <&intc>;
  1445. interrupts = <48>;
  1446. clocks = <&dummy_clock_apb>;
  1447. clock-frequency = <100000>;
  1448. ss_hcnt = /bits/ 16 <0x104>;
  1449. ss_lcnt = /bits/ 16 <0xec>;
  1450. fs_hcnt = /bits/ 16 <0x37>;
  1451. fs_lcnt = /bits/ 16 <0x42>;
  1452. fp_hcnt = /bits/ 16 <0x14>;
  1453. fp_lcnt = /bits/ 16 <0x1a>;
  1454. hs_hcnt = /bits/ 16 <0x9>;
  1455. hs_lcnt = /bits/ 16 <0x11>;
  1456. status = "disabled";
  1457. #address-cells = <1>;
  1458. #size-cells = <0>;
  1459. };
  1460. audio_i2c0: i2c@0xffcb01a000 {
  1461. compatible = "snps,designware-i2c";
  1462. reg = <0xff 0xcb01a000 0x0 0x1000>;
  1463. interrupt-parent = <&intc>;
  1464. interrupts = <182>;
  1465. clocks = <&dummy_clock_apb>;
  1466. clock-frequency = <100000>;
  1467. ss_hcnt = /bits/ 16 <0x82>;
  1468. ss_lcnt = /bits/ 16 <0x78>;
  1469. fs_hcnt = /bits/ 16 <0x37>;
  1470. fs_lcnt = /bits/ 16 <0x42>;
  1471. fp_hcnt = /bits/ 16 <0x14>;
  1472. fp_lcnt = /bits/ 16 <0x1a>;
  1473. hs_hcnt = /bits/ 16 <0x5>;
  1474. hs_lcnt = /bits/ 16 <0x15>;
  1475. #address-cells = <1>;
  1476. #size-cells = <0>;
  1477. };
  1478. isp0: isp@ffe4100000 {
  1479. compatible = "thead,light-isp";
  1480. reg = <0xff 0xe4100000 0x0 0x10000>;
  1481. interrupt-parent = <&intc>;
  1482. interrupts = <117>,<118>;
  1483. clocks = <&dummy_clock_visys>,
  1484. <&dummy_clock_visys>,
  1485. <&dummy_clock_visys>,
  1486. <&dummy_clock_visys>;
  1487. clock-names = "aclk", "hclk", "isp0_pclk", "cclk";
  1488. status = "disabled";
  1489. };
  1490. isp1: isp@ffe4110000 {
  1491. compatible = "thead,light-isp";
  1492. reg = <0xff 0xe4110000 0x0 0x10000>;
  1493. interrupt-parent = <&intc>;
  1494. interrupts = <120>,<121>;
  1495. clocks = <&dummy_clock_visys>,
  1496. <&dummy_clock_visys>,
  1497. <&dummy_clock_visys>,
  1498. <&dummy_clock_visys>,
  1499. <&dummy_clock_visys>;
  1500. clock-names = "aclk", "hclk", "isp0_pclk", "cclk", "isp1_pclk";
  1501. status = "disabled";
  1502. };
  1503. isp_ry0: isp_ry@ffe4120000 {
  1504. compatible = "thead,light-isp_ry";
  1505. reg = <0xff 0xe4120000 0x0 0x10000>;
  1506. interrupt-parent = <&intc>;
  1507. interrupts = <123>,<124>;
  1508. clocks = <&dummy_clock_visys>,
  1509. <&dummy_clock_visys>,
  1510. <&dummy_clock_visys>;
  1511. clock-names = "aclk", "hclk", "cclk";
  1512. status = "disabled";
  1513. };
  1514. dewarp: dewarp@ffe4130000 {
  1515. compatible = "thead,light-dewarp";
  1516. reg = <0xff 0xe4130000 0x0 0x10000>;
  1517. interrupt-parent = <&intc>;
  1518. interrupts = <98>,<99>;
  1519. clocks = <&dummy_clock_visys>,
  1520. <&dummy_clock_visys>,
  1521. <&dummy_clock_visys>,
  1522. <&dummy_clock_visys>;
  1523. clock-names = "aclk", "hclk", "vseclk", "dweclk";
  1524. status = "disabled";
  1525. };
  1526. dec400_isp0: dec400@ffe4060000 {
  1527. compatible = "thead,dec400";
  1528. reg = <0xff 0xe4060000 0x0 0x8000>;
  1529. status = "disabled";
  1530. };
  1531. dec400_isp1: dec400@ffe4068000 {
  1532. compatible = "thead,dec400";
  1533. reg = <0xff 0xe4068000 0x0 0x8000>;
  1534. status = "disabled";
  1535. };
  1536. dec400_isp2: dec400@ffe4070000 {
  1537. compatible = "thead,dec400";
  1538. reg = <0xff 0xe4070000 0x0 0x8000>;
  1539. status = "disabled";
  1540. };
  1541. bm_visys: bm_visys@ffe4040000 {
  1542. compatible = "thead,light-bm-visys";
  1543. reg = <0xff 0xe4040000 0x0 0x1000>;
  1544. status = "disabled";
  1545. };
  1546. bm_csi0: csi@ffe4000000{ //CSI2
  1547. compatible = "thead,light-bm-csi";
  1548. reg = < 0xff 0xe4000000 0x0 0x10000>;
  1549. interrupt-parent = <&intc>;
  1550. interrupts = <128>;
  1551. dphyglueiftester = <0x180>;
  1552. sysreg_mipi_csi_ctrl = <0x140>;
  1553. clocks = <&dummy_clock_visys>,
  1554. <&dummy_clock_visys>,
  1555. <&dummy_clock_visys>;
  1556. clock-names = "pclk", "pixclk", "cfg_clk";
  1557. phy_name = "CSI_4LANE";
  1558. status = "disabled";
  1559. };
  1560. csia_reg: visys-reg@ffe4020000 {
  1561. compatible = "thead,light-visys-reg", "syscon";
  1562. reg = < 0xff 0xe4020000 0x0 0x10000>;
  1563. status = "okay";
  1564. };
  1565. bm_csi1: csi@ffe4010000{ //CSI2X2_B
  1566. compatible = "thead,light-bm-csi";
  1567. reg = < 0xff 0xe4010000 0x0 0x10000>;
  1568. interrupt-parent = <&intc>;
  1569. interrupts = <126>; // 110 + 16 int_mipi_csi2x2_int0
  1570. dphyglueiftester = <0x182>; // for FPGA PHY only. ASIC not needed.
  1571. sysreg_mipi_csi_ctrl = <0x148>;
  1572. visys-regmap = <&visys_reg>;
  1573. csia-regmap = <&csia_reg>;
  1574. clocks = <&dummy_clock_visys>,
  1575. <&dummy_clock_visys>,
  1576. <&dummy_clock_visys>;
  1577. clock-names = "pclk", "pixclk", "cfg_clk";
  1578. phy_name = "CSI_B";
  1579. status = "disabled";
  1580. };
  1581. bm_csi2: csi@ffe4020000{ //CSI2X2_A
  1582. compatible = "thead,light-bm-csi";
  1583. reg = < 0xff 0xe4020000 0x0 0x10000>;
  1584. interrupt-parent = <&intc>;
  1585. interrupts = <127>;
  1586. dphyglueiftester = <0x184>;
  1587. sysreg_mipi_csi_ctrl = <0x144>;
  1588. clocks = <&dummy_clock_visys>,
  1589. <&dummy_clock_visys>,
  1590. <&dummy_clock_visys>;
  1591. clock-names = "pclk", "pixclk", "cfg_clk";
  1592. phy_name = "CSI_A";
  1593. status = "disabled";
  1594. };
  1595. bm_isp0: bm_isp@ffe4100000 {
  1596. compatible = "thead,light-bm-isp";
  1597. reg = <0xff 0xe4100000 0x0 0x10000>;
  1598. status = "disabled";
  1599. };
  1600. bm_isp1: bm_isp@ffe4110000 {
  1601. compatible = "thead,light-bm-isp";
  1602. reg = <0xff 0xe4110000 0x0 0x10000>;
  1603. status = "disabled";
  1604. };
  1605. //isp-ry
  1606. bm_isp2: bm_isp@ffe4120000 {
  1607. compatible = "thead,light-bm-isp";
  1608. reg = <0xff 0xe4120000 0x0 0x10000>;
  1609. status = "disabled";
  1610. };
  1611. vi_pre: vi_pre@ffe4030000 {
  1612. compatible = "thead,vi_pre";
  1613. reg = <0xff 0xe4030000 0x0 0x1000>;
  1614. interrupt-parent = <&intc>;
  1615. interrupts = <134>;
  1616. clocks = <&dummy_clock_vipre>,
  1617. <&dummy_clock_vipre>,
  1618. <&dummy_clock_vipre>;
  1619. clock-names ="aclk", "pclk", "pixclk";
  1620. status = "disabled";
  1621. };
  1622. video0: cam_dev@100 {
  1623. compatible = "thead,video";
  1624. status = "disabled";
  1625. };
  1626. video1: cam_dev@200 {
  1627. compatible = "thead,video";
  1628. status = "disabled";
  1629. };
  1630. video2: cam_dev@300 {
  1631. compatible = "thead,video";
  1632. status = "disabled";
  1633. };
  1634. video3: cam_dev@400 {
  1635. compatible = "thead,video";
  1636. status = "disabled";
  1637. };
  1638. video4: cam_dev@500 {
  1639. compatible = "thead,video";
  1640. status = "disabled";
  1641. };
  1642. video5: cam_dev@600 {
  1643. compatible = "thead,video";
  1644. status = "disabled";
  1645. };
  1646. video6: cam_dev@700 {
  1647. compatible = "thead,video";
  1648. status = "disabled";
  1649. };
  1650. video7: cam_dev@800 {
  1651. compatible = "thead,video";
  1652. status = "disabled";
  1653. };
  1654. video8: cam_dev@900 {
  1655. compatible = "thead,video";
  1656. status = "disabled";
  1657. };
  1658. video9: cam_dev@a00 {
  1659. compatible = "thead,video";
  1660. status = "disabled";
  1661. };
  1662. video10: cam_dev@b00 {
  1663. compatible = "thead,video";
  1664. status = "disabled";
  1665. };
  1666. video11: cam_dev@c00 {
  1667. compatible = "thead,video";
  1668. status = "disabled";
  1669. };
  1670. video12: cam_dev@d00 {
  1671. compatible = "thead,video";
  1672. status = "disabled";
  1673. };
  1674. video13: cam_dev@e00 {
  1675. compatible = "thead,video";
  1676. status = "disabled";
  1677. };
  1678. video14: cam_dev@f00 {
  1679. compatible = "thead,video";
  1680. status = "disabled";
  1681. };
  1682. video15: cam_dev@f01 {
  1683. compatible = "thead,video";
  1684. status = "disabled";
  1685. };
  1686. vvcam_flash_led0: vvcam_flash_led@0 {
  1687. compatible = "thead,light-vvcam-flash_led";
  1688. status = "disabled";
  1689. };
  1690. vvcam_sensor0: vvcam_sensor@0 {
  1691. compatible = "thead,light-vvcam-sensor";
  1692. status = "disabled";
  1693. };
  1694. vvcam_sensor1: vvcam_sensor@1 {
  1695. compatible = "thead,light-vvcam-sensor";
  1696. status = "disabled";
  1697. };
  1698. vvcam_sensor2: vvcam_sensor@2 {
  1699. compatible = "thead,light-vvcam-sensor";
  1700. status = "disabled";
  1701. };
  1702. vvcam_sensor3: vvcam_sensor@3 {
  1703. compatible = "thead,light-vvcam-sensor";
  1704. status = "disabled";
  1705. };
  1706. vvcam_sensor4: vvcam_sensor@4 {
  1707. compatible = "thead,light-vvcam-sensor";
  1708. status = "disabled";
  1709. };
  1710. vvcam_sensor5: vvcam_sensor@5 {
  1711. compatible = "thead,light-vvcam-sensor";
  1712. status = "disabled";
  1713. };
  1714. vvcam_sensor6: vvcam_sensor@6 {
  1715. compatible = "thead,light-vvcam-sensor";
  1716. status = "disabled";
  1717. };
  1718. xtensa_dsp: dsp@01{
  1719. compatible = "thead,dsp-hw-common";
  1720. reg = <0xff 0xef040000 0x0 0x001000 >; /*DSP_SYSREG(0x0000-0xFFF) */
  1721. status = "disabled";
  1722. };
  1723. xtensa_dsp0: dsp@0 {
  1724. compatible = "cdns,xrp-hw-simple";
  1725. reg = <0xff 0xe4040190 0x0 0x000010 /* host irq DSP->CPU INT Register */
  1726. 0xff 0xe40401e0 0x0 0x000010 /* device irq CPU->DSP INT Register */
  1727. 0xff 0xef048000 0x0 0x008000>; /* DSP shared memory */
  1728. dsp = <0>;
  1729. dspsys-rst-bit = <8>; /*bit# in DSP_SYSREG*/
  1730. dspsys-bus-offset = <0x90>; /*in DSP_SYSREG*/
  1731. device-irq = <0x4 1 24>; /*0xff 0xe40401e4 offset to clear DSP I]RQ, bit#, IRQ# */
  1732. device-irq-host-offset = <0x8>; /*0xff 0xe40401e8 offset to trigger DSP IRQ*/
  1733. device-irq-mode = <1>; /*level trigger*/
  1734. host-irq = <0x4 1>; /*0xff 0xe4040194 offset to clear, bit# */
  1735. host-irq-mode = <1>; /*level trigger */
  1736. host-irq-offset = <0x8>; /* 0xff 0xe4040198 offset to trigger ,device side*/
  1737. interrupt-parent = <&intc>;
  1738. interrupts = <156>;
  1739. firmware-name = "xrp0.elf";
  1740. clocks = <&dummy_clock_visys>,
  1741. <&dummy_clock_visys>;
  1742. clock-names = "pclk", "cclk";
  1743. status = "disabled";
  1744. #address-cells = <2>;
  1745. #size-cells = <1>;
  1746. ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000
  1747. 0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000
  1748. 0x00 0xfa000000 0xff 0xe0000000 0x00180000
  1749. 0x00 0xe0180000 0xff 0xe0180000 0x00040000
  1750. 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */
  1751. dsp@0 {
  1752. ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000
  1753. 0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000
  1754. 0x00 0xfa000000 0xff 0xe0000000 0x00180000
  1755. 0x00 0xe0180000 0xff 0xe0180000 0x00040000
  1756. 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */
  1757. };
  1758. };
  1759. xtensa_dsp1: dsp@1 {
  1760. compatible = "cdns,xrp-hw-simple";
  1761. reg = <0xff 0xe40401a0 0x0 0x000010 /* host irq DSP->CPU INT Register */
  1762. 0xff 0xe40401d0 0x0 0x000010 /* device irq CPU->DSP INT Register */
  1763. 0xff 0xef050000 0x0 0x008000>; /* DSP shared memory */
  1764. dsp = <1>;
  1765. dspsys-rst-bit = <8>; /*bit# in DSP_SYSREG*/
  1766. dspsys-bus-offset = <0x90>; /*in DSP_SYSREG*/
  1767. device-irq = <0x4 1 24>; /*0xff 0xe40401e4 offset to clear DSP I]RQ, bit#, IRQ# */
  1768. device-irq-host-offset = <0x8>; /*0xff 0xe40401e8 offset to trigger DSP IRQ*/
  1769. device-irq-mode = <1>; /*level trigger*/
  1770. host-irq = <0x4 1>; /*0xff 0xe4040194 offset to clear, bit# */
  1771. host-irq-mode = <1>; /*level trigger */
  1772. host-irq-offset = <0x8>; /* 0xff 0xe4040198 offset to trigger ,device side*/
  1773. interrupt-parent = <&intc>;
  1774. interrupts = <157>;
  1775. firmware-name = "xrp1.elf";
  1776. clocks = <&dummy_clock_visys>,
  1777. <&dummy_clock_visys>;
  1778. clock-names = "pclk", "cclk";
  1779. status = "disabled";
  1780. #address-cells = <2>;
  1781. #size-cells = <1>;
  1782. ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000
  1783. 0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000
  1784. 0x00 0xfa000000 0xff 0xe0000000 0x00180000
  1785. 0x00 0xe0180000 0xff 0xe01C0000 0x00040000
  1786. 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */
  1787. dsp@0 {
  1788. ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000
  1789. 0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000
  1790. 0x00 0xfa000000 0xff 0xe0000000 0x00180000
  1791. 0x00 0xe0180000 0xff 0xe01C0000 0x00040000
  1792. 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */
  1793. };
  1794. };
  1795. mrvbr: mrvbr@ffff018050 {
  1796. compatible = "mrvbr";
  1797. reg = <0xff 0xff019050 0x0 0x1000>;
  1798. };
  1799. mrmr: mrmr@ffff014004 {
  1800. compatible = "mrmr";
  1801. reg = <0xff 0xff015004 0x0 0x1000>;
  1802. };
  1803. bmu: ddr-pmu@ffff008000 {
  1804. compatible = "thead,light-ddr-pmu";
  1805. reg = <0xff 0xff008000 0x0 0x800
  1806. 0xff 0xff008800 0x0 0x800
  1807. 0xff 0xff009000 0x0 0x800
  1808. 0xff 0xff009800 0x0 0x800
  1809. 0xff 0xff00a000 0x0 0x800>;
  1810. interrupt-parent = <&intc>;
  1811. interrupts = <87>;
  1812. status = "okay";
  1813. };
  1814. mbox_910t: mbox@ffffc38000 {
  1815. compatible = "thead,light-mbox";
  1816. reg = <0xff 0xffc38000 0x0 0x4000>,
  1817. <0xff 0xffc44000 0x0 0x1000>,
  1818. <0xff 0xffc4c000 0x0 0x1000>,
  1819. <0xff 0xffc54000 0x0 0x1000>;
  1820. reg-names = "local_base", "remote_icu0", "remote_icu1", "remote_icu2";
  1821. interrupt-parent = <&intc>;
  1822. interrupts = <28>;
  1823. clocks = <&dummy_clock_apb>;
  1824. clock-names = "ipg";
  1825. icu_cpu_id = <0>;
  1826. #mbox-cells = <2>;
  1827. status = "disabled";
  1828. };
  1829. trng: rng@ffff300000 {
  1830. compatible = "inside-secure,safexcel-eip76";
  1831. reg = <0xff 0xff300000 0x0 0x7d>;
  1832. interrupt-parent = <&intc>;
  1833. interrupts = <149>;
  1834. clocks = <&dummy_clock_eip>;
  1835. status = "disabled";
  1836. };
  1837. eip_28: eip-28@ffff300000 {
  1838. compatible = "xlnx,sunrise-fpga-1.0", "safexcel-eip-28";
  1839. reg = <0xff 0xff300000 0x0 0x40000>;
  1840. interrupt-parent = <&intc>;
  1841. interrupts = <144>,<145>,<146>,<147>;
  1842. clocks = <&dummy_clock_eip>;
  1843. status = "disabled";
  1844. };
  1845. khvhost: khvhost {
  1846. compatible = "thead,khv-host";
  1847. interrupt-parent = <&intc>;
  1848. interrupts = <215>; /* TEE INT SRC_7 */
  1849. };
  1850. visys_clk_gate: visys-clk-gate { /* VI_SYSREG_R */
  1851. compatible = "thead,visys-gate-controller";
  1852. visys-regmap = <&visys_reg>;
  1853. #clock-cells = <1>;
  1854. status = "okay";
  1855. };
  1856. vpsys_clk_gate: vpsys-clk-gate@ffecc30000 { /* VP_SYSREG_R */
  1857. compatible = "thead,vpsys-gate-controller";
  1858. reg = <0xff 0xecc30000 0x0 0x1000>;
  1859. #clock-cells = <1>;
  1860. status = "okay";
  1861. };
  1862. vosys_clk_gate: vosys-clk-gate@ffef528000 { /* VO_SYSREG_R */
  1863. compatible = "thead,vosys-gate-controller";
  1864. reg = <0xff 0xef528000 0x0 0x1000>;
  1865. #clock-cells = <1>;
  1866. status = "okay";
  1867. };
  1868. dspsys_clk_gate: dspsys-clk-gate {
  1869. compatible = "thead,dspsys-gate-controller";
  1870. dspsys-regmap = <&dspsys_reg>;
  1871. #clock-cells = <1>;
  1872. status = "okay";
  1873. };
  1874. };
  1875. };