sysconfig.c 13 KB

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  1. /*************************************************************************/ /*!
  2. @File
  3. @Title System Configuration
  4. @Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
  5. @Description System Configuration functions
  6. @License Dual MIT/GPLv2
  7. The contents of this file are subject to the MIT license as set out below.
  8. Permission is hereby granted, free of charge, to any person obtaining a copy
  9. of this software and associated documentation files (the "Software"), to deal
  10. in the Software without restriction, including without limitation the rights
  11. to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12. copies of the Software, and to permit persons to whom the Software is
  13. furnished to do so, subject to the following conditions:
  14. The above copyright notice and this permission notice shall be included in
  15. all copies or substantial portions of the Software.
  16. Alternatively, the contents of this file may be used under the terms of
  17. the GNU General Public License Version 2 ("GPL") in which case the provisions
  18. of GPL are applicable instead of those above.
  19. If you wish to allow use of your version of this file only under the terms of
  20. GPL, and not to allow others to use your version of this file under the terms
  21. of the MIT license, indicate your decision by deleting the provisions above
  22. and replace them with the notice and other provisions required by GPL as set
  23. out in the file called "GPL-COPYING" included in this distribution. If you do
  24. not delete the provisions above, a recipient may use your version of this file
  25. under the terms of either the MIT license or GPL.
  26. This License is also included in this distribution in the file called
  27. "MIT-COPYING".
  28. EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
  29. PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
  30. BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  31. PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
  32. COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  33. IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  34. CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  35. */ /**************************************************************************/
  36. #include <linux/interrupt.h>
  37. #include "interrupt_support.h"
  38. #include "pvrsrv_device.h"
  39. #include "syscommon.h"
  40. #include "vz_vmm_pvz.h"
  41. #include "allocmem.h"
  42. #include "sysinfo.h"
  43. #include "sysconfig.h"
  44. #include "physheap.h"
  45. #include "pvr_debug.h"
  46. #if defined(SUPPORT_ION)
  47. #include "ion_support.h"
  48. #endif
  49. #if defined(__linux__)
  50. #include <linux/platform_device.h>
  51. #include <linux/dma-mapping.h>
  52. #endif
  53. #include "rgx_bvnc_defs_km.h"
  54. #include "thead_sys.h"
  55. /*
  56. * In systems that support trusted device address protection, there are three
  57. * physical heaps from which pages should be allocated:
  58. * - one heap for normal allocations
  59. * - one heap for allocations holding META code memory
  60. * - one heap for allocations holding secured DRM data
  61. */
  62. #define PHYS_HEAP_IDX_GENERAL 0
  63. #define PHYS_HEAP_IDX_FW 1
  64. #if defined(SUPPORT_TRUSTED_DEVICE)
  65. #define PHYS_HEAP_IDX_TDFWMEM 2
  66. #define PHYS_HEAP_IDX_TDSECUREBUF 3
  67. #elif defined(SUPPORT_DEDICATED_FW_MEMORY)
  68. #define PHYS_HEAP_IDX_FW_MEMORY 2
  69. #endif
  70. #define UMA_HEAP_USAGE_FLAG PHYS_HEAP_USAGE_GPU_LOCAL
  71. #define UMA_DEFAULT_HEAP PVRSRV_PHYS_HEAP_GPU_LOCAL
  72. /*
  73. CPU to Device physical address translation
  74. */
  75. static
  76. void UMAPhysHeapCpuPAddrToDevPAddr(IMG_HANDLE hPrivData,
  77. IMG_UINT32 ui32NumOfAddr,
  78. IMG_DEV_PHYADDR *psDevPAddr,
  79. IMG_CPU_PHYADDR *psCpuPAddr)
  80. {
  81. PVR_UNREFERENCED_PARAMETER(hPrivData);
  82. /* Optimise common case */
  83. psDevPAddr[0].uiAddr = psCpuPAddr[0].uiAddr;
  84. if (ui32NumOfAddr > 1)
  85. {
  86. IMG_UINT32 ui32Idx;
  87. for (ui32Idx = 1; ui32Idx < ui32NumOfAddr; ++ui32Idx)
  88. {
  89. psDevPAddr[ui32Idx].uiAddr = psCpuPAddr[ui32Idx].uiAddr;
  90. }
  91. }
  92. }
  93. /*
  94. Device to CPU physical address translation
  95. */
  96. static
  97. void UMAPhysHeapDevPAddrToCpuPAddr(IMG_HANDLE hPrivData,
  98. IMG_UINT32 ui32NumOfAddr,
  99. IMG_CPU_PHYADDR *psCpuPAddr,
  100. IMG_DEV_PHYADDR *psDevPAddr)
  101. {
  102. PVR_UNREFERENCED_PARAMETER(hPrivData);
  103. /* Optimise common case */
  104. psCpuPAddr[0].uiAddr = psDevPAddr[0].uiAddr;
  105. if (ui32NumOfAddr > 1)
  106. {
  107. IMG_UINT32 ui32Idx;
  108. for (ui32Idx = 1; ui32Idx < ui32NumOfAddr; ++ui32Idx)
  109. {
  110. psCpuPAddr[ui32Idx].uiAddr = psDevPAddr[ui32Idx].uiAddr;
  111. }
  112. }
  113. }
  114. static PHYS_HEAP_FUNCTIONS gsPhysHeapFuncs =
  115. {
  116. /* pfnCpuPAddrToDevPAddr */
  117. UMAPhysHeapCpuPAddrToDevPAddr,
  118. /* pfnDevPAddrToCpuPAddr */
  119. UMAPhysHeapDevPAddrToCpuPAddr,
  120. };
  121. static PVRSRV_ERROR PhysHeapsCreate(PHYS_HEAP_CONFIG **ppasPhysHeapsOut,
  122. IMG_UINT32 *puiPhysHeapCountOut)
  123. {
  124. /*
  125. * This function is called during device initialisation, which on Linux,
  126. * means it won't be called concurrently. As such, there's no need to
  127. * protect it with a lock or use an atomic variable.
  128. */
  129. PHYS_HEAP_CONFIG *pasPhysHeaps;
  130. IMG_UINT32 uiHeapCount = 2;
  131. #if defined(SUPPORT_TRUSTED_DEVICE)
  132. uiHeapCount += 2;
  133. #elif defined(SUPPORT_DEDICATED_FW_MEMORY)
  134. uiHeapCount += 1;
  135. #endif
  136. pasPhysHeaps = OSAllocZMem(sizeof(*pasPhysHeaps) * uiHeapCount);
  137. if (!pasPhysHeaps)
  138. {
  139. return PVRSRV_ERROR_OUT_OF_MEMORY;
  140. }
  141. pasPhysHeaps[PHYS_HEAP_IDX_GENERAL].pszPDumpMemspaceName = "SYSMEM";
  142. pasPhysHeaps[PHYS_HEAP_IDX_GENERAL].eType = PHYS_HEAP_TYPE_UMA;
  143. pasPhysHeaps[PHYS_HEAP_IDX_GENERAL].psMemFuncs = &gsPhysHeapFuncs;
  144. pasPhysHeaps[PHYS_HEAP_IDX_GENERAL].ui32UsageFlags = UMA_HEAP_USAGE_FLAG;
  145. pasPhysHeaps[PHYS_HEAP_IDX_FW].pszPDumpMemspaceName = "SYSMEM_FW";
  146. pasPhysHeaps[PHYS_HEAP_IDX_FW].eType = PHYS_HEAP_TYPE_UMA;
  147. pasPhysHeaps[PHYS_HEAP_IDX_FW].psMemFuncs = &gsPhysHeapFuncs;
  148. pasPhysHeaps[PHYS_HEAP_IDX_FW].ui32UsageFlags = PHYS_HEAP_USAGE_FW_MAIN;
  149. #if defined(SUPPORT_TRUSTED_DEVICE)
  150. pasPhysHeaps[PHYS_HEAP_IDX_TDFWMEM].pszPDumpMemspaceName = "TDFWMEM";
  151. pasPhysHeaps[PHYS_HEAP_IDX_TDFWMEM].eType = PHYS_HEAP_TYPE_UMA;
  152. pasPhysHeaps[PHYS_HEAP_IDX_TDFWMEM].psMemFuncs = &gsPhysHeapFuncs;
  153. pasPhysHeaps[PHYS_HEAP_IDX_TDFWMEM].ui32UsageFlags =
  154. PHYS_HEAP_USAGE_FW_CODE | PHYS_HEAP_USAGE_FW_PRIV_DATA;
  155. pasPhysHeaps[PHYS_HEAP_IDX_TDSECUREBUF].pszPDumpMemspaceName = "TDSECBUFMEM";
  156. pasPhysHeaps[PHYS_HEAP_IDX_TDSECUREBUF].eType = PHYS_HEAP_TYPE_UMA;
  157. pasPhysHeaps[PHYS_HEAP_IDX_TDSECUREBUF].psMemFuncs = &gsPhysHeapFuncs;
  158. pasPhysHeaps[PHYS_HEAP_IDX_TDSECUREBUF].ui32UsageFlags =
  159. PHYS_HEAP_USAGE_GPU_SECURE;
  160. #elif defined(SUPPORT_DEDICATED_FW_MEMORY)
  161. pasPhysHeaps[PHYS_HEAP_IDX_FW_MEMORY].pszPDumpMemspaceName = "DEDICATEDFWMEM";
  162. pasPhysHeaps[PHYS_HEAP_IDX_FW_MEMORY].eType = PHYS_HEAP_TYPE_UMA;
  163. pasPhysHeaps[PHYS_HEAP_IDX_FW_MEMORY].psMemFuncs = &gsPhysHeapFuncs;
  164. pasPhysHeaps[PHYS_HEAP_IDX_FW_MEMORY].ui32UsageFlags =
  165. PHYS_HEAP_USAGE_FW_CODE | PHYS_HEAP_USAGE_FW_PRIV_DATA;
  166. #endif
  167. *ppasPhysHeapsOut = pasPhysHeaps;
  168. *puiPhysHeapCountOut = uiHeapCount;
  169. return PVRSRV_OK;
  170. }
  171. static void PhysHeapsDestroy(PHYS_HEAP_CONFIG *pasPhysHeaps)
  172. {
  173. OSFreeMem(pasPhysHeaps);
  174. }
  175. static PVRSRV_ERROR SysDevPrePowerState(
  176. IMG_HANDLE hSysData,
  177. PVRSRV_SYS_POWER_STATE eNewPowerState,
  178. PVRSRV_SYS_POWER_STATE eCurrentPowerState,
  179. PVRSRV_POWER_FLAGS ePwrFlags)
  180. {
  181. struct gpu_plat_if *mfg = hSysData;
  182. thead_debug("SysDevPrePowerState (%d->%d), bPwrFlags = 0x%08x\n",
  183. eCurrentPowerState, eNewPowerState, ePwrFlags);
  184. mutex_lock(&mfg->set_power_state);
  185. if ((PVRSRV_SYS_POWER_STATE_OFF == eNewPowerState) &&
  186. (PVRSRV_SYS_POWER_STATE_ON == eCurrentPowerState))
  187. thead_mfg_disable(mfg);
  188. mutex_unlock(&mfg->set_power_state);
  189. return PVRSRV_OK;
  190. }
  191. static PVRSRV_ERROR SysDevPostPowerState(
  192. IMG_HANDLE hSysData,
  193. PVRSRV_SYS_POWER_STATE eNewPowerState,
  194. PVRSRV_SYS_POWER_STATE eCurrentPowerState,
  195. PVRSRV_POWER_FLAGS ePwrFlags)
  196. {
  197. struct gpu_plat_if *mfg = hSysData;
  198. PVRSRV_ERROR ret;
  199. thead_debug("SysDevPostPowerState (%d->%d)\n",
  200. eCurrentPowerState, eNewPowerState);
  201. mutex_lock(&mfg->set_power_state);
  202. if ((PVRSRV_SYS_POWER_STATE_ON == eNewPowerState) &&
  203. (PVRSRV_SYS_POWER_STATE_OFF == eCurrentPowerState)) {
  204. if (thead_mfg_enable(mfg)) {
  205. ret = PVRSRV_ERROR_DEVICE_POWER_CHANGE_FAILURE;
  206. goto done;
  207. }
  208. }
  209. ret = PVRSRV_OK;
  210. done:
  211. mutex_unlock(&mfg->set_power_state);
  212. return ret;
  213. }
  214. static void SysDevFeatureDepInit(PVRSRV_DEVICE_CONFIG *psDevConfig, IMG_UINT64 ui64Features)
  215. {
  216. #if defined(SUPPORT_AXI_ACE_TEST)
  217. if ( ui64Features & RGX_FEATURE_AXI_ACELITE_BIT_MASK)
  218. {
  219. psDevConfig->eCacheSnoopingMode = PVRSRV_DEVICE_SNOOP_CPU_ONLY;
  220. }else
  221. #endif
  222. {
  223. psDevConfig->eCacheSnoopingMode = PVRSRV_DEVICE_SNOOP_NONE;
  224. }
  225. }
  226. PVRSRV_ERROR SysDevInit(void *pvOSDevice, PVRSRV_DEVICE_CONFIG **ppsDevConfig)
  227. {
  228. PVRSRV_DEVICE_CONFIG *psDevConfig;
  229. RGX_DATA *psRGXData;
  230. RGX_TIMING_INFORMATION *psRGXTimingInfo;
  231. PHYS_HEAP_CONFIG *pasPhysHeaps;
  232. IMG_UINT32 uiPhysHeapCount;
  233. PVRSRV_ERROR eError;
  234. struct gpu_plat_if *mfg;
  235. #if defined(__linux__)
  236. int iIrq;
  237. struct resource *psDevMemRes = NULL;
  238. struct platform_device *psDev;
  239. psDev = to_platform_device((struct device *)pvOSDevice);
  240. #endif
  241. #if defined(__linux__)
  242. dma_set_mask(pvOSDevice, DMA_BIT_MASK(40));
  243. #endif
  244. mfg = dt_hw_init(pvOSDevice);
  245. if (IS_ERR(mfg)) {
  246. if (PTR_ERR(mfg) == -EPROBE_DEFER)
  247. return PVRSRV_ERROR_PROBE_DEFER;
  248. else
  249. return PVRSRV_ERROR_INIT_FAILURE;
  250. }
  251. psDevConfig = OSAllocZMem(sizeof(*psDevConfig) +
  252. sizeof(*psRGXData) +
  253. sizeof(*psRGXTimingInfo));
  254. if (!psDevConfig)
  255. {
  256. return PVRSRV_ERROR_OUT_OF_MEMORY;
  257. }
  258. psRGXData = (RGX_DATA *)((IMG_CHAR *)psDevConfig + sizeof(*psDevConfig));
  259. psRGXTimingInfo = (RGX_TIMING_INFORMATION *)((IMG_CHAR *)psRGXData + sizeof(*psRGXData));
  260. eError = PhysHeapsCreate(&pasPhysHeaps, &uiPhysHeapCount);
  261. if (eError)
  262. {
  263. goto ErrorFreeDevConfig;
  264. }
  265. /* Setup RGX specific timing data */
  266. psRGXTimingInfo->ui32CoreClockSpeed = RGX_THEAD_CORE_CLOCK_SPEED;
  267. psRGXTimingInfo->bEnableActivePM = IMG_TRUE;
  268. psRGXTimingInfo->bEnableRDPowIsland = IMG_FALSE;
  269. psRGXTimingInfo->ui32ActivePMLatencyms = SYS_RGX_ACTIVE_POWER_LATENCY_MS;
  270. /* Set up the RGX data */
  271. psRGXData->psRGXTimingInfo = psRGXTimingInfo;
  272. /* Setup the device config */
  273. psDevConfig->pvOSDevice = pvOSDevice;
  274. psDevConfig->pszName = "thead";
  275. psDevConfig->pszVersion = NULL;
  276. psDevConfig->pfnSysDevFeatureDepInit = SysDevFeatureDepInit;
  277. /* Device setup information */
  278. #if defined(__linux__)
  279. psDevMemRes = platform_get_resource(psDev, IORESOURCE_MEM, 0);
  280. if (psDevMemRes)
  281. {
  282. psDevConfig->sRegsCpuPBase.uiAddr = psDevMemRes->start;
  283. psDevConfig->ui32RegsSize = (unsigned int)(psDevMemRes->end - psDevMemRes->start);
  284. }
  285. iIrq = platform_get_irq(psDev, 0);
  286. if (iIrq >= 0)
  287. {
  288. psDevConfig->ui32IRQ = (IMG_UINT32) iIrq;
  289. }
  290. #else
  291. /* Device setup information */
  292. psDevConfig->sRegsCpuPBase.uiAddr = 0xFFEF400000;
  293. psDevConfig->ui32RegsSize = 0x100000;
  294. psDevConfig->ui32IRQ = 102;
  295. #endif
  296. PVR_LOG(("*****enter sys dev init %llx %d\r\n", psDevConfig->sRegsCpuPBase.uiAddr, psDevConfig->ui32IRQ));
  297. psDevConfig->pasPhysHeaps = pasPhysHeaps;
  298. psDevConfig->ui32PhysHeapCount = uiPhysHeapCount;
  299. psDevConfig->eDefaultHeap = UMA_DEFAULT_HEAP;
  300. /* No power management on no HW system */
  301. psDevConfig->pfnPrePowerState = SysDevPrePowerState;
  302. psDevConfig->pfnPostPowerState = SysDevPostPowerState;
  303. psDevConfig->bHasFBCDCVersion31 = IMG_FALSE;
  304. /* No clock frequency either */
  305. psDevConfig->pfnClockFreqGet = NULL;
  306. psDevConfig->hDevData = psRGXData;
  307. psDevConfig->hSysData = mfg;
  308. /* Setup other system specific stuff */
  309. #if defined(SUPPORT_ION)
  310. IonInit(NULL);
  311. #endif
  312. /* Set psDevConfig->pfnSysDevErrorNotify callback */
  313. psDevConfig->pfnSysDevErrorNotify = SysRGXErrorNotify;
  314. *ppsDevConfig = psDevConfig;
  315. return PVRSRV_OK;
  316. ErrorFreeDevConfig:
  317. OSFreeMem(psDevConfig);
  318. return eError;
  319. }
  320. void SysDevDeInit(PVRSRV_DEVICE_CONFIG *psDevConfig)
  321. {
  322. #if defined(SUPPORT_ION)
  323. IonDeinit();
  324. #endif
  325. PhysHeapsDestroy(psDevConfig->pasPhysHeaps);
  326. OSFreeMem(psDevConfig);
  327. }
  328. PVRSRV_ERROR SysInstallDeviceLISR(IMG_HANDLE hSysData,
  329. IMG_UINT32 ui32IRQ,
  330. const IMG_CHAR *pszName,
  331. PFN_LISR pfnLISR,
  332. void *pvData,
  333. IMG_HANDLE *phLISRData)
  334. {
  335. PVR_LOG(("*****enter sysintstall LISR\r\n"));
  336. PVR_UNREFERENCED_PARAMETER(hSysData);
  337. return OSInstallSystemLISR(phLISRData, ui32IRQ, pszName, pfnLISR, pvData,
  338. SYS_IRQ_FLAG_TRIGGER_DEFAULT);
  339. }
  340. PVRSRV_ERROR SysUninstallDeviceLISR(IMG_HANDLE hLISRData)
  341. {
  342. return OSUninstallSystemLISR(hLISRData);
  343. }
  344. PVRSRV_ERROR SysDebugInfo(PVRSRV_DEVICE_CONFIG *psDevConfig,
  345. DUMPDEBUG_PRINTF_FUNC *pfnDumpDebugPrintf,
  346. void *pvDumpDebugFile)
  347. {
  348. PVR_UNREFERENCED_PARAMETER(psDevConfig);
  349. PVR_UNREFERENCED_PARAMETER(pfnDumpDebugPrintf);
  350. PVR_UNREFERENCED_PARAMETER(pvDumpDebugFile);
  351. return PVRSRV_OK;
  352. }
  353. /******************************************************************************
  354. End of file (sysconfig.c)
  355. ******************************************************************************/