os_cpu_cache.h 3.4 KB

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  1. /*************************************************************************/ /*!
  2. @File
  3. @Title OS and CPU d-cache maintenance mechanisms
  4. @Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
  5. @Description Defines for cache management which are visible internally only
  6. @License Dual MIT/GPLv2
  7. The contents of this file are subject to the MIT license as set out below.
  8. Permission is hereby granted, free of charge, to any person obtaining a copy
  9. of this software and associated documentation files (the "Software"), to deal
  10. in the Software without restriction, including without limitation the rights
  11. to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12. copies of the Software, and to permit persons to whom the Software is
  13. furnished to do so, subject to the following conditions:
  14. The above copyright notice and this permission notice shall be included in
  15. all copies or substantial portions of the Software.
  16. Alternatively, the contents of this file may be used under the terms of
  17. the GNU General Public License Version 2 ("GPL") in which case the provisions
  18. of GPL are applicable instead of those above.
  19. If you wish to allow use of your version of this file only under the terms of
  20. GPL, and not to allow others to use your version of this file under the terms
  21. of the MIT license, indicate your decision by deleting the provisions above
  22. and replace them with the notice and other provisions required by GPL as set
  23. out in the file called "GPL-COPYING" included in this distribution. If you do
  24. not delete the provisions above, a recipient may use your version of this file
  25. under the terms of either the MIT license or GPL.
  26. This License is also included in this distribution in the file called
  27. "MIT-COPYING".
  28. EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
  29. PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
  30. BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  31. PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
  32. COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  33. IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  34. CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  35. */ /**************************************************************************/
  36. #ifndef OS_CPU_CACHE_H
  37. #define OS_CPU_CACHE_H
  38. #include "info_page_defs.h"
  39. #define PVRSRV_CACHE_OP_TIMELINE 0x8 /*!< Request SW_SYNC timeline notification when executed */
  40. #define PVRSRV_CACHE_OP_FORCE_SYNCHRONOUS 0x10 /*!< Force all batch members to be executed synchronously */
  41. #define CACHEFLUSH_ISA_X86 0x1 /*!< x86/x64 specific UM range-based cache flush */
  42. #define CACHEFLUSH_ISA_ARM64 0x2 /*!< Aarch64 specific UM range-based cache flush */
  43. #define CACHEFLUSH_ISA_GENERIC 0x3 /*!< Other ISA's without UM range-based cache flush */
  44. #ifndef CACHEFLUSH_ISA_TYPE
  45. #if defined(__i386__) || defined(__x86_64__)
  46. #define CACHEFLUSH_ISA_TYPE CACHEFLUSH_ISA_X86
  47. #elif defined(__arm64__) || defined(__aarch64__)
  48. #define CACHEFLUSH_ISA_TYPE CACHEFLUSH_ISA_ARM64
  49. #else
  50. #define CACHEFLUSH_ISA_TYPE CACHEFLUSH_ISA_GENERIC
  51. #endif
  52. #endif
  53. #if (CACHEFLUSH_ISA_TYPE == CACHEFLUSH_ISA_X86) || (CACHEFLUSH_ISA_TYPE == CACHEFLUSH_ISA_ARM64)
  54. #define CACHEFLUSH_ISA_SUPPORTS_UM_FLUSH /*!< x86/x86_64/ARM64 supports user-mode d-cache flush */
  55. #endif
  56. #endif /* OS_CPU_CACHE_H */