dmaif.c 27 KB

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  1. /********************************************************************************************
  2. ************************************************************************************************/
  3. #include <stdio.h>
  4. #include <stdlib.h>
  5. #include <string.h>
  6. #ifndef __XTENSA__
  7. #include <conio.h>
  8. #endif
  9. #include <csi_dsp_types.h>
  10. //#include "commondef.h"
  11. //#include "dma.h"
  12. #include "dmaif.h"
  13. //#include "dl_hw_cfg.h"
  14. #include <xtensa\config\core-isa.h>
  15. #define DMA_DESCR_CNT 8 // number of DMA descriptors
  16. #define MAX_PIF XCHAL_IDMA_MAX_OUTSTANDING_REQ
  17. #define _USE_IDMA_
  18. #define _USE_MULTI_IDMA
  19. //#define _USE_TCM_ALLOCATE
  20. //#if XCHAL_HAVE_NX
  21. IDMA_BUFFER_DEFINE(idmaObjBuff, DMA_DESCR_CNT, IDMA_64B_DESC);
  22. //#else
  23. //IDMA_BUFFER_DEFINE(idmaObjBuff, DMA_DESCR_CNT, IDMA_2D_DESC);
  24. //#endif
  25. //#if XCHAL_HAVE_NX
  26. #ifdef _USE_MULTI_IDMA
  27. IDMA_BUFFER_DEFINE(idmaObjBuff1, DMA_DESCR_CNT, IDMA_64B_DESC);
  28. #else
  29. static idma_buffer_t *idmaObjBuff1=NULL;
  30. #endif
  31. //#endif
  32. #define _LOCAL_RAM0_ __attribute__((section(".dram0.data")))
  33. #define _LOCAL_RAM1_ __attribute__((section(".dram1.data")))
  34. #define ALIGN64 __attribute__((aligned(64)))
  35. #ifdef _USE_TCM_ALLOCATE
  36. #define NON_POOL_MEM (20*1024)
  37. #define POOL_SIZE1 ((XCHAL_DATARAM1_SIZE) - NON_POOL_MEM)
  38. #define POOL_SIZE0 ((XCHAL_DATARAM0_SIZE) - NON_POOL_MEM)
  39. uint8_t ALIGN64 pBankBuffPool0[POOL_SIZE0] _LOCAL_RAM0_;
  40. uint8_t ALIGN64 pBankBuffPool1[POOL_SIZE1] _LOCAL_RAM1_;
  41. #endif
  42. /****************************************************************************************
  43. log
  44. ****************************************************************************************/
  45. #include "dsp_ps_debug.h"
  46. #define DL_VRB(fmt, ...) //ps_debug(fmt,##__VA_ARGS__)
  47. #define DL_DBG(fmt, ...) ps_debug(fmt,##__VA_ARGS__)
  48. #define DL_INF(fmt, ...) ps_info(fmt,##__VA_ARGS__)
  49. #define DL_WRN(fmt, ...) ps_wrn(fmt,##__VA_ARGS__)
  50. #define DL_ERR(fmt, ...) ps_err(fmt,##__VA_ARGS__)
  51. //#include <vpu_log.h>
  52. /****************************************************************************************
  53. IVPEP Highlevel spec.
  54. .One and only one of the source or destination must be local data memory (DRam) and remain so for the duration of the transfer
  55. .One and only one of the source or destination must be external memory (AXI) and remain so for the duration of the transfer
  56. .DMA of external memory to external memory is not supported
  57. .DMA of local memory to local memory is not supported
  58. .DMA that switches direction during the transfer is not supported
  59. .moves two-dimensional (2-D) data tiles between the IVP-EP coreˇs local data RAMs (DRam0 and DRam1) and memories external to the core accessed via AXI
  60. local ram
  61. /\
  62. |
  63. |
  64. micro DMA controller
  65. |
  66. |
  67. \/
  68. external ram
  69. .register
  70. IVP_RER
  71. IVP_WER
  72. Enabling DMA
  73. Enabling NMI interrupt for error (descriptor and bus errors) reporting
  74. Pointers to a circular buffer of DMA descriptors
  75. Number of DMA descriptors to process
  76. Status registers
  77. .DMA completion may be signaled in the following ways:
  78. Reading a status or progress register that can be polled with an IVP_RER operation.
  79. Setting up a short DMA transaction to write a memory location with a completion flag.
  80. enerating an edge-triggered interrupt when enabled by a descriptor field.
  81. .DMA can only access the IVP-EP coreˇs DRams, not its IRam.
  82. .A DMA transaction is generally defined by the following parameters:
  83. Source and destination addresses
  84. Source and destination pitch (distance from the start of one row to the start of the next row in a 2-D transfer)
  85. Number of rows to transfer and number of bytes to transfer per row
  86. Block size limit for PIF requests
  87. Number of outstanding requests limit
  88. Control for completion interrupt notification
  89. .Descriptors have the following properties:
  90. Size 32B
  91. Aligned to 32B
  92. .Block size limit (i.e. maximum size) for DMA
  93. 0: Block 2 (32 bytes)
  94. 1: Block 4 (64 bytes)
  95. 2: Block 8 (128 bytes)
  96. 3: Block 16 (256 bytes)
  97. .Transfers with row lengths of 16 B or less have the following additional requirements:
  98. The number of bytes per row must be 1, 2, 4, 8, or 16
  99. Both the source and destination addresses must have the same 16B alignment
  100. The source and destination addresses must be aligned to the number of bytes per row
  101. .Transfers with row lengths greater than 16B transfer each row using one or more block (or burst) transactions. Block transaction sizes are 2, 4, 8, or 16 transfers, corresponding to 32B, 64B, 128B, or 256B respectively. The same block transaction size is used for the entire transfer  i.e., for all rows and all block transactions within each row. The following additional requirements apply:
  102. There must be a block transaction size that meets the following requirements  each row transfer will use the largest block size meeting these requirements that is no larger than the maximum block size specified in the descriptor:
  103. The number of bytes per row is an integer multiple of the block size
  104. The external memory address (source or destination) is aligned to the size of the block transaction
  105. The local memory address (source or destination) is aligned to the smaller of the local memory width (64 B) or the block transaction length
  106. The row transfer must not cross a local memory DRam boundary
  107. ****************************************************************************************/
  108. /****************************************************************************************
  109. declaration
  110. ****************************************************************************************/
  111. #define _ALIGN_(a,b) ((((TUINT32)a+(b-1))/b)*b)
  112. /****************************************************************************************
  113. declaration
  114. ****************************************************************************************/
  115. TBOOL init();
  116. TBOOL uninit();
  117. TBOOL config(xvTile *tile_obj, uint32_t tile_x,uint32_t tile_y );
  118. xvTile *setup(uint64_t imgBuff,uint32_t frame_BuffSize,int32_t frame_width, int32_t frame_height, int32_t frame_pitch, uint8_t frame_pixRes, uint8_t frame_numChannels, uint8_t frame_paddingtype, uint32_t frame_paddingVal,
  119. int32_t tile_BuffSize, int32_t tile_width, uint16_t tile_height, int32_t tile_pitch, uint16_t tile_edgeWidth, uint16_t tile_edgeHeight, int32_t tile_color, uint16_t tile_type, int32_t alignType);
  120. TBOOL release(xvTile *tile_obj);
  121. TUINT32 store(xvTile *tile_obj, uint64_t pdst64, uint64_t psrc64, uint32_t srcPitchBytes, uint32_t dstPitchBytes, uint32_t numRows, uint32_t numBytesPerRow, uint32_t interruptOnCompletion);
  122. TUINT32 copy(xvTile *tile_obj,uint64_t pdst64, uint64_t psrc64, uint32_t srcPitchBytes, uint32_t dstPitchBytes, uint32_t numRows, uint32_t numBytesPerRow, uint32_t interruptOnCompletion);
  123. TBOOL stop();
  124. TBOOL stall();
  125. TBOOL isDone();
  126. TBOOL align_check(xvTile *tile_obj,uint64_t pdst64,uint64_t psrc64,TUINT32 srcPitchBytes,TUINT32 dstPitchBytes,TUINT32 numRows,TUINT32 numBytesPerRow,tm_dma_direction direction);
  127. TBOOL get_alignment(_IN_ xvTile *tile_obj,_IN_ TUINT32 numBytesPerRow,_OUT_ TUINT32 *rowByteAlign,_OUT_ TUINT32 *sysMemAlign,_OUT_ TUINT32 *SMemAlign);
  128. TUINT32 load(xvTile * tile_obj, uint64_t pdst64, uint64_t psrc64, uint32_t srcPitchBytes, uint32_t dstPitchBytes, uint32_t numRows, uint32_t numBytesPerRow, uint32_t interruptOnCompletion);
  129. TBOOL start(TUINT32, TUINT32);
  130. TBOOL waitDone(xvTile * tileIn_obj,xvTile * tileOut_obj);
  131. TBOOL waitLoadDone(xvTile * tile_obj);
  132. TBOOL waitStoreDone(xvTile * tile_obj);
  133. T_PTR allocateTcm(_IN_ TUINT32 num_bytes,_IN_ TUINT32 buf_id,_IN_ TUINT32 align);
  134. TBOOL freeTcm(void* ptr);
  135. /****************************************************************************************
  136. ****************************************************************************************/
  137. static volatile uint32_t idxDmaCnt[DMA_DIR_MAX] _LOCAL_RAM0_;
  138. static int32_t idma_requests[DMA_DIR_MAX][DMA_DESCR_CNT] _LOCAL_RAM0_;
  139. static uint32_t dmaAlignment _LOCAL_RAM0_ = 0;
  140. //static xv_dmaObject ALIGN64 dmaObj _LOCAL_DRAM0_;
  141. static xvTileManager ALIGN64 g_TMObj _LOCAL_RAM0_;
  142. static idma_max_block_t idma_block_index _LOCAL_RAM0_;
  143. //static xvFrame* frame;
  144. //static xvTile * tile;
  145. typedef struct intrCallbackDataStruct
  146. {
  147. int32_t intrCount;
  148. } intrCbDataStruct;
  149. intrCbDataStruct cbData0 _LOCAL_RAM0_;
  150. intrCbDataStruct cbData1 _LOCAL_RAM0_;
  151. /****************************************************************************
  152. * internal func
  153. * ****************************************************************/
  154. // IDMA error callback function
  155. static void errCallbackFunc0(idma_error_details_t* data)
  156. {
  157. DL_DBG("ERROR CALLBACK: iDMA in Error\n");
  158. g_TMObj.errFlag = (xvError_t)XVTM_ERROR;
  159. g_TMObj.idmaErrorFlag[0] = (xvError_t)XVTM_ERROR;
  160. printf("COPY FAILED, Error %d at desc:%p, PIF src/dst=%x/%x\n", data->err_type, (void *) data->currDesc, data->srcAddr, data->dstAddr);
  161. return;
  162. }
  163. // IDMA error callback function
  164. static void errCallbackFunc1(idma_error_details_t* data)
  165. {
  166. DL_DBG("ERROR CALLBACK: iDMA in Error\n");
  167. g_TMObj.errFlag = (xvError_t)XVTM_ERROR;
  168. g_TMObj.idmaErrorFlag[1] = (xvError_t)XVTM_ERROR;
  169. //printf("COPY FAILED, Error %d at desc:%p, PIF src/dst=%x/%x\n", data->err_type, (void *) data->currDesc, data->srcAddr, data->dstAddr);
  170. return;
  171. }
  172. // IDMA Interrupt callback function
  173. static void intrCallbackFunc0(void *pCallBackStr)
  174. {
  175. // DL_DBG("INTERRUPT CALLBACK : processing iDMA interrupt\n");
  176. ((intrCbDataStruct *) pCallBackStr)->intrCount++;
  177. return;
  178. }
  179. static void intrCallbackFunc1(void *pCallBackStr)
  180. {
  181. // DL_DBG("INTERRUPT CALLBACK : processing iDMA interrupt\n");
  182. ((intrCbDataStruct *) pCallBackStr)->intrCount++;
  183. return;
  184. }
  185. static TMDMA g_TMDMA _LOCAL_RAM0_ = {
  186. .init = init,
  187. .uninit = uninit,
  188. .setup = setup,
  189. .release = release,
  190. .config = config,
  191. .load = load,
  192. .store = store,
  193. .copy = copy,
  194. .start = start,
  195. .stop = stop,
  196. .stall = stall,
  197. .waitDone = waitDone,
  198. .waitLoadDone = waitLoadDone,
  199. .waitStoreDone = waitStoreDone,
  200. .isDone = isDone,
  201. .align_check = align_check,
  202. .get_alignment = get_alignment,
  203. .allocateTcm =allocateTcm,
  204. .freeTcm = freeTcm};
  205. /****************************************************************************************
  206. ****************************************************************************************/
  207. TMDMA*
  208. dmaif_getDMACtrl(void)
  209. {
  210. return &g_TMDMA;
  211. }
  212. /****************************************************************************************
  213. ****************************************************************************************/
  214. TBOOL
  215. init()
  216. {
  217. TBOOL ret = TTRUE;
  218. DL_VRB(":E");
  219. DL_DBG("%s\n",__func__);
  220. #if defined (_USE_IDMA_)
  221. idma_block_index= MAX_BLOCK_16;
  222. dmaAlignment = 32;
  223. #if 1
  224. void *buffPool[2]={NULL};
  225. int32_t buffSize[2]={0};
  226. uint32_t pool_num=0;
  227. #ifdef _USE_TCM_ALLOCATE
  228. pool_num=2;
  229. buffPool[0] = pBankBuffPool0;
  230. buffPool[1] = pBankBuffPool1;
  231. buffSize[0] = POOL_SIZE0;
  232. buffSize[1] = POOL_SIZE1;
  233. xvCreateTileManagerMultiChannel(&g_TMObj,idmaObjBuff,idmaObjBuff1,pool_num,buffPool,buffSize,
  234. (idma_err_callback_fn)errCallbackFunc0, (idma_err_callback_fn)errCallbackFunc1,
  235. intrCallbackFunc0, (void *) &cbData0,
  236. intrCallbackFunc1, (void *) &cbData1,
  237. DMA_DESCR_CNT, idma_block_index, MAX_PIF);
  238. #else
  239. xvInitIdmaMultiChannel(&g_TMObj,idmaObjBuff,idmaObjBuff1,DMA_DESCR_CNT, idma_block_index, MAX_PIF,
  240. (idma_err_callback_fn)errCallbackFunc0, (idma_err_callback_fn)errCallbackFunc1,
  241. intrCallbackFunc0, (void *) &cbData0,
  242. intrCallbackFunc1, (void *) &cbData1);
  243. #endif
  244. #else
  245. // int32_t timeoutTicks = 0;
  246. // int32_t initFlags = 0;
  247. // int32_t retVal;
  248. // retVal = idma_init(TM_IDMA_CH0, initFlags, idma_block_index, MAX_PIF, TICK_CYCLES_2, timeoutTicks, errCallbackFunc0);
  249. // retVal |= idma_init_loop(TM_IDMA_CH0, idmaObjBuff, IDMA_64B_DESC, DMA_DESCR_CNT, cbData0, intrCallbackFunc0);
  250. //
  251. // #ifdef _USE_MULTI_IDMA
  252. // retVal = idma_init(TM_IDMA_CH1, initFlags, idma_block_index, MAX_PIF, TICK_CYCLES_2, timeoutTicks, errCallbackFunc1);
  253. // retVal |= idma_init_loop(TM_IDMA_CH1, idmaObjBuff1, IDMA_64B_DESC, DMA_DESCR_CNT, cbData1, intrCallbackFunc1);
  254. //
  255. // #endif
  256. // idxDmaCnt[DMA_DIR_IN] =0;
  257. // idxDmaCnt[DMA_DIR_OUT] =0;
  258. #endif
  259. #endif
  260. DL_VRB(":X");
  261. return ret;
  262. }
  263. /****************************************************************************************
  264. ****************************************************************************************/
  265. TBOOL
  266. uninit()
  267. {
  268. TBOOL ret = TTRUE;
  269. DL_VRB(":E");
  270. xvResetTileManager(&g_TMObj);
  271. DL_VRB(":X");
  272. return ret;
  273. }
  274. /****************************************************************************************
  275. ****************************************************************************************/
  276. xvTile *
  277. setup(uint64_t imgBuff,uint32_t frame_BuffSize,int32_t frame_width, int32_t frame_height, int32_t frame_pitch, uint8_t frame_pixRes, uint8_t frame_numChannels, uint8_t frame_paddingtype, uint32_t frame_paddingVal,
  278. int32_t tile_BuffSize, int32_t tile_width, uint16_t tile_height, int32_t tile_pitch, uint16_t tile_edgeWidth, uint16_t tile_edgeHeight, int32_t tile_color, uint16_t tile_type, int32_t alignType)
  279. {
  280. xvTile * tile;
  281. xvFrame * frame = xvCreateFrame(&g_TMObj,imgBuff, frame_BuffSize, frame_width, frame_height, frame_pitch, frame_pixRes, frame_numChannels, frame_paddingtype, frame_paddingVal);
  282. tile = xvCreateTile(&g_TMObj, tile_BuffSize, tile_width, tile_height, tile_pitch, tile_edgeWidth, tile_edgeHeight,tile_color, frame, tile_type, alignType);
  283. if((void *)XVTM_ERROR == (void *)tile)
  284. tile =NULL;
  285. return tile;
  286. }
  287. /****************************************************************************************
  288. ****************************************************************************************/
  289. TBOOL
  290. release(xvTile *tile_obj)
  291. {
  292. if(tile_obj==NULL)
  293. {
  294. return TFALSE;
  295. }
  296. xvFrame * frame = tile_obj->pFrame;
  297. if(XVTM_ERROR ==xvFreeBuffer(&g_TMObj,XV_TILE_GET_BUFF_PTR(tile_obj)))
  298. {
  299. return TFALSE;
  300. }
  301. if(XVTM_ERROR==xvFreeTile(&g_TMObj,tile_obj))
  302. {
  303. return TFALSE;
  304. }
  305. if(XVTM_ERROR==xvFreeFrame(&g_TMObj,frame))
  306. {
  307. return TFALSE;
  308. }
  309. return TTRUE;
  310. }
  311. /****************************************************************************************
  312. ****************************************************************************************/
  313. TBOOL
  314. config(xvTile * tile_obj,
  315. uint32_t tile_x,
  316. uint32_t tile_y)
  317. {
  318. TBOOL ret = TTRUE;
  319. DL_VRB(":E");
  320. if(tile_obj == NULL)
  321. {
  322. return TFALSE;
  323. }
  324. XV_TILE_SET_X_COORD(tile_obj, tile_x);
  325. XV_TILE_SET_Y_COORD(tile_obj, tile_y);
  326. DL_VRB(":X");
  327. return ret;
  328. }
  329. /****************************************************************************************
  330. ****************************************************************************************/
  331. TUINT32
  332. load(xvTile * tile_obj, uint64_t pdst64, uint64_t psrc64, uint32_t srcPitchBytes, uint32_t dstPitchBytes, uint32_t numRows, uint32_t numBytesPerRow, uint32_t interruptOnCompletion)
  333. {
  334. numBytesPerRow = (_ALIGN_(numBytesPerRow,dmaAlignment) > dstPitchBytes) ? dstPitchBytes : _ALIGN_(numBytesPerRow,dmaAlignment);
  335. #ifndef _USE_IDMA_
  336. copy(g_TMObj, psrc, pdst, srcPitchBytes, dstPitchBytes, numRows, numBytesPerRow, interruptOnCompletion);
  337. #else
  338. if(tile_obj)
  339. {
  340. int32_t ret = xvReqTileTransferInFastMultiChannel(TM_IDMA_CH0,&g_TMObj,tile_obj,interruptOnCompletion);
  341. return ret==XVTM_SUCCESS?TTRUE:TFALSE;
  342. }
  343. else
  344. {
  345. if (DMA_DESCR_CNT <= idxDmaCnt[DMA_DIR_IN]) {
  346. DL_ERR("desc full(%d)",idxDmaCnt[DMA_DIR_IN]);
  347. return 0;
  348. }
  349. //from sysram to local
  350. int32_t id = xvAddIdmaRequestMultiChannel_wide(TM_IDMA_CH0,&g_TMObj,pdst64,psrc64,numBytesPerRow,numRows,srcPitchBytes,dstPitchBytes,interruptOnCompletion);
  351. if ( 0 != numBytesPerRow && 0 != numRows ) {
  352. idma_requests[DMA_DIR_IN][idxDmaCnt[DMA_DIR_IN]]=id;
  353. idxDmaCnt[DMA_DIR_IN]++;
  354. }
  355. }
  356. #endif
  357. return (numBytesPerRow*numRows);
  358. }
  359. /****************************************************************************************
  360. ****************************************************************************************/
  361. TUINT32
  362. store(xvTile * tile_obj, uint64_t pdst64, uint64_t psrc64, uint32_t srcPitchBytes, uint32_t dstPitchBytes, uint32_t numRows, uint32_t numBytesPerRow, uint32_t interruptOnCompletion)
  363. {
  364. //
  365. numBytesPerRow = (_ALIGN_(numBytesPerRow,dmaAlignment) > dstPitchBytes) ? dstPitchBytes : _ALIGN_(numBytesPerRow,dmaAlignment);
  366. #ifndef _USE_IDMA_
  367. copy(g_TMObj, pdst64, psrc64, srcPitchBytes, dstPitchBytes, numRows, numBytesPerRow, interruptOnCompletion);
  368. #else
  369. if(tile_obj)
  370. {
  371. int32_t ret;
  372. #ifdef _USE_MULTI_IDMA
  373. ret = xvReqTileTransferOutFastMultiChannel(TM_IDMA_CH1,&g_TMObj,tile_obj,interruptOnCompletion);
  374. #else
  375. ret = xvReqTileTransferOutFastMultiChannel(TM_IDMA_CH0,&g_TMObj,tile_obj,interruptOnCompletion);
  376. #endif
  377. return ret==XVTM_SUCCESS?TTRUE:TFALSE;
  378. }
  379. else
  380. {
  381. if ( DMA_DESCR_CNT <= idxDmaCnt[DMA_DIR_OUT] ) {
  382. DL_ERR("desc full(%d)",idxDmaCnt[DMA_DIR_OUT]);
  383. return 0;
  384. }
  385. //from sysram to local
  386. #ifdef _USE_MULTI_IDMA
  387. int32_t id = xvAddIdmaRequestMultiChannel_wide(TM_IDMA_CH1,&g_TMObj,pdst64,psrc64,numBytesPerRow,numRows,srcPitchBytes,dstPitchBytes,interruptOnCompletion);
  388. #else
  389. int32_t id = xvAddIdmaRequestMultiChannel_wide(TM_IDMA_CH0,&g_TMObj,pdst64,psrc64,numBytesPerRow,numRows,srcPitchBytes,dstPitchBytes,interruptOnCompletion);
  390. #endif
  391. if ( 0 != numBytesPerRow && 0 != numRows ) {
  392. idma_requests[DMA_DIR_OUT][idxDmaCnt[DMA_DIR_OUT]]=id;
  393. idxDmaCnt[DMA_DIR_OUT]++;
  394. }
  395. }
  396. #endif
  397. return (numBytesPerRow*numRows);
  398. }
  399. /****************************************************************************************
  400. ****************************************************************************************/
  401. TUINT32
  402. copy(xvTile * tile_obj, uint64_t pdst64, uint64_t psrc64, uint32_t srcPitchBytes, uint32_t dstPitchBytes, uint32_t numRows, uint32_t numBytesPerRow, uint32_t interruptOnCompletion)
  403. {
  404. uint32_t i;
  405. uint8_t *pdst = (uint8_t *)(uint32_t)pdst64;
  406. uint8_t *psrc = (uint8_t *)(uint32_t)psrc64;
  407. if((pdst64&0xffffffff00000000) | (psrc64&0xffffffff00000000))
  408. {
  409. return 0;
  410. }
  411. for ( i=0; i<numRows;i++) {
  412. memcpy(pdst+dstPitchBytes*i, psrc+srcPitchBytes*i, numBytesPerRow);
  413. }
  414. return (numBytesPerRow*numRows);
  415. }
  416. /****************************************************************************************
  417. ****************************************************************************************/
  418. TBOOL
  419. start(TUINT32 sDesc, TUINT32 eDesc)
  420. {
  421. TBOOL ret = TTRUE;
  422. DL_VRB(":E");
  423. DL_VRB(":X");
  424. return ret;
  425. }
  426. /****************************************************************************************
  427. ****************************************************************************************/
  428. TBOOL
  429. stop()
  430. {
  431. TBOOL ret = TTRUE;
  432. DL_VRB(":E");
  433. DL_VRB(":X");
  434. return ret;
  435. }
  436. /****************************************************************************************
  437. ****************************************************************************************/
  438. TBOOL
  439. stall()
  440. {
  441. TBOOL ret = TTRUE;
  442. DL_VRB(":E");
  443. DL_VRB(":X");
  444. return ret;
  445. }
  446. /****************************************************************************************
  447. ****************************************************************************************/
  448. TBOOL
  449. waitDone(xvTile * tileIn_obj,xvTile * tileOut_obj)
  450. {
  451. TBOOL ret = TTRUE;
  452. DL_VRB(":E");
  453. ret = waitLoadDone(tileIn_obj);
  454. ret &= waitStoreDone(tileOut_obj);
  455. DL_VRB(":X");
  456. return ret;
  457. }
  458. TBOOL
  459. waitLoadDone(xvTile * tile_obj)
  460. {
  461. TBOOL ret = TTRUE;
  462. DL_VRB(":E");
  463. if(tile_obj)
  464. {
  465. xvWaitForTileFastMultiChannel(TM_IDMA_CH0,&g_TMObj,tile_obj);
  466. }
  467. else
  468. {
  469. int32_t loop;
  470. int32_t done_flag=0;
  471. for(loop= 0; loop < idxDmaCnt[DMA_DIR_IN];loop++)
  472. {
  473. do{
  474. done_flag = xvCheckForIdmaIndexMultiChannel(TM_IDMA_CH0,&g_TMObj,idma_requests[DMA_DIR_IN][loop]);
  475. }while(!done_flag && g_TMObj.idmaErrorFlag[TM_IDMA_CH0]==XV_ERROR_SUCCESS);
  476. }
  477. }
  478. idxDmaCnt[DMA_DIR_IN] = 0;
  479. if( g_TMObj.idmaErrorFlag[TM_IDMA_CH0]!=XV_ERROR_SUCCESS)
  480. {
  481. DL_DBG("Fail\n");
  482. ret =TFALSE;
  483. }
  484. DL_VRB(":X");
  485. return ret;
  486. }
  487. TBOOL
  488. waitStoreDone(xvTile * tile_obj)
  489. {
  490. TBOOL ret = TTRUE;
  491. DL_VRB(":E");
  492. #ifdef _USE_MULTI_IDMA
  493. int32_t channle = TM_IDMA_CH1;
  494. #else
  495. int32_t channle = TM_IDMA_CH0;
  496. #endif
  497. if(tile_obj)
  498. {
  499. xvWaitForTileFastMultiChannel(channle,&g_TMObj,tile_obj);
  500. }
  501. else
  502. {
  503. int32_t loop;
  504. int32_t done_flag=0;
  505. for(loop= 0; loop < idxDmaCnt[DMA_DIR_OUT];loop++)
  506. {
  507. do{
  508. done_flag =xvCheckForIdmaIndexMultiChannel(channle,&g_TMObj,idma_requests[DMA_DIR_OUT][loop]);
  509. }while(!done_flag&&g_TMObj.idmaErrorFlag[channle]==XV_ERROR_SUCCESS);
  510. }
  511. }
  512. idxDmaCnt[DMA_DIR_OUT] = 0;
  513. if(g_TMObj.idmaErrorFlag[channle]!=XV_ERROR_SUCCESS)
  514. {
  515. DL_DBG("Fail");
  516. ret =TFALSE;
  517. }
  518. DL_VRB(":X");
  519. return ret;
  520. }
  521. /****************************************************************************************
  522. ****************************************************************************************/
  523. TBOOL
  524. isDone()
  525. {
  526. TBOOL ret = TTRUE;
  527. DL_VRB(":E");
  528. DL_VRB(":X");
  529. return ret;
  530. }
  531. /****************************************************************************************
  532. ****************************************************************************************/
  533. TBOOL
  534. align_check(xvTile * tile_obj,
  535. uint64_t pdst64,
  536. uint64_t psrc64,
  537. TUINT32 srcPitchBytes,
  538. TUINT32 dstPitchBytes,
  539. TUINT32 numRows,
  540. TUINT32 numBytesPerRow,
  541. tm_dma_direction direction)
  542. {
  543. TBOOL ret = TTRUE;
  544. int i = 0;
  545. DL_VRB(":E");
  546. /*
  547. .Transfers with row lengths of 16 B or less have the following additional requirements:
  548. The number of bytes per row must be 1, 2, 4, 8, or 16
  549. Both the source and destination addresses must have the same 16B alignment
  550. The source and destination addresses must be aligned to the number of bytes per row
  551. .Transfers with row lengths greater than 16B transfer each row using one or more block (or burst) transactions.
  552. Block transaction sizes are 2, 4, 8, or 16 transfers, corresponding to 32B, 64B, 128B, or 256B respectively.
  553. The same block transaction size is used for the entire transfer  i.e., for all rows and all block transactions
  554. within each row. The following additional requirements apply:
  555. There must be a block transaction size that meets the following requirements  each row transfer will use
  556. the largest block size meeting these requirements that is no larger than the maximum block size specified
  557. in the descriptor:
  558. The number of bytes per row is an integer multiple of the block size
  559. The external memory address (source or destination) is aligned to the size of the block transaction
  560. The local memory address (source or destination) is aligned to the smaller of the local memory width (64 B)
  561. or the block transaction length
  562. The row transfer must not cross a local memory DRam boundary
  563. */
  564. if ( 16 >= numBytesPerRow ) {
  565. for ( i=1; i<=5; i++ ) {
  566. if ( 0 == (numBytesPerRow >> i) ) {
  567. break;
  568. }
  569. }
  570. if ( 1<<i != numBytesPerRow ) {
  571. DL_ERR("invalid numBytesPerRow(%d)",numBytesPerRow);
  572. ret = TFALSE;
  573. }
  574. if ( 0 != ((TUINT32)psrc64&0x0F) || 0 != ((TUINT32)pdst64&0x0F) ) {
  575. DL_ERR("invalid psrc64/pdst alignment(0x%x/0x%x)",(TUINT32)psrc64,(TUINT32)pdst64);
  576. ret = TFALSE;
  577. }
  578. }else {
  579. int ialign = 1 << (idma_block_index + 5);
  580. if ( 0 != (numBytesPerRow&(~ialign)) ) {
  581. DL_ERR("invalid numBytesPerRow alignment(0x%x/0x%x)",numBytesPerRow,ialign);
  582. ret = TFALSE;
  583. }
  584. if ( DMA_DIR_IN == direction ) {
  585. /* external mem*/
  586. if ( 0 != ((TUINT32)psrc64&(~ialign)) ) {
  587. DL_ERR("invalid psrc64 alignment(0x%x/0x%x),dir(%d)",(TUINT32)psrc64,ialign,direction);
  588. ret = TFALSE;
  589. }
  590. /* internal mem.*/
  591. if ( 0 != ((TUINT32)psrc64&(~((64>ialign)?ialign:64))) ) {
  592. DL_ERR("invalid psrc64 alignment(0x%x/0x%x),dir(%d)",(TUINT32)psrc64,ialign,direction);
  593. ret = TFALSE;
  594. }
  595. }else {
  596. /* external mem*/
  597. if ( 0 != ((TUINT32)psrc64&(~ialign)) ) {
  598. DL_ERR("invalid psrc64 alignment(0x%x/0x%x),dir(%d)",(TUINT32)psrc64,ialign,direction);
  599. ret = TFALSE;
  600. }
  601. /* internal mem.*/
  602. if ( 0 != ((TUINT32)psrc64&(~((64>ialign)?ialign:64))) ) {
  603. DL_ERR("invalid psrc64 alignment(0x%x/0x%x),dir(%d)",(TUINT32)psrc64,ialign,direction);
  604. ret = TFALSE;
  605. }
  606. }
  607. }
  608. DL_VRB(":X");
  609. return ret;
  610. }
  611. /****************************************************************************************
  612. ****************************************************************************************/
  613. TBOOL
  614. get_alignment(_IN_ xvTile * tile_obj,
  615. _IN_ TUINT32 numBytesPerRow,
  616. _OUT_ TUINT32 *rowByteAlign,
  617. _OUT_ TUINT32 *sysMemAlign,
  618. _OUT_ TUINT32 *SMemAlign)
  619. {
  620. TBOOL ret = TTRUE;
  621. DL_VRB(":E");
  622. if ( 16 >= numBytesPerRow ) {
  623. *rowByteAlign = 1;
  624. *sysMemAlign = 0x10; /* 16B align*/
  625. *SMemAlign = 0x10; /* 16B align*/
  626. }
  627. else {
  628. int ialign = 1 << (idma_block_index + 5);
  629. *rowByteAlign = ialign;
  630. *sysMemAlign = ialign; /* 16B align*/
  631. *SMemAlign = (64>ialign)?ialign:64; /* 16B align*/
  632. }
  633. DL_VRB(":X");
  634. return ret;
  635. }
  636. /****************************************************************************************
  637. ****************************************************************************************/
  638. T_PTR
  639. allocateTcm(_IN_ TUINT32 num_bytes,
  640. _IN_ TUINT32 buf_id,
  641. _IN_ TUINT32 align)
  642. {
  643. T_PTR ptr=xvAllocateBuffer(&g_TMObj,num_bytes,buf_id,align);
  644. if(ptr ==(void*)XVTM_ERROR)
  645. {
  646. return 0;
  647. }
  648. return ptr;
  649. }
  650. /****************************************************************************************
  651. ****************************************************************************************/
  652. TBOOL
  653. freeTcm(void* ptr)
  654. {
  655. return xvFreeBuffer(&g_TMObj,ptr)==XVTM_ERROR?TFALSE:TTRUE;
  656. }