test_main.cbc 21 KB

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  1. #include <stdio.h>
  2. #include <stdlib.h>
  3. #include <string.h>
  4. #ifdef _XOS
  5. #define IDMA_APP_USE_XOS // will use inlined disable/enable int
  6. #endif
  7. #ifdef _XTOS
  8. #define IDMA_APP_USE_XTOS // will use inlined disable/enable int
  9. #endif
  10. #include "../src/driver/isp/isp_hw.h"
  11. #include "../src/driver/isp/post_isp_hw.h"
  12. #include "../src/include/isp_api.h"
  13. #include "../src/include/dsp_ps_debug.h"
  14. #include "dsp_ps_ns.h"
  15. #include "ps_sched.h"
  16. //#include "CppUTest/CommandLineTestRunner.h"
  17. //#include "CppUTest/TestHarness.h"
  18. #include "isp_hw.h"
  19. #include <xtensa/hal.h>
  20. #include <xtensa/idma.h>
  21. #include "dmaif.h"
  22. // Define this to enable the wide address API.
  23. #define IDMA_USE_WIDE_ADDRESS_COMPILE 1
  24. // Define this to enable the large Description API.
  25. #define IDMA_USE_64B_DESC 1
  26. #define IDMA_DEBUG 1
  27. IDMA_BUFFER_DEFINE(task_copy, 2, IDMA_64B_DESC);
  28. // IDMA_BUFFER_DEFINE(task_write, 1, IDMA_64B_DESC);
  29. #define TCM_SIZE (64 * 1024)
  30. #define HOR_RES 4096
  31. #define VER_RES 3192
  32. #define SIZE_PER_PEX_BIT 8
  33. #define LINE_SIZE ((HOR_RES * SIZE_PER_PEX_BIT + 7) / 8)
  34. #define N_LINE 16
  35. char temp_bufer_tcm[TCM_SIZE] __attribute__((section(".dram1.data")));
  36. #define FRAME_NUM 2
  37. #define N_BUFFER_NUM 3
  38. char dst_pic[FRAME_NUM][VER_RES * LINE_SIZE];
  39. char *ref_pic=(char *)0xc1000000;
  40. char *isp_ry_out=(char *)0xd0000000;
  41. #define MAX_ENTRY 1536
  42. uint32_t post_isp_tick[MAX_ENTRY];
  43. uint32_t isp_int_tick[MAX_ENTRY];
  44. int32_t post_isp_cnt;
  45. int32_t isp_int_cnt;
  46. //char source_pic[FRAME_NUM][VER_RES * LINE_SIZE];
  47. char frame_buffer[N_BUFFER_NUM][LINE_SIZE * N_LINE];
  48. int32_t bus_idle_flag;
  49. static TMDMA *idma_obj;
  50. static xvTile *tile_obj;
  51. void
  52. idmaErrCB(const idma_error_details_t* data)
  53. {
  54. idma_error_details_t* error = idma_error_details(IDMA_CHAN_FUNC_ARG);
  55. printf("COPY FAILED, Error 0x%x at desc:%p, PIF src/dst=%x/%x\n", error->err_type, (void*)error->currDesc, error->srcAddr, error->dstAddr);
  56. }
  57. volatile uint32_t do_cnt;
  58. void
  59. idmaDoneCB(void* data)
  60. {
  61. do_cnt=1;
  62. }
  63. static int idma_copy(uint64_t src_addr, uint64_t dst_addr, uint32_t block_size,
  64. idma_callback_fn cb) {
  65. // Construct wide pointers for the 3 buffers. Note that the addresses for
  66. // the two buffers in local memory must not have any of the high bits set or
  67. // else they'll look like sysmem addresses.
  68. int loop;
  69. int fragment_size = block_size % TCM_SIZE;
  70. int loop_num = block_size / TCM_SIZE;
  71. int ret = 0;
  72. int size = TCM_SIZE;
  73. loop_num = fragment_size ? loop_num + 1 : loop_num;
  74. uint32_t frame_counter = 0;
  75. uint32_t start,end;
  76. // idma_log_handler(idmaLogHander);
  77. for (loop = 0; loop < loop_num; loop++) {
  78. uint64_t dst1_wide =
  79. ((uint64_t)0xffffffff) & ((uint64_t)&temp_bufer_tcm[0]);
  80. uint64_t src1_wide = src_addr + size * loop;
  81. uint64_t dst2_wide = dst_addr + size * loop;
  82. if (loop == (loop_num - 1) && fragment_size) {
  83. size = fragment_size;
  84. }
  85. #if 0
  86. idma_init_task(task_copy, IDMA_64B_DESC, 2, cb, task_copy);
  87. idma_add_desc64_wide(task_copy, &dst1_wide, &src1_wide, size, 0);
  88. idma_add_desc64_wide(task_copy, &dst2_wide, &dst1_wide, size,
  89. DESC_NOTIFY_W_INT);
  90. do_cnt=0;
  91. ret = idma_schedule_task(task_copy);
  92. start = XT_RSR_CCOUNT();
  93. if (ret != IDMA_OK) {
  94. ps_debug("FAILED to schedule taskh: %d\n", ret);
  95. return -1;
  96. }
  97. idma_hw_wait_all();
  98. while(do_cnt==0)
  99. {
  100. ;
  101. }
  102. end = XT_RSR_CCOUNT();
  103. #else
  104. idma_obj->load(NULL,dst1_wide,src1_wide,size,size,1,size,1);
  105. idma_obj->store(NULL,dst2_wide,dst1_wide,size,size,1,size,1);
  106. idma_obj->waitDone(NULL,NULL);
  107. #endif
  108. // idma_tick[idma_cnt++]=end-start;
  109. // idma_tick[idma_cnt++]= *(uint32_t *)(0xffffffff&src_addr+122880);
  110. // uint32_t * src_buffer = (uint32_t*)(src_addr&0xffffffff);
  111. // uint32_t * dst_buffer = (uint32_t*)(dst_addr&0xffffffff);
  112. // if(src_buffer[0]!=dst_buffer[0])
  113. // {
  114. // printf("src addr:%x,value:%d,dst addr:%x,value:%d\n",src_buffer,src_buffer[0],
  115. // dst_buffer,dst_buffer[0]);
  116. // }
  117. }
  118. return 0;
  119. }
  120. static int compare(char *src, char *dst, uint32_t size) {
  121. int i;
  122. for (i = 0; i < size; i++) {
  123. if (src[i] != dst[i]) {
  124. printf("Compare fail,expect:%d,actrul:%d,at:%d\n", src[i], dst[i],
  125. i);
  126. return -1;
  127. }
  128. }
  129. return 0;
  130. }
  131. void mask_flag(uint32_t addr, uint32_t flag)
  132. {
  133. *(volatile uint32_t *)addr = flag;
  134. }
  135. int test_isp(uint16_t hor_res, uint16_t ver_res,EIsp_raw_fomrat raw_type,
  136. uint64_t isp_out_addr, uint32_t isp_out_size,uint32_t entry_num) {
  137. uint32_t frame_counter = 0;
  138. Sisp_buffer buffer_list[2];
  139. uint64_t frame_buffer_addr = ((uint64_t)0x0<<32)|(uint32_t)&dst_pic[frame_counter];
  140. int ret = 0;
  141. post_isp_cnt =0;
  142. isp_int_cnt =0;
  143. #if USE_TILE
  144. tile_obj = idma_obj->setup(isp_out_addr,isp_out_size£¬hor_res,entry_num,isp_out_size,1,1,0,0,
  145. 16*64,64,16,16*64£¬0,0,0,0,0);
  146. #endif
  147. isp_initialize(0);
  148. isp_handler_config(hor_res, ver_res, raw_type, entry_num,
  149. (uint64_t)isp_out_addr, isp_out_size);
  150. uint32_t frame_size = isp_get_frame_size();
  151. memset((void*)isp_out_addr,0x0,isp_out_size);
  152. memset((void*)frame_buffer_addr,0x0,frame_size);
  153. idma_init(0, MAX_BLOCK_16, 32, TICK_CYCLES_8, 100000, idmaErrCB);
  154. mask_flag(0x90000000,0xdead0000);
  155. while (frame_counter < FRAME_NUM) {
  156. if (isp_check_exeptional() == EISP_ERROR_OVER_FLOW) {
  157. ps_debug("Err ISP input is overflow\n");
  158. break;
  159. }
  160. uint64_t block_addr = 0;
  161. uint32_t block_size = 0;
  162. mask_flag(0x90000000,0xdead0001);
  163. if (isp_get_next_entry(buffer_list) != EISP_BOOL_TRUE) {
  164. // isp_interrupt_handler(NULL);
  165. continue;
  166. }
  167. int buffer_index;
  168. int line_in_entry =0;
  169. for(buffer_index=0;buffer_index<2;buffer_index++)
  170. {
  171. if(buffer_list[buffer_index].line_num==0){break;}
  172. if (idma_copy(buffer_list[buffer_index].start_addr,
  173. frame_buffer_addr + (get_n_counter()+line_in_entry) * isp_get_line_size(),
  174. buffer_list[buffer_index].size, idmaDoneCB) != 0) {
  175. ps_debug("idma copy error\n");
  176. ret = -1;
  177. mask_flag(0x90000004,0xdead0002);
  178. break;
  179. }
  180. line_in_entry +=buffer_list[buffer_index].line_num;
  181. }
  182. if ( isp_is_last_entry_pop_in_frame() == EISP_BOOL_TRUE) {
  183. mask_flag(0x90000008,0xdead000f);
  184. frame_counter++;
  185. // frame_counter =frame_counter%FRAME_NUM;
  186. frame_buffer_addr = ((uint64_t)0x0<<32)|(uint32_t)&dst_pic[frame_counter];
  187. }
  188. if (isp_check_exeptional() == EISP_ERROR_OVER_FLOW) {
  189. ps_debug("%s:line:%d,Err ISP input is overflow\n",__FUNCTION__,__LINE__);
  190. ret = -1;
  191. mask_flag(0x90000004,0xdead0003);
  192. break;
  193. }
  194. if (isp_pop_n_line(buffer_list[0].line_num+buffer_list[1].line_num) != EISP_BOOL_TRUE) {
  195. ps_debug("pop fail\n");
  196. ret = -1;
  197. mask_flag(0x90000004,0xdead0004);
  198. break;
  199. }
  200. }
  201. mask_flag(0x90000000,0xdead0005);
  202. isp_disable_inerrupt(0);
  203. int frame_index=0;
  204. for(frame_index=0;frame_index<FRAME_NUM;frame_index++)
  205. {
  206. ret |= compare((char *)dst_pic[frame_index], (char *)(ref_pic), frame_size);
  207. ps_debug("Compare frame:%d,the pic:%s\n",frame_index,ret==0?"pass":"fail");
  208. }
  209. // CHECK_EQUAL_ZERO(ret);
  210. // MEMCMP_EQUAL(dst_pic, source_pic, 128 *2);
  211. }
  212. void test_post_isp(uint16_t hor_res, uint16_t ver_res,EIsp_raw_fomrat raw_type,
  213. uint64_t post_isp_in_addr, uint32_t post_isp_in_size,uint32_t entry_num) {
  214. uint32_t frame_counter = 0;
  215. uint64_t src_buffer_addr = (uint64_t)0xb0000000;
  216. int ret = 0;
  217. int check=0;
  218. int M_counter = 0;
  219. Sisp_buffer buffer_list[2];
  220. uint32_t frame_size = isp_get_frame_size();
  221. // memset((void*)post_isp_in_addr,0x0,post_isp_in_size);
  222. // memset((void*)dst_buffer_addr,0x0,frame_size);
  223. post_isp_initialize(0);
  224. post_isp_handler_config(hor_res, ver_res, raw_type, entry_num,
  225. (uint64_t)post_isp_in_addr,post_isp_in_size);
  226. idma_init(0, MAX_BLOCK_16, 32, TICK_CYCLES_8, 100000, idmaErrCB);
  227. while (frame_counter < 5) {
  228. uint64_t block_addr = 0;
  229. uint32_t block_size = 0;
  230. if (post_isp_get_next_entry(buffer_list) != EISP_OK) {
  231. ret = -1;
  232. break;
  233. }
  234. if (get_m_counter() < 0) {
  235. break;
  236. }
  237. if (idma_copy(src_buffer_addr +
  238. post_isp_get_line_size() * get_m_counter(),
  239. buffer_list[0].start_addr, buffer_list[0].size, idmaDoneCB) != 0) {
  240. printf("idma copy error");
  241. ret = -1;
  242. break;
  243. }
  244. if (post_isp_check_exeptional() == EISP_ERROR_OVER_FLOW) {
  245. printf("Err Post ISP input is overflow");
  246. ret = -1;
  247. break;
  248. }
  249. if (post_isp_is_last_block_in_frame() == EISP_BOOL_TRUE) {
  250. frame_counter++;
  251. check=1;
  252. //src_buffer_addr = (uint64_t)&source_pic[frame_counter][0];
  253. }
  254. post_isp_push_entry(buffer_list[0].line_num);
  255. while(!post_isp_is_empty())
  256. {
  257. ;
  258. }
  259. if(check)
  260. {
  261. ret = compare((char *)ref_pic, (char *)isp_ry_out, hor_res*ver_res);
  262. printf("Compare the frame:%d,pic:%s\n",frame_counter,ret==0?"pass":"fail");
  263. memset((void*)isp_ry_out,0x0,hor_res*ver_res);
  264. check =0;
  265. }
  266. /********************************************************************/
  267. }
  268. // CHECK_EQUAL_ZERO(ret);
  269. // CHECK_EQUAL_ZERO(ret);
  270. // MEMCMP_EQUAL(dst_pic, source_pic, VER_RES * LINE_SIZE);
  271. }
  272. void test_post_isp_reset(uint16_t hor_res, uint16_t ver_res,EIsp_raw_fomrat raw_type,
  273. uint64_t post_isp_in_addr, uint32_t post_isp_in_size,uint32_t entry_num) {
  274. uint32_t frame_counter = 0;
  275. uint64_t src_buffer_addr = (uint64_t)0xb0000000;
  276. int ret = 0;
  277. int check=0;
  278. int M_counter = 0;
  279. Sisp_buffer buffer_list[2];
  280. uint32_t frame_size = isp_get_frame_size();
  281. memset((void*)post_isp_in_addr,0x0,post_isp_in_size);
  282. // memset((void*)dst_buffer_addr,0x0,frame_size);
  283. post_isp_initialize(0);
  284. post_isp_handler_config(hor_res, ver_res, raw_type, entry_num,
  285. (uint64_t)post_isp_in_addr,post_isp_in_size);
  286. idma_init(0, MAX_BLOCK_16, 32, TICK_CYCLES_8, 100000, idmaErrCB);
  287. while (frame_counter < 2) {
  288. uint64_t block_addr = 0;
  289. uint32_t block_size = 0;
  290. if (post_isp_get_next_entry(buffer_list) != EISP_OK) {
  291. ret = -1;
  292. break;
  293. }
  294. if (get_m_counter() < 0) {
  295. break;
  296. }
  297. if (idma_copy(src_buffer_addr +
  298. post_isp_get_line_size() * get_m_counter(),
  299. buffer_list[0].start_addr, buffer_list[0].size, idmaDoneCB) != 0) {
  300. printf("idma copy error");
  301. ret = -1;
  302. break;
  303. }
  304. if (post_isp_check_exeptional() == EISP_ERROR_OVER_FLOW) {
  305. printf("Err Post ISP input is overflow\n");
  306. ret = -1;
  307. break;
  308. }
  309. if (post_isp_is_last_block_in_frame() == EISP_BOOL_TRUE) {
  310. frame_counter++;
  311. check=1;
  312. //src_buffer_addr = (uint64_t)&source_pic[frame_counter][0];
  313. }
  314. if((frame_counter==0) && (post_isp_get_pushed_line_num()>=256))
  315. {
  316. printf("Post ISP Error Need reset\n");
  317. bus_idle_flag = 0;
  318. // CLEAR_POST_ISP_BUS(0);
  319. while(!bus_idle_flag)
  320. {
  321. ;
  322. }
  323. post_isp_soft_reset(0);
  324. printf("Post ISP reset finish\n");
  325. post_isp_register_interrupt(0);
  326. frame_counter++;
  327. memset((void*)isp_ry_out,0x0,hor_res*ver_res);
  328. continue;
  329. }
  330. post_isp_push_entry(buffer_list[0].line_num);
  331. while(!post_isp_is_empty())
  332. {
  333. ;
  334. }
  335. if(check)
  336. {
  337. ret = compare((char *)ref_pic, (char *)isp_ry_out, hor_res*ver_res);
  338. printf("Compare the frame:%d,pic:%s\n",frame_counter,ret==0?"pass":"fail");
  339. memset((void*)isp_ry_out,0x0,hor_res*ver_res);
  340. }
  341. /********************************************************************/
  342. }
  343. // CHECK_EQUAL_ZERO(ret);
  344. // CHECK_EQUAL_ZERO(ret);
  345. // MEMCMP_EQUAL(dst_pic, source_pic, VER_RES * LINE_SIZE);
  346. }
  347. void test_isp_post_isp(uint16_t hor_res, uint16_t ver_res,EIsp_raw_fomrat raw_type,
  348. uint64_t isp_out_addr, uint32_t isp_out_size,
  349. uint64_t post_isp_in_addr, uint32_t post_isp_in_size,uint32_t entry_num) {
  350. uint32_t frame_counter = 0;
  351. // uint64_t frame_buffer_addr = ((uint64_t)0x0<<32)|(uint32_t)post_isp_in_addr;
  352. Sisp_buffer isp_buffer_list[2];
  353. Sisp_buffer p_isp_buffer_list[2];
  354. int ret = 0;
  355. post_isp_cnt =0;
  356. isp_int_cnt =0;
  357. isp_initialize(0);
  358. isp_handler_config(hor_res, ver_res, raw_type, entry_num,
  359. (uint64_t)isp_out_addr, isp_out_size);
  360. post_isp_initialize(0);
  361. post_isp_handler_config(hor_res, ver_res, raw_type, entry_num,
  362. (uint64_t)post_isp_in_addr,post_isp_in_size);
  363. memset((void*)isp_out_addr,0x0,isp_out_size);
  364. memset((void*)post_isp_in_addr,0x0,isp_out_size);
  365. // memset((void*)frame_buffer_addr,0x0,frame_size);
  366. idma_init(0, MAX_BLOCK_16, 32, TICK_CYCLES_8, 100000, idmaErrCB);
  367. memset(0x90000000,0xff,128);
  368. mask_flag(0x90000000,0xdead0000);
  369. while (1) {
  370. if (isp_check_exeptional() == EISP_ERROR_OVER_FLOW) {
  371. mask_flag(0x90000004,0xdead0002);
  372. ps_debug("Err ISP input is overflow\n");
  373. break;
  374. }
  375. uint64_t post_isp_block_addr = 0;
  376. uint32_t post_isp_block_size = 0;
  377. mask_flag(0x90000020,frame_counter);
  378. mask_flag(0x90000028,0xdead0000|(XT_RSR_CCOUNT()&0xffff));
  379. if (isp_get_next_entry(isp_buffer_list) != EISP_BOOL_TRUE) {
  380. // isp_interrupt_handler(NULL);
  381. continue;
  382. }
  383. if (post_isp_get_next_entry(p_isp_buffer_list) != EISP_OK) {
  384. ps_debug("Err post_isp get fail\n");
  385. ret = -1;
  386. break;
  387. }
  388. if(isp_buffer_list[0].line_num+isp_buffer_list[1].line_num!=
  389. p_isp_buffer_list[0].line_num)
  390. {
  391. ps_debug("ISP- Post ISP buffer not match\n");
  392. }
  393. int buffer_index;
  394. int line_in_entry =0;
  395. for(buffer_index=0;buffer_index<2;buffer_index++)
  396. {
  397. if(isp_buffer_list[buffer_index].line_num==0){break;}
  398. #if 1
  399. if (idma_copy(isp_buffer_list[buffer_index].start_addr,
  400. p_isp_buffer_list[0].start_addr +line_in_entry * isp_get_line_size(),
  401. isp_buffer_list[buffer_index].size, idmaDoneCB) != 0) {
  402. printf("idma copy error\n");
  403. ret = -1;
  404. break;
  405. }
  406. #else
  407. // idma_obj->load(NULL,);
  408. #endif
  409. line_in_entry +=isp_buffer_list[buffer_index].line_num;
  410. }
  411. if (isp_check_exeptional() == EISP_ERROR_OVER_FLOW) {
  412. mask_flag(0x9000000c,0xdead0004);
  413. ps_debug("%s:line:%d,Err ISP input is overflow\n",__FUNCTION__,__LINE__);
  414. ret = -1;
  415. break;
  416. }
  417. if ( isp_is_last_entry_pop_in_frame() == EISP_BOOL_TRUE && post_isp_is_last_block_in_frame() == EISP_BOOL_TRUE) {
  418. frame_counter++;
  419. }
  420. if (isp_pop_n_line(line_in_entry) != EISP_BOOL_TRUE) {
  421. ps_debug("pop fail\n");
  422. mask_flag(0x90000014,0xdead0006);
  423. ret = -1;
  424. break;
  425. }
  426. if(post_isp_push_entry(line_in_entry)!=EISP_BOOL_TRUE){
  427. ps_debug("post isp push fail\n");
  428. mask_flag(0x90000018,0xdead0007);
  429. ret = -1;
  430. break;
  431. }
  432. /*trigger RY INT*/
  433. post_isp_pop_entry();
  434. }
  435. mask_flag(0x90000010,0xdead0005);
  436. ret = compare((char *)ref_pic, (char *)isp_ry_out, hor_res*ver_res);
  437. ps_debug("Compare the frame:%d,pic:%s\n",frame_counter,ret==0?"pass":"fail");
  438. }
  439. void print_tick()
  440. {
  441. int i;
  442. // if(idma_cnt>MAX_ENTRY ||isp_int_cnt>MAX_ENTRY )
  443. // {
  444. // printf("Count overflow idma count:%d,isp_int count:%d",idma_cnt,isp_int_cnt);
  445. // }
  446. // for(i=0;i<idma_cnt;i++)
  447. // {
  448. // printf("idma(%d) cost tick:%x\n",i,idma_tick[i]);
  449. // }
  450. for(i=0;i<isp_int_cnt-1;i++)
  451. {
  452. printf("isp int(%d) cost tick:%d\n",i,isp_int_tick[i+1]-isp_int_tick[i]);
  453. }
  454. }
  455. extern enum xrp_status ps_post_isp_config_message_handler(void* in_data,void* out_data);
  456. void test_ps_isp_algo_api()
  457. {
  458. if (0 != ps_xrp_device_int(0)) {
  459. fprintf(stderr, "xrp_open_device failed\n");
  460. abort();
  461. }
  462. if(0 != init_scheduler()){
  463. fprintf(stderr, "scheduler init failed\n");
  464. abort();
  465. }
  466. sisp_config_par isp_data=(sisp_config_par){
  467. .id=0,
  468. .hor=1920,
  469. .ver=1080,
  470. .data_fmt=EISP_RAW12_FORMAT_ALGIN1,
  471. .line_in_entry=16,
  472. .buffer_size = 1920*2*16,
  473. .buffer_addr=0xb1000000,
  474. };
  475. extern enum xrp_status ps_isp_config_message_handler(void* in_data,void* out_data);
  476. ps_isp_config_message_handler(&isp_data,NULL);
  477. spost_isp_config_par pisp_data=(spost_isp_config_par){
  478. .id=0,
  479. .hor=1920,
  480. .ver=1080,
  481. .data_fmt=EISP_RAW12_FORMAT_ALGIN1,
  482. .line_in_entry=16,
  483. .buffer_size = 1920*2*16,
  484. .buffer_addr=0xc0000000,
  485. };
  486. extern enum xrp_status ps_post_isp_config_message_handler(void* in_data,void* out_data);
  487. ps_post_isp_config_message_handler(&pisp_data,NULL);
  488. extern enum xrp_status ps_isp_algo_start(void* in_data,void* out_data);
  489. ps_isp_algo_start(NULL,NULL);
  490. ps_task_shedule();
  491. }
  492. int main() {
  493. idma_obj =dmaif_getDMACtrl();
  494. idma_obj->init();
  495. test_isp(640,480,EISP_RAW8_FORMAT,0xd0000000,480 * ispc_get_line_size(EISP_RAW8_FORMAT,
  496. 640),N_LINE);//pp_640x480_16Line_test Raw8
  497. // *(int *)0xa0000000 =0xdeadbeee;
  498. // test_isp(640,480,EISP_RAW8_FORMAT,0xe0100000,80*2* ispc_get_line_size(EISP_RAW8_FORMAT,
  499. // 640),80);//API
  500. // test_isp(640,480,EISP_RAW8_FORMAT,0xd0000000,2*N_LINE*ispc_get_line_size(EISP_RAW8_FORMAT,
  501. // 640),N_LINE); //pp_640x480_16Linex2_test
  502. // test_isp(1920,480,EISP_RAW12_FORMAT_ALGIN1,0xd0000000,480 * ispc_get_line_size(EISP_RAW12_FORMAT_ALGIN1,
  503. // 1920),N_LINE);// pp_640x480_16Line_test Raw12
  504. // test_isp(1920,480,EISP_RAW12_FORMAT_ALGIN1,0xd0000000,2*N_LINE * ispc_get_line_size(EISP_RAW12_FORMAT_ALGIN1,
  505. // 1920),N_LINE);// pp_1920x480_raw12_mode1_2X16Line Raw12
  506. // test_isp(1920,480,EISP_RAW12_FORMAT_ALGIN1,0xffe0000000,2*N_LINE * ispc_get_line_size(EISP_RAW12_FORMAT_ALGIN1,
  507. // 1920),N_LINE);// pp_1920x480_raw12_mode1_2X16Line Raw12
  508. // test_isp(1920,480,EISP_RAW12_FORMAT_ALGIN1,0xd0000000,2*32 * ispc_get_line_size(EISP_RAW12_FORMAT_ALGIN1,
  509. // 1920),32);// pp_1920x480_raw12_mode1_2X32Line Raw12 480/32*2=7.5
  510. // test_isp(1920,480,EISP_RAW12_FORMAT_ALGIN1,0xd0000000,2*64 * ispc_get_line_size(EISP_RAW12_FORMAT_ALGIN1,
  511. // 1920),64);// pp_1920x480_raw12_mode1_2X64Line Raw12 480/64=7.5 OK
  512. // test_post_isp(1920,1080,EISP_RAW8_FORMAT,0xc0000000,1080 * ispc_get_line_size(EISP_RAW8_FORMAT,
  513. // 1920),N_LINE); //ppr_format.RAW8.YUV422.mp16line
  514. // test_post_isp(640,480,EISP_RAW8_FORMAT,0xc0000000,480 * ispc_get_line_size(EISP_RAW8_FORMAT,
  515. // 640),N_LINE); //API
  516. // test_post_isp(1920,1080,EISP_RAW8_FORMAT,0xc0000000,2*N_LINE * ispc_get_line_size(EISP_RAW8_FORMAT,
  517. // 1920),N_LINE); //ppr_format.RAW8.YUV422.mp16line
  518. // test_post_isp(1920,1080,EISP_RAW12_FORMAT_ALGIN1,0xc0000000,2*16 * ispc_get_line_size(EISP_RAW12_FORMAT_ALGIN1,
  519. // 1920),16); //ppr_format.RAW12.YUV422.mp16lineX2
  520. // test_post_isp(1920,1080,EISP_RAW12_FORMAT_ALGIN1,0xffe0000000,2*16 * ispc_get_line_size(EISP_RAW12_FORMAT_ALGIN1,
  521. // 1920),16); //ppr_format.RAW12.YUV422.mp16lineX2
  522. // test_post_isp(1920,1080,EISP_RAW12_FORMAT_ALGIN1,0xc0000000,2*32 * ispc_get_line_size(EISP_RAW12_FORMAT_ALGIN1,
  523. // 1920),32); //ppr_format.RAW12.YUV422.mp32lineX2
  524. // test_post_isp(1920,1080,EISP_RAW12_FORMAT_ALGIN1,0xc0000000,2*64 * ispc_get_line_size(EISP_RAW12_FORMAT_ALGIN1,
  525. // 1920),64); //ppr_format.RAW12.YUV422.mp64lineX2
  526. // test_post_isp_reset(1920,1080,EISP_RAW12_FORMAT_ALGIN1,0xc0000000,2*16 * ispc_get_line_size(EISP_RAW12_FORMAT_ALGIN1,
  527. // 1920),16);
  528. // test_isp_post_isp(1920,1080,EISP_RAW12_FORMAT_ALGIN1,
  529. // 0xb1000000,2*N_LINE * ispc_get_line_size(EISP_RAW12_FORMAT_ALGIN1,1920),
  530. // 0xc0000000,2*N_LINE * ispc_get_line_size(EISP_RAW12_FORMAT_ALGIN1,1920),N_LINE);
  531. // // pp_1920x1080_raw12_mode1_2X16Line ppr_format.RAW12.YUV422.mp16lineX2
  532. // test_isp_post_isp(640,480,EISP_RAW8_FORMAT,
  533. // 0xe0100000,2*80 * ispc_get_line_size(EISP_RAW8_FORMAT,640),
  534. // 0xe0000000,2*80 * ispc_get_line_size(EISP_RAW8_FORMAT,640),80);// API
  535. // test_isp_post_isp(1920,1080,EISP_RAW12_FORMAT_ALGIN1,
  536. // 0xffe0000000,2*N_LINE * ispc_get_line_size(EISP_RAW12_FORMAT_ALGIN1,1920),
  537. // 0xffe00c0000,2*N_LINE * ispc_get_line_size(EISP_RAW12_FORMAT_ALGIN1,1920),N_LINE);
  538. // //pp_1920x1080_raw12_mode1_2X16Line ppr_format.RAW12.YUV422.mp16lineX2
  539. // test_ps_isp_algo_api();
  540. // print_tick();
  541. }