post_isp_hw.c 4.4 KB

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  1. /*
  2. * Copyright (c) 2021 Alibaba Group. All rights reserved.
  3. * License-Identifier: Apache-2.0
  4. *
  5. * Licensed under the Apache License, Version 2.0 (the "License"); you may
  6. * not use this file except in compliance with the License.
  7. * You may obtain a copy of the License at
  8. *
  9. * http://www.apache.org/licenses/LICENSE-2.0
  10. *
  11. * Unless required by applicable law or agreed to in writing, software
  12. * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
  13. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  14. * See the License for the specific language governing permissions and
  15. * limitations under the License.
  16. *
  17. */
  18. #include "post_isp_hw.h"
  19. #include "isp_common.h"
  20. #include "vi_hw_api.h"
  21. #include "dsp_ps_debug.h"
  22. #include <xtensa/config/core.h>
  23. #define POST_ISP_ENABLE_INTS()
  24. #define POST_ISP_DISABLE_INTS()
  25. #define POST_ISP_INT_DEBUG
  26. #define XCHAL_POST_ISP_INTERRUPT XCHAL_EXTINT4_NUM
  27. #define XCHAL_POST_ISP_INTERRUPT_LEVEL 15
  28. extern int32_t bus_idle_flag;
  29. extern Sisp_handler g_post_isp_handler;
  30. static uint32_t post_isp_tick[1536];
  31. static int32_t post_isp_cnt=0;
  32. static uint32_t isp_fram_start_tick=0;
  33. static uint32_t isp_fram_start_index=0;
  34. //static uint32_t drop_test_cnt=0;
  35. void post_isp_interrupt_handler(void *data) {
  36. uint32_t mi3 = READ_POST_ISP_M_INTERRUPT_STATUS_REG(0);
  37. uint32_t mi = ps_l32((volatile void *)POST_ISP_MI_MIS);
  38. uint32_t mi2 = ps_l32((volatile void *)POST_ISP_MI_MIS2);
  39. uint32_t mp_line_cnt = ps_l32((volatile void *)MI_MP_LINE_CNT);
  40. #ifdef POST_ISP_INT_DEBUG
  41. // post_isp_tick[post_isp_cnt++]=0xdead;
  42. post_isp_tick[post_isp_cnt++]=mi3;
  43. post_isp_tick[post_isp_cnt++]=mi;
  44. post_isp_tick[post_isp_cnt++]=mp_line_cnt;
  45. // post_isp_tick[post_isp_cnt++]=drop_test_cnt;
  46. post_isp_tick[post_isp_cnt++]=post_isp_get_poped_line_num();
  47. post_isp_cnt=post_isp_cnt&0x3ff;
  48. #endif
  49. if(mi3&POST_ISP_ENTRY_INT_CLEAR_MASK)
  50. {
  51. if(post_isp_get_status(0)== EHW_OK)
  52. {
  53. post_isp_pop_entry();
  54. }
  55. else if (post_isp_get_status(0)== EHW_RECOVERYING && (g_post_isp_handler.current_N_value<g_post_isp_handler.base.line_num_per_frame))
  56. {
  57. TRIGGER_POST_ISP_REG(0);
  58. g_post_isp_handler.current_N_value += g_post_isp_handler.base.line_num_per_entry;
  59. }
  60. CLEAR_POST_ISP_ENTRY_INT(0);
  61. }
  62. if (mi3&POST_ISP_BUS_IDLE_MASK)
  63. {
  64. CLEAR_POST_ISP_BUS_IDLE_INT(0);
  65. // bus_idle_flag=1; TODO post isp reset handle
  66. }
  67. /*if mp_ycbcr_frame_end, remap to ISP int and trigger to CPU*/
  68. if(mi&(POST_ISP_MP_FRAME_DONE_MASK|POST_ISP_SP1_FRAME_DONE_MASK|POST_ISP_SP2_FRAME_DONE_MASK))
  69. {
  70. // drop_test_cnt++;
  71. if (post_isp_get_status(0)== EHW_RECOVERYING)
  72. {
  73. post_isp_recovery_state_update(0);
  74. ps_s32(0x1<<11,(volatile void *)POST_ISP_ISP_ISR);
  75. }
  76. else
  77. {
  78. // // map INT
  79. // if((drop_test_cnt&0xf)==0)
  80. // {
  81. // ps_s32(0x1<<11,(volatile void *)POST_ISP_ISP_ISR);
  82. // }
  83. // else
  84. {
  85. if(mi&POST_ISP_MP_FRAME_DONE_MASK)
  86. ps_s32(0x1<<8,(volatile void *)POST_ISP_ISP_ISR);
  87. if(mi&POST_ISP_SP1_FRAME_DONE_MASK)
  88. ps_s32(0x1<<9,(volatile void *)POST_ISP_ISP_ISR);
  89. if(mi&POST_ISP_SP2_FRAME_DONE_MASK)
  90. ps_s32(0x1<<10,(volatile void *)POST_ISP_ISP_ISR);
  91. }
  92. }
  93. ps_s32((uint32_t)(0xffffffff),(volatile void *)POST_ISP_MI_ICR);
  94. }
  95. WRITE_POST_ISP_CLEAR_INTERRUPT_REG(0);
  96. return;
  97. }
  98. int32_t post_isp_register_interrupt(uint16_t id) {
  99. int32_t ret = 0;
  100. // Normally none of these calls should fail. We don't check them
  101. // individually, any one failing will cause this function to return failure.
  102. xthal_interrupt_sens_set(XCHAL_POST_ISP_INTERRUPT, 1); //0~ eage 1~ level
  103. xthal_interrupt_pri_set(XCHAL_POST_ISP_INTERRUPT,XCHAL_POST_ISP_INTERRUPT_LEVEL);
  104. ret += xtos_set_interrupt_handler(XCHAL_POST_ISP_INTERRUPT,
  105. post_isp_interrupt_handler, NULL, NULL);
  106. ret += xtos_interrupt_enable(XCHAL_POST_ISP_INTERRUPT);
  107. ps_debug("enable Post ISP interrupt %s,trace buf:0x%x\n",ret==0?"success":"fail",post_isp_tick);
  108. return ret;
  109. }
  110. int32_t post_isp_enable_inerrupt(uint16_t id) {
  111. int32_t ret = 0;
  112. ret = xtos_interrupt_enable(XCHAL_POST_ISP_INTERRUPT);
  113. ps_debug("enable Post ISP interrupt %s,trace buf:0x%x\n",ret==0?"success":"fail",post_isp_tick);
  114. return ret;
  115. }
  116. int32_t post_isp_disable_inerrupt(uint16_t id) {
  117. int32_t ret = 0;
  118. ret = xtos_interrupt_disable(XCHAL_POST_ISP_INTERRUPT);
  119. return ret;
  120. }
  121. void set_post_isp_ae_remap()
  122. {
  123. ps_s32(0x1<<19,(volatile void *)POST_ISP_ISP_ISR);
  124. }