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Linux_SDK_V1.0.2

thead_admin 1 year ago
parent
commit
94d5278286

+ 1 - 4
.settings/targets/xtensa/Release_Core0.bts

@@ -84,16 +84,13 @@
                     <StringListMapEntry>
                         <key>LinkerAdditionalOptions</key>
                         <value flag="" inheritance="append">
-                            <ListEntry>-Wl,--defsym,xrp_dsp_comm_base_magic=0x25000000</ListEntry>
+                            <ListEntry>-Wl,--defsym,xrp_dsp_comm_base_magic=0x20280000</ListEntry>
                         </value>
                     </StringListMapEntry>
                     <StringListMapEntry>
                         <key>Libraries</key>
                         <value flag="-l" inheritance="prepend">
                             <ListEntry>idma-xtos</ListEntry>
-                            <ListEntry>idma-debug-xtos</ListEntry>
-                            <ListEntry>idma</ListEntry>
-                            <ListEntry>idma-debug</ListEntry>
                             <ListEntry>xtutil</ListEntry>
                             <ListEntry>CppUTest</ListEntry>
                             <ListEntry>CppUTestExt</ListEntry>

+ 0 - 5
.settings/targets/xtensa/Release_Core0_FL.bts

@@ -85,11 +85,6 @@
                     <StringListMapEntry>
                         <key>Libraries</key>
                         <value flag="-l" inheritance="prepend">
-                            <ListEntry>idma</ListEntry>
-                            <ListEntry>idma-debug</ListEntry>
-                            <ListEntry>idma-debug-os</ListEntry>
-                            <ListEntry>idma-debug-xtos</ListEntry>
-                            <ListEntry>idma-os</ListEntry>
                             <ListEntry>idma-xtos</ListEntry>
                             <ListEntry>xtutil</ListEntry>
                             <ListEntry>CppUTest</ListEntry>

+ 0 - 5
.settings/targets/xtensa/Release_Core0_PI.bts

@@ -84,11 +84,6 @@
                     <StringListMapEntry>
                         <key>Libraries</key>
                         <value flag="-l" inheritance="prepend">
-                            <ListEntry>idma</ListEntry>
-                            <ListEntry>idma-debug</ListEntry>
-                            <ListEntry>idma-debug-os</ListEntry>
-                            <ListEntry>idma-debug-xtos</ListEntry>
-                            <ListEntry>idma-os</ListEntry>
                             <ListEntry>idma-xtos</ListEntry>
                             <ListEntry>xtutil</ListEntry>
                             <ListEntry>CppUTest</ListEntry>

+ 1 - 4
.settings/targets/xtensa/Release_Core1.bts

@@ -84,16 +84,13 @@
                     <StringListMapEntry>
                         <key>LinkerAdditionalOptions</key>
                         <value flag="" inheritance="append">
-                            <ListEntry>-Wl,--defsym,xrp_dsp_comm_base_magic=0x25000000</ListEntry>
+                            <ListEntry>-Wl,--defsym,xrp_dsp_comm_base_magic=0x20680000</ListEntry>
                         </value>
                     </StringListMapEntry>
                     <StringListMapEntry>
                         <key>Libraries</key>
                         <value flag="-l" inheritance="prepend">
                             <ListEntry>idma-xtos</ListEntry>
-                            <ListEntry>idma-debug-xtos</ListEntry>
-                            <ListEntry>idma</ListEntry>
-                            <ListEntry>idma-debug</ListEntry>
                             <ListEntry>xtutil</ListEntry>
                             <ListEntry>CppUTest</ListEntry>
                             <ListEntry>CppUTestExt</ListEntry>

+ 0 - 5
.settings/targets/xtensa/Release_Core1_FL.bts

@@ -91,11 +91,6 @@
                     <StringListMapEntry>
                         <key>Libraries</key>
                         <value flag="-l" inheritance="prepend">
-                            <ListEntry>idma</ListEntry>
-                            <ListEntry>idma-debug</ListEntry>
-                            <ListEntry>idma-debug-os</ListEntry>
-                            <ListEntry>idma-debug-xtos</ListEntry>
-                            <ListEntry>idma-os</ListEntry>
                             <ListEntry>idma-xtos</ListEntry>
                             <ListEntry>xtutil</ListEntry>
                             <ListEntry>CppUTest</ListEntry>

+ 0 - 5
.settings/targets/xtensa/Release_Core1_PI.bts

@@ -84,11 +84,6 @@
                     <StringListMapEntry>
                         <key>Libraries</key>
                         <value flag="-l" inheritance="prepend">
-                            <ListEntry>idma</ListEntry>
-                            <ListEntry>idma-debug</ListEntry>
-                            <ListEntry>idma-debug-os</ListEntry>
-                            <ListEntry>idma-debug-xtos</ListEntry>
-                            <ListEntry>idma-os</ListEntry>
                             <ListEntry>idma-xtos</ListEntry>
                             <ListEntry>xtutil</ListEntry>
                             <ListEntry>CppUTest</ListEntry>

+ 6 - 7
src/algo/algo.c

@@ -54,7 +54,7 @@ typedef struct cb_args{
 
 int dsp_dummy_algo(csi_dsp_algo_param_t* param)
 {
-	if(!param || param->buffer_num <2 )
+	if(!param)
 	{
 		return -1;
 	}
@@ -76,13 +76,12 @@ int dsp_dummy_algo(csi_dsp_algo_param_t* param)
     int fragment_size ;
     int loop_num ;
     static uint64_t temp_buf=0;
-    if(param->buffer_num==3)
+    if(param->buffer_num < 2)
     {
-    	if(temp_buf !=bufs[2].planes[0].buf_phy)
-    	{
-    		temp_buf = bufs[2].planes[0].buf_phy;
-    		printf("update temp_buf:0x%lx\n",*((uint32_t*)temp_buf));
-    	}
+
+		printf("buffer num %d is not expect %d\n",param->buffer_num,param->buf_desc_num);
+		return -1;
+
     }
     for(index=0;index<bufs->plane_count;index++)
     {

+ 5 - 8
src/core/ps_front_end_wrapper.c

@@ -106,6 +106,7 @@ static int get_isp_next_entry(int id, entry_struct_t *ctrl_info){
 	ctrl_info->frame_height = isp_get_frame_height();
 	ctrl_info->pitch= isp_buffer_list[0].line_size;
 	ctrl_info->pBuff =isp_buffer_list[0].start_addr;
+	ctrl_info->width = isp_buffer_list[0].width;
 	memset(&ctrl_info->meta,0x0,sizeof(csi_dsp_frame_meta_t));
 	return 0;
 }
@@ -118,14 +119,8 @@ static int get_post_isp_next_entry(int id, struct csi_dsp_buffer * buf_entry)
 	{
 		return -1;
 	}
-//	ctrl_info->frame=NULL;
-//	ctrl_info->x =0;
-//	ctrl_info->y= isp_get_pushed_line_num();
-//	ctrl_info->pitch = p_isp_buffer.line_size;
-//	ctrl_info->pBuff = p_isp_buffer.start_addr;
-//	ctrl_info->height =p_isp_buffer.line_num;
-
-//	buf_entry->width = p_isp_buffer.
+
+	buf_entry->width = p_isp_buffer.width;
 	buf_entry->height = p_isp_buffer.line_num;
 	buf_entry->format = p_isp_buffer.fmt;
 	buf_entry->plane_count=1;
@@ -173,6 +168,7 @@ static int get_vipre_next_entry(int id, entry_struct_t *ctrl_info){
 	ctrl_info->frame_height = vipre_get_frame_height();
 	ctrl_info->height= buffer_list.line_num;
 	ctrl_info->pitch= buffer_list.line_size;
+	ctrl_info->width = buffer_list.width;
 	ctrl_info->pBuff =buffer_list.start_addr[0];
 	if(ctrl_info->frame_height == ctrl_info->height)
 	{
@@ -288,6 +284,7 @@ enum xrp_status sw_be_asgin_buf(int id ,sw_be_config_par* cfg)
 	int i,buf_id;
 	if((g_sw_be_hands[id].valid_buf_num+cfg->num_buf) >g_sw_be_hands[id].buf_num)
 	{
+		ps_err("new buffer:%d,and valid buffer:%d,exceed limit:%d\n",cfg->num_buf,g_sw_be_hands[id].valid_buf_num,g_sw_be_hands[id].buf_num);
 		return XRP_STATUS_FAILURE;
 	}
 	buf_id = g_sw_be_hands[id].head_id+g_sw_be_hands[id].valid_buf_num;

+ 36 - 3
src/core/ps_sched.c

@@ -541,6 +541,7 @@ static inline void fill_hw_task_algo_param(csi_dsp_algo_param_t* param,entry_str
 		param->extra_param_ptr->end_line = in_info->y+in_info->height;
 		param->extra_param_ptr->total_line = in_info->frame_height;
 	}
+
 //	if(in_info->meta)
 	{
 		param->extra_param_ptr->frame_meta.temp_projector = in_info->meta.temp_projector;
@@ -638,6 +639,23 @@ static inline enum xrp_status  dsp_process_sw_task(void *context,
 	return XRP_STATUS_SUCCESS;
 }
 
+static inline csi_dsp_report_e dsp_convert_error_to_report(ehw_error_code err_code)
+{
+	switch(err_code)
+	{
+		case EHW_ERROR_VIPRE_NM_OVERFLOW_FLOW:
+				return CSI_DSP_REPORT_HW_VIPRE_NM_OVERFLOW_FLOW;
+		case EHW_ERROR_VIPRE_FIFO_OVER_FLOW:
+				return CSI_DSP_REPORT_HW_VIPRE_FIFO_ERROR;
+		case EHW_ERROR_VIPRE_BUS_ERROR:
+				return CSI_DSP_REPORT_HW_VIPRE_BUS_ERROR;
+		default:
+			ps_wrn("can't find valid map report id\n");
+			return CSI_DSP_REPORT_MAX;
+	}
+
+}
+
 static enum task_result  dsp_process_hw_task(void* context)
 {
 	dsp_task_t *task = (dsp_task_t *)context;
@@ -662,6 +680,15 @@ static enum task_result  dsp_process_hw_task(void* context)
 			}
 			return PS_TASK_FAILURE_WITH_REPORT;
 		}
+		if(task->task_fe.get_state(task->task_fe.id)>=EHW_ERROR_HW_ERR && task->task_fe.get_state(task->task_fe.id)<=EHW_ERROR_HW_ERR_END)
+		{
+			if(task->report_info.buf)
+			{
+				csi_dsp_report_e report_id = dsp_convert_error_to_report(task->task_fe.get_state(task->task_fe.id));
+				ps_fill_report(task->report_info.buf,report_id,NULL,0);
+			}
+			return PS_TASK_FAILURE_WITH_REPORT;
+		}
 		return PS_TASK_FAILURE;
 	}
 #if 0
@@ -711,12 +738,18 @@ static enum task_result  dsp_process_hw_task(void* context)
 
 	if(task->task_be.entry_start(task->task_be.id,&out_info))
 	{
-
+		ps_wrn("Be trigger fail\n");
 		if(task->task_be.get_state(task->task_be.id) < 0)
 		{
-			return PS_TASK_FAILURE_WITH_REPORT;
+			if(task->type == CSI_DSP_TASK_HW_TO_SW)
+				return PS_TASK_FAILURE_WITH_REPORT;
+
+			if(task->task_be.get_state(task->task_be.id)==EHW_ERROR_OVER_FLOW)
+			{
+				task->task_fe.update_state(task->task_fe.id);
+				task->task_be.update_state(task->task_be.id);
+			}
 		}
-		ps_wrn("Be trigger fail\n");
 		return PS_TASK_FAILURE;
 	}
 

+ 6 - 4
src/core/ps_sched.h

@@ -32,6 +32,7 @@
 #include "csi_dsp_task_defs.h"
 #include "csi_dsp_post_process_defs.h"
 #include "csi_dsp_types.h"
+#include "isp_common.h"
 #define PS_MAX_TASK_TYPE   16
 
 #define DSP_REPORT_TO_HOST_FLAG  0x10000000
@@ -75,11 +76,11 @@ typedef struct entry_struct{
     uint64_t  pBuff;
 	uint16_t  x;
 	uint16_t  y;
-    int16_t   width;
     int16_t   height;
     int16_t   fmt;
     int16_t   pitch;
     uint32_t  frame_height;
+    uint32_t   width;
     csi_dsp_frame_meta_t meta;
 }entry_struct_t;
 
@@ -146,9 +147,9 @@ typedef struct  {
 }s_schduler_t;
 
 typedef enum buffer_status{
-	DSP_BUF_STATUS_FREE =-40,     // the buf is not allocted
-	DSP_BUF_STATUS_INVALID,
-	DSP_BUF_STATUS_NO_MEMORY,
+	DSP_BUF_STATUS_FREE = EHW_ERROR_SW_ERR_1,     // the buf is not allocted
+	DSP_BUF_STATUS_INVALID = EHW_ERROR_SW_ERR_2,
+	DSP_BUF_STATUS_NO_MEMORY = EHW_ERROR_SW_ERR_3,
 	DSP_BUF_STATUS_ALLOCTED = 0,	// the buf is allocted,normal running
 }buffer_status_e;
 
@@ -188,6 +189,7 @@ extern struct xrp_device * ps_xrp_device_int(int idx);
 extern int ps_register_cmd_handler(unsigned char * nsid,xrp_command_handler *cmd_handler,void * context);
 
 extern int ps_wait_host_sync();
+extern void ps_dsp_init_done();
 extern int ps_send_report(uint32_t id);
 extern int ps_report_avaiable();
 extern int ps_task_interrupt_unregister(int32_t pri,uint32_t intrnum);

+ 1 - 1
src/core/ps_sched_main.c

@@ -77,7 +77,7 @@ int main(void)
 		fprintf(stderr, "scheduler init failed\n");
 		abort();
     }
-
+    ps_dsp_init_done();
     ps_task_enable_common_task();
     ps_task_shedule(device);
 

+ 5 - 0
src/core/ps_xrp_wrapper.c

@@ -89,6 +89,11 @@ int ps_wait_host_sync()
     return 0;
 }
 
+void ps_dsp_init_done()
+{
+	xrp_device_init_done(device);
+}
+
 int ps_send_report(uint32_t id)
 {
 

+ 4 - 0
src/driver/common/isp_common.c

@@ -27,6 +27,7 @@ int32_t ispc_base_info_update(Sisp_control_info *base_info, uint16_t hor_res,
     base_info->line_num_per_buffer = buffer_size / line_size;
     base_info->frame_buffer_addr = buffer_addr;
     base_info->format = raw_type;
+    base_info->pixel_per_line = hor_res;
     return EHW_OK;
 }
 uint32_t ispc_check_exeptional(Sisp_handler *handler) {
@@ -62,6 +63,7 @@ Eisp_bool ispc_get_entry_to_pop(const Sisp_handler *handler,const uint16_t line_
 		buffer_list[0].start_addr = info->frame_buffer_addr + get_head_fifo(fifo) * info->size_per_line;
 		buffer_list[0].size = buffer_list[0].line_num*info->size_per_line;
 		buffer_list[0].fmt = info->format;
+		buffer_list[0].width = info->pixel_per_line;
 		buffer_list[1].line_num =0;
 		buffer_list[1].start_addr = 0;
 		buffer_list[1].size = 0;
@@ -73,11 +75,13 @@ Eisp_bool ispc_get_entry_to_pop(const Sisp_handler *handler,const uint16_t line_
     	buffer_list[0].size = buffer_list[0].line_num*info->size_per_line;
        	buffer_list[0].line_size = info->size_per_line;
        	buffer_list[0].fmt = info->format;
+		buffer_list[0].width = info->pixel_per_line;
     	buffer_list[1].line_num = line_num - buffer_list[0].line_num;
     	buffer_list[1].start_addr = info->frame_buffer_addr;
     	buffer_list[1].size = buffer_list[1].line_num *info->size_per_line;
        	buffer_list[1].line_size = info->size_per_line;
        	buffer_list[1].fmt = info->format;
+		buffer_list[1].width = info->pixel_per_line;
 
     }
     return EISP_BOOL_TRUE;

+ 15 - 0
src/driver/common/isp_common.h

@@ -6,6 +6,7 @@
 #include <xtensa/xtensa-types.h>
 #include <xtensa/xtruntime.h>
 #include "csi_dsp_post_process_defs.h"
+#include "csi_dsp_types.h"
 #define ALWAYS_INLINE __attribute__((always_inline)) static inline
 #define ISP_SECTION __attribute__((section(".dram1.data")))
 #define PING_PONG 2
@@ -44,6 +45,15 @@ typedef enum {
     EHW_ERROR_OVER_FLOW,
     EHW_ERROR_POP_FAIL,
     EHW_ERROR_FRAME_SWITCH_FAIL,
+    EHW_ERROR_HW_ERR,
+    EHW_ERROR_VIPRE_NM_OVERFLOW_FLOW,
+    EHW_ERROR_VIPRE_FIFO_OVER_FLOW,
+    EHW_ERROR_VIPRE_BUS_ERROR,
+    EHW_ERROR_HW_ERR_END,
+    EHW_ERROR_SW_ERR_1,
+    EHW_ERROR_SW_ERR_2,
+    EHW_ERROR_SW_ERR_3,
+    EHW_ERROR_SW_ERR_4,
     EHW_OK = 0,
     EHW_INPUT_EMPRY,
     EHW_RECOVERYING,
@@ -70,6 +80,7 @@ typedef struct {
     uint16_t size_per_line;
     uint16_t line_num_per_buffer;
     uint16_t line_num_used_per_frame;
+    uint32_t pixel_per_line;
     csi_dsp_img_fmt_e format;
     uint64_t frame_buffer_addr;
 
@@ -103,16 +114,20 @@ typedef struct{
 	uint16_t fmt;
 	uint16_t line_num;
 	uint32_t size;
+	uint32_t width;
 	uint32_t line_size;
 	uint64_t start_addr;
 }Sisp_buffer;
 
 
 typedef struct {
+	/***************should algin with LED Driver Define**********************/
     uint64_t frame_cnt;
     uint64_t frame_ts_us;
     int32_t floodlight_temperature;
     int32_t projection_temperature;
+    /****************************extra define**********************************************/
+    bool even_odd_revert;
 } frame_meta_t;
 
 ALWAYS_INLINE void reset_fifo(Sfifo *ptr, uint16_t depth, int16_t base_index,uint16_t max) {

+ 42 - 54
src/driver/idma/dmaif.c

@@ -65,16 +65,14 @@ log
     .DMA of external memory to external memory is not supported
     .DMA of local memory to local memory is not supported
     .DMA that switches direction during the transfer is not supported
-    .moves two-dimensional (2-D) data tiles between the IVP-EP core¡¦s local data RAMs (DRam0 and DRam1) and memories external to the core accessed via AXI
+    .moves two-dimensional (2-D) data tiles between the IVP-EP coreˇs local data RAMs (DRam0 and DRam1) and memories external to the core accessed via AXI
 
     local ram
        /\
        |
-      512b
        |
     micro DMA controller
        |
-      128b
        |
        \/
     external ram
@@ -82,50 +80,41 @@ log
     .register
         IVP_RER
         IVP_WER
-            ƒÞ Enabling DMA
-            ƒÞ Enabling NMI interrupt for error (descriptor and bus errors) reporting
-            ƒÞ Pointers to a circular buffer of DMA descriptors
-            ƒÞ Number of DMA descriptors to process
-            ƒÞ Status registers
+            Enabling DMA
+            Enabling NMI interrupt for error (descriptor and bus errors) reporting
+            Pointers to a circular buffer of DMA descriptors
+            Number of DMA descriptors to process
+            Status registers
     .DMA completion may be signaled in the following ways:
-        ƒÞ Reading a status or progress register that can be polled with an IVP_RER operation.
-        ƒÞ Setting up a short DMA transaction to write a memory location with a completion flag.
-        ƒÞ Generating an edge-triggered interrupt when enabled by a descriptor field.
-    .DMA can only access the IVP-EP core¡¦s DRams, not its IRam.
+        	Reading a status or progress register that can be polled with an IVP_RER operation.
+       	 	Setting up a short DMA transaction to write a memory location with a completion flag.
+       		enerating an edge-triggered interrupt when enabled by a descriptor field.
+    .DMA can only access the IVP-EP coreˇs DRams, not its IRam.
     .A DMA transaction is generally defined by the following parameters:
-        ƒÞ Source and destination addresses
-        ƒÞ Source and destination pitch (distance from the start of one row to the start of the next row in a 2-D transfer)
-        ƒÞ Number of rows to transfer and number of bytes to transfer per row
-        ƒÞ Block size limit for PIF requests
-        ƒÞ Number of outstanding requests limit
-        ƒÞ Control for completion interrupt notification
+      		Source and destination addresses
+     		Source and destination pitch (distance from the start of one row to the start of the next row in a 2-D transfer)
+     		Number of rows to transfer and number of bytes to transfer per row
+      		Block size limit for PIF requests
+        	Number of outstanding requests limit
+        	Control for completion interrupt notification
     .Descriptors have the following properties:
-        ƒÞ Size 32B
-        ƒÞ Aligned to 32B
-    .mem footpring
-        0x101C Reserved
-        0x1018 Reserved
-        0x1014 Destination Pitch
-        0x1010 Source Pitch
-        0x100C Num of Rows
-        0x1008 Control
-        0x1004 Destination Address
-        0x1000 Source Address
+       		Size 32B
+    		Aligned to 32B
     .Block size limit (i.e. maximum size) for DMA
         0: Block 2 (32 bytes)
         1: Block 4 (64 bytes)
         2: Block 8 (128 bytes)
         3: Block 16 (256 bytes)
     .Transfers with row lengths of 16 B or less have the following additional requirements:
-        ƒÞ The number of bytes per row must be 1, 2, 4, 8, or 16
-        ƒÞ Both the source and destination addresses must have the same 16B alignment
-        ƒÞ The source and destination addresses must be aligned to the number of bytes per row
-    .Transfers with row lengths greater than 16B transfer each row using one or more block (or burst) transactions. Block transaction sizes are 2, 4, 8, or 16 transfers, corresponding to 32B, 64B, 128B, or 256B respectively. The same block transaction size is used for the entire transfer ¡V i.e., for all rows and all block transactions within each row. The following additional requirements apply:
-        ƒÞ There must be a block transaction size that meets the following requirements ¡V each row transfer will use the largest block size meeting these requirements that is no larger than the maximum block size specified in the descriptor:
-            ƒÞ The number of bytes per row is an integer multiple of the block size
-            ƒÞ The external memory address (source or destination) is aligned to the size of the block transaction
-            ƒÞ The local memory address (source or destination) is aligned to the smaller of the local memory width (64 B) or the block transaction length
-        ƒÞ The row transfer must not cross a local memory DRam boundary
+        	The number of bytes per row must be 1, 2, 4, 8, or 16
+       		Both the source and destination addresses must have the same 16B alignment
+        	The source and destination addresses must be aligned to the number of bytes per row
+    .Transfers with row lengths greater than 16B transfer each row using one or more block (or burst) transactions. Block transaction sizes are 2, 4, 8, or 16 transfers, corresponding to 32B, 64B, 128B, or 256B respectively. The same block transaction size is used for the entire transfer  i.e., for all rows and all block transactions within each row. The following additional requirements apply:
+        	There must be a block transaction size that meets the following requirements  each row transfer will use the largest block size meeting these requirements that is no larger than the maximum block size specified in the descriptor:
+            The number of bytes per row is an integer multiple of the block size
+            The external memory address (source or destination) is aligned to the size of the block transaction
+            The local memory address (source or destination) is aligned to the smaller of the local memory width (64 B) or the block transaction length
+        	The row transfer must not cross a local memory DRam boundary
 ****************************************************************************************/
 /****************************************************************************************
     declaration
@@ -158,15 +147,15 @@ TBOOL freeTcm(void* ptr);
 /****************************************************************************************
 
 ****************************************************************************************/
-static volatile uint32_t idxDmaCnt[DMA_DIR_MAX];
-static int32_t  idma_requests[DMA_DIR_MAX][DMA_DESCR_CNT];
-static uint32_t dmaAlignment = 0;
+static volatile uint32_t idxDmaCnt[DMA_DIR_MAX] _LOCAL_RAM0_;
+static int32_t  idma_requests[DMA_DIR_MAX][DMA_DESCR_CNT] _LOCAL_RAM0_;
+static uint32_t dmaAlignment _LOCAL_RAM0_ = 0;
 
 //static xv_dmaObject ALIGN64 dmaObj _LOCAL_DRAM0_;
 static xvTileManager ALIGN64 g_TMObj _LOCAL_RAM0_;
 
 
-static idma_max_block_t idma_block_index;
+static idma_max_block_t idma_block_index _LOCAL_RAM0_;
 //static xvFrame* frame;
 //static xvTile * tile;
 
@@ -216,7 +205,7 @@ static void intrCallbackFunc1(void *pCallBackStr)
 	return;
 }
 
-static TMDMA g_TMDMA = {
+static TMDMA g_TMDMA _LOCAL_RAM0_ = {
 			.init = init,
             .uninit = uninit,
             .setup = setup,
@@ -380,7 +369,7 @@ config(xvTile * tile_obj,
 TUINT32
 load(xvTile * tile_obj, uint64_t pdst64, uint64_t psrc64, uint32_t srcPitchBytes, uint32_t dstPitchBytes, uint32_t numRows, uint32_t numBytesPerRow, uint32_t interruptOnCompletion)
 {
-    //
+
     numBytesPerRow = (_ALIGN_(numBytesPerRow,dmaAlignment) > dstPitchBytes) ? dstPitchBytes : _ALIGN_(numBytesPerRow,dmaAlignment);
 
 #ifndef _USE_IDMA_
@@ -639,22 +628,21 @@ align_check(xvTile * tile_obj,
 
 /*
     .Transfers with row lengths of 16 B or less have the following additional requirements:
-        ƒÞ The number of bytes per row must be 1, 2, 4, 8, or 16
-        ƒÞ Both the source and destination addresses must have the same 16B alignment
-        ƒÞ The source and destination addresses must be aligned to the number of bytes per row
+        	The number of bytes per row must be 1, 2, 4, 8, or 16
+        	Both the source and destination addresses must have the same 16B alignment
+       	The source and destination addresses must be aligned to the number of bytes per row
     .Transfers with row lengths greater than 16B transfer each row using one or more block (or burst) transactions. 
      Block transaction sizes are 2, 4, 8, or 16 transfers, corresponding to 32B, 64B, 128B, or 256B respectively. 
-     The same block transaction size is used for the entire transfer ¡V i.e., for all rows and all block transactions 
+     The same block transaction size is used for the entire transfer  i.e., for all rows and all block transactions 
      within each row. The following additional requirements apply:
-        ƒÞ There must be a block transaction size that meets the following requirements ¡V each row transfer will use 
+        	There must be a block transaction size that meets the following requirements  each row transfer will use 
            the largest block size meeting these requirements that is no larger than the maximum block size specified
            in the descriptor:
-            ƒÞ The number of bytes per row is an integer multiple of the block size
-            ƒÞ The external memory address (source or destination) is aligned to the size of the block transaction
-            ƒÞ The local memory address (source or destination) is aligned to the smaller of the local memory width (64 B) 
+           	The number of bytes per row is an integer multiple of the block size
+            	The external memory address (source or destination) is aligned to the size of the block transaction
+           	The local memory address (source or destination) is aligned to the smaller of the local memory width (64 B) 
                or the block transaction length
-        ƒÞ The row transfer must not cross a local memory DRam boundary
-
+       	The row transfer must not cross a local memory DRam boundary
 */
     if ( 16 >= numBytesPerRow ) {
         for ( i=1; i<=5; i++ ) {

+ 1 - 1
src/driver/isp/isp_hw.c

@@ -27,7 +27,7 @@
 #define XCHAL_ISP_INTERRUPT_LEVEL  15
 
 static uint32_t isp_int_tick[1536];
-static int32_t isp_int_cnt =0;
+static uint32_t isp_int_cnt =0;
 extern Sisp_handler g_isp_handler;
 
 void isp_interrupt_handler(void *data) {

+ 2 - 2
src/driver/isp/post_isp_handler.c

@@ -80,6 +80,7 @@ int32_t post_isp_get_next_entry(Sisp_buffer *entry_info) {
     entry_info->size = entry_info->line_num*post_isp_info->size_per_line;
     entry_info->line_size = post_isp_info->size_per_line;
     entry_info->fmt = post_isp_info->format;
+    entry_info->width = post_isp_info->pixel_per_line;
     return EHW_OK;
 }
 
@@ -196,11 +197,10 @@ void post_isp_recovery_state_update(uint16_t id )
 			post_isp_fifo_reset(id);
 			g_post_isp_handler.status = EHW_RECOVERY_DONE;
 			break;
-		case EHW_ERROR_OVER_FLOW:
-			break;
 		case EHW_RECOVERY_DONE:
 			g_post_isp_handler.status = EHW_OK;
 			break;
+		case EHW_ERROR_OVER_FLOW:
 		default:
 			TRIGGER_POST_ISP_REG(0);
 			g_post_isp_handler.current_N_value += g_post_isp_handler.base.line_num_per_entry;

+ 30 - 12
src/driver/isp/post_isp_hw.c

@@ -32,22 +32,25 @@ static uint32_t post_isp_tick[1536];
 static int32_t post_isp_cnt=0;
 static uint32_t isp_fram_start_tick=0;
 static uint32_t isp_fram_start_index=0;
+//static uint32_t drop_test_cnt=0;
 void post_isp_interrupt_handler(void *data) {
 
- //   g_post_isp_handler.current_N_value = READ_POST_ISP_M_COUNTER_REG();
-//	isp_int_tick[isp_int_cnt++]=XT_RSR_CCOUNT();
+	uint32_t mi3 = READ_POST_ISP_M_INTERRUPT_STATUS_REG(0);
+	uint32_t mi = ps_l32((volatile void *)POST_ISP_MI_MIS);
+	uint32_t mi2 = ps_l32((volatile void *)POST_ISP_MI_MIS2);
+	uint32_t mp_line_cnt = ps_l32((volatile void *)MI_MP_LINE_CNT);
 #ifdef POST_ISP_INT_DEBUG
 //	post_isp_tick[post_isp_cnt++]=0xdead;
-	post_isp_tick[post_isp_cnt++]=READ_POST_ISP_M_INTERRUPT_STATUS_REG(0);
-	post_isp_tick[post_isp_cnt++]=ps_l32((volatile void *)POST_ISP_MI_MIS);
-	post_isp_tick[post_isp_cnt++]=ps_l32((volatile void *)MI_MP_LINE_CNT);
-	post_isp_tick[post_isp_cnt++]=ps_l32((volatile void *)POST_ISP_MI_MIS2);
+	post_isp_tick[post_isp_cnt++]=mi3;
+	post_isp_tick[post_isp_cnt++]=mi;
+	post_isp_tick[post_isp_cnt++]=mp_line_cnt;
+//	post_isp_tick[post_isp_cnt++]=drop_test_cnt;
 	post_isp_tick[post_isp_cnt++]=post_isp_get_poped_line_num();
 	post_isp_cnt=post_isp_cnt&0x3ff;
 
 #endif
 
-	if(READ_POST_ISP_M_INTERRUPT_STATUS_REG(0)&0x1)
+	if(mi3&POST_ISP_ENTRY_INT_CLEAR_MASK)
 	{
 		if(post_isp_get_status(0)== EHW_OK)
 		{
@@ -61,22 +64,37 @@ void post_isp_interrupt_handler(void *data) {
 
 		CLEAR_POST_ISP_ENTRY_INT(0);
 	}
-	if (READ_POST_ISP_M_INTERRUPT_STATUS_REG(0)&(0x1<<5))
+	if (mi3&POST_ISP_BUS_IDLE_MASK)
 	{
 		CLEAR_POST_ISP_BUS_IDLE_INT(0);
 //		bus_idle_flag=1;   TODO  post isp reset handle
 	}
 	/*if mp_ycbcr_frame_end, remap to ISP int and trigger to CPU*/
-	if(ps_l32((volatile void *)POST_ISP_MI_MIS)&0x1)
+	if(mi&(POST_ISP_MP_FRAME_DONE_MASK|POST_ISP_SP1_FRAME_DONE_MASK|POST_ISP_SP2_FRAME_DONE_MASK))
 	{
+//		drop_test_cnt++;
 		if (post_isp_get_status(0)== EHW_RECOVERYING)
 		{
 			post_isp_recovery_state_update(0);
+			ps_s32(0x1<<11,(volatile void *)POST_ISP_ISP_ISR);
 		}
-//		else
+		else
 		{
-			// map INT
-			ps_s32(0x1<<8,(volatile void *)POST_ISP_ISP_ISR);
+//			// map INT
+//			if((drop_test_cnt&0xf)==0)
+//			{
+//				ps_s32(0x1<<11,(volatile void *)POST_ISP_ISP_ISR);
+//			}
+//			else
+			{
+				if(mi&POST_ISP_MP_FRAME_DONE_MASK)
+					ps_s32(0x1<<8,(volatile void *)POST_ISP_ISP_ISR);
+				if(mi&POST_ISP_SP1_FRAME_DONE_MASK)
+					ps_s32(0x1<<9,(volatile void *)POST_ISP_ISP_ISR);
+				if(mi&POST_ISP_SP2_FRAME_DONE_MASK)
+					ps_s32(0x1<<10,(volatile void *)POST_ISP_ISP_ISR);
+			}
+
 		}
 
 		ps_s32((uint32_t)(0xffffffff),(volatile void *)POST_ISP_MI_ICR);

+ 4 - 0
src/driver/isp/post_isp_hw.h

@@ -29,6 +29,10 @@
 #define POST_ISP_BUS_IDLE_MASK   (0x1<<5)
 #define POST_ISP_SOFT_RESET_MASK (0x1<<20)
 #define POST_ISP_ENTRY_INT_CLEAR_MASK  (0x1<<0)
+#define POST_ISP_MP_FRAME_DONE_MASK  (0x1<<0)
+#define POST_ISP_SP1_FRAME_DONE_MASK  (0x1<<3)
+#define POST_ISP_SP2_FRAME_DONE_MASK  (0x1<<4)
+
 #define POST_ISP_MI_ICR              (POST_ISP_BASE_ADDR+0x16d8)
 #define POST_ISP_MI_MIS              (POST_ISP_BASE_ADDR+0x16d0)
 #define POST_ISP_MI_ICR1             (POST_ISP_BASE_ADDR+0x16dc)

+ 36 - 3
src/driver/vipre/vipre_handler.c

@@ -137,7 +137,7 @@ int32_t vipre_frame_mode_handler_config(uint32_t act_channel,uint16_t hor_res, u
 	}
 	g_vipre_handler.base_buffer_info.data_fmt= raw_type;
 	g_vipre_handler.base_buffer_info.line_num_per_buffer = ver_res;
-	g_vipre_handler.base_buffer_info.pixs_per_line = hor_res;
+	g_vipre_handler.base_buffer_info.pixel_per_line = hor_res;
 	g_vipre_handler.base_buffer_info.size_per_line = stride;
 	memcpy(&g_vipre_handler.buffer_info[start_side],&g_vipre_handler.base_buffer_info,sizeof(Svipre_buffer_list));
     reset_fifo(&g_vipre_handler.fifo[start_side],g_vipre_handler.base_buffer_info.buffer_num,0,g_vipre_handler.base_buffer_info.buffer_num);
@@ -158,6 +158,10 @@ Eisp_bool vipre_push_new_entry()
 		    	g_vipre_handler.status = EHW_ERROR_OVER_FLOW;
 		        return EISP_BOOL_FASE;
 		  }
+		  if(IS_VIPRE_BUFFER_READY(0,get_tail_fifo(vipre_fifo))==0)
+		  {
+			  ps_err("vipre hw frame done index is mismatch with sw\n");
+		  }
 		  vipre_store_frame_meta(vipre_fifo);
 		  if (push_fifo(vipre_fifo,1,0) == EISP_BOOL_FASE) {
 				ps_err("vipre push fail\n");
@@ -268,6 +272,12 @@ Eisp_bool vipre_get_entry_to_pop(const uint16_t line_num,Svipre_buffer *buffer_l
 static Eisp_bool even_odd_frame_match(uint16_t id,uint16_t frame_id)
 {
 	uint16_t is_even = frame_id&0x1;
+	frame_meta_t *frame_meta = &g_vipre_handler.meta[frame_id];
+	if(frame_meta->even_odd_revert == true)
+	{
+		/************revert the flag************/
+		is_even = is_even^0x1;
+	}
 	switch(id)
 	{
 		case 0:     //EVEN and ODD
@@ -326,6 +336,7 @@ Eisp_bool vipre_get_next_entry(uint16_t id,Svipre_buffer *buffer) {
     	buffer->size = g_vipre_handler.buffer_info[ping_pong_side].size_per_line*buffer->line_num;
     	buffer->line_size = g_vipre_handler.buffer_info[ping_pong_side].size_per_line;
     	buffer->fmt = g_vipre_handler.buffer_info[ping_pong_side].data_fmt;
+    	buffer->width = g_vipre_handler.buffer_info[ping_pong_side].pixel_per_line;
     	return EISP_BOOL_TRUE;
     }
     else
@@ -619,14 +630,36 @@ void vipre_recovery_state_update(uint16_t id )
 void vipre_store_frame_meta( Sfifo *vipre_fifo )
 {
     uint32_t index;
-
+    static int cnt = 0;
+    static bool even_odd_revert = false;
+    bool revert_flag;
 	index = get_tail_fifo(vipre_fifo);
+	frame_meta_t *local_meta = &g_vipre_handler.meta[index];
 	if(index<MAX_VIPRE_BUFFER && g_vipre_handler.frame_meta_reg)
 	{
-		memcpy(&g_vipre_handler.meta[index],g_vipre_handler.frame_meta_reg,sizeof(frame_meta_t));
+		memcpy(local_meta,g_vipre_handler.frame_meta_reg,sizeof(frame_meta_t));
+		revert_flag = ((index&0x1) == ((local_meta->frame_cnt-1)&0x1)) ? false:true;
+		if(revert_flag == even_odd_revert)
+		{
+			local_meta->even_odd_revert =even_odd_revert;
+			cnt = 0;
+
+		}else
+		{
+			cnt++;
+			/*******continue 3 frame revert then revert the flag**************************/
+			if(cnt>2)
+			{
+				cnt =0;
+				even_odd_revert = revert_flag;
+				ps_wrn("revert even odd flag:%d\n",even_odd_revert);
+			}
+			local_meta->even_odd_revert =even_odd_revert;
+		}
 	}else
 	{
 		ps_wrn("invalid index\n");
+		return;
 	}
 
 }

+ 2 - 1
src/driver/vipre/vipre_handler.h

@@ -41,7 +41,7 @@ typedef struct{
     uint16_t size_per_line;
 //    uint16_t stride_per_line;
     uint16_t line_num_per_buffer;
-	uint16_t pixs_per_line;
+	uint32_t pixel_per_line;
 	csi_dsp_img_fmt_e data_fmt;
 	struct {
 		  uint64_t buffer_addr[4];
@@ -94,6 +94,7 @@ typedef struct{
 	uint16_t channel_num;
 	uint16_t line_num;
 	uint16_t fmt;
+	uint32_t width;
 	uint32_t line_size;
 	uint32_t size;
 	uint64_t start_addr[MAX_VIPRE_CHANNEL];

+ 10 - 0
src/driver/vipre/vipre_hw.c

@@ -67,6 +67,16 @@ void vipre_interrupt_handler(void *data) {
     	vipre_pop_new_entry(1);
 //    	ps_err("VIPRE HW overflow N line:%d,N entry:%d\n",g_vipre_handler.current_NM,value);
     }
+    else if(vipre_int & VIPRE_BUS_ERR_INT_MASK)
+    {
+    	g_vipre_handler.status= EHW_ERROR_VIPRE_BUS_ERROR ;
+    	CLEAR_VIPRE_INTERRUPT_REG(0,VIPRE_BUS_ERR_INT_MASK);
+    }
+    else if(vipre_int &VIPRE_FIFO_OVER_ERR_INT_MASK)
+    {
+    	g_vipre_handler.status= EHW_ERROR_VIPRE_FIFO_OVER_FLOW;
+    	CLEAR_VIPRE_INTERRUPT_REG(0,(VIPRE_FIFO_OVER_ERR_INT_MASK));
+    }
     else
     {
     	CLEAR_VIPRE_INTERRUPT_REG(0,vipre_int);

+ 8 - 3
src/driver/vipre/vipre_hw.h

@@ -37,6 +37,8 @@
 #define VIPRE_FRAME_DONE_INT_MASK  ( 0x1<<0)
 #define VIPRE_N_LINE_DONE_INT_MASK (0x1<<1)
 #define VIPRE_OVERFLOW_INT_MASK   (0x1<<2)
+#define VIPRE_FIFO_OVER_ERR_INT_MASK (0x1<<4)
+#define VIPRE_BUS_ERR_INT_MASK      (0x1<<5)
 #define VIPRE_N_FRAME_END_INT_MASK  ( 0x1<<6)
 
 #define VIPRE_M_FRAME_DONE_STATUS_REG  (VIPRE_BASE_ADDR+0x244)
@@ -100,11 +102,14 @@ ALWAYS_INLINE void SET_VIPRE_ALL_ENTRY_DONE_REG(int32_t channel_id)
 
 ALWAYS_INLINE uint32_t READ_VIPRE_BUFFER_REG(int32_t channel_id)
 {
-//    uint32_t val=ps_l32((volatile void *)VIPRE_M_FRAME_DONE_STATUS_REG);
-//    ps_s32(val,(volatile void *)VIPRE_M_FRAME_DONE_STATUS_REG);
-//    return val;
 	return ps_l32((volatile void *)VIPRE_M_FRAME_DONE_STATUS_REG)>>((MAX_VIPRE_CHANNEL-1-channel_id)*MAX_VIPRE_BUFFER)&0xf;
 }
+ALWAYS_INLINE uint32_t IS_VIPRE_BUFFER_READY(int32_t channel_id,uint16_t buffer_index)
+{
+	uint32_t mask= 0x1<<(MAX_VIPRE_BUFFER-1-(buffer_index+1)%MAX_VIPRE_BUFFER);
+	uint32_t value = READ_VIPRE_BUFFER_REG(channel_id);
+	return mask&value;
+}
 
 ALWAYS_INLINE void SET_VIPRE_M_FRAME_BUFFER_READ_DONE(int32_t channel_id,uint16_t buffer_index)
 {

+ 6 - 1
src/include/csi_dsp_task_defs.h

@@ -88,10 +88,15 @@ typedef enum{
   CSI_DSP_REPORT_RY_ERR,
   CSI_DSP_REPORT_VI_PRE_ERR,
   CSI_DSP_REPORT_NO_BUF,
-
   CSI_DSP_REPORT_HEARTBEAT_ERR,
   CSI_DSP_HW_FRAME_DROP,
   CSI_DSP_REPORT_EXRA_PARAM,
+  CSI_DSP_REPORT_HW_ERROR,
+  CSI_DSP_REPORT_HW_VIPRE_NM_OVERFLOW_FLOW,
+  CSI_DSP_REPORT_HW_VIPRE_FIFO_ERROR,
+  CSI_DSP_REPORT_HW_VIPRE_BUS_ERROR,
+  CSI_DSP_REPORT_HW_ERROR_END,
+  CSI_DSP_REPORT_MAX
 }csi_dsp_report_e;
 
 typedef struct dsp_frame{

+ 2 - 0
src/include/xrp_api.h

@@ -596,6 +596,8 @@ void xrp_interrupt_on();
 void xrp_interrupt_off();
 
 void xrp_user_initialize(enum xrp_status *status);
+
+enum xrp_status xrp_device_init_done(struct xrp_device *device);
 #ifdef __cplusplus
 }
 #endif

+ 19 - 5
src/xrp-dsp/xrp_dsp.c

@@ -421,11 +421,11 @@ static void do_handshake(struct xrp_device *device)
 
 	process_sync_data(device, shared_sync->hw_sync_data);
 
-	xrp_s32ri(XRP_DSP_SYNC_DSP_TO_HOST, &shared_sync->sync);
-	dcache_region_writeback(&shared_sync->sync,
-				sizeof(shared_sync->sync));
-
-	xrp_hw_wait_device_irq();
+//	xrp_s32ri(XRP_DSP_SYNC_DSP_TO_HOST, &shared_sync->sync);
+//	dcache_region_writeback(&shared_sync->sync,
+//				sizeof(shared_sync->sync));
+//
+//	xrp_hw_wait_device_irq();
 
 	//xrp_hw_send_host_irq();
 
@@ -708,6 +708,20 @@ enum xrp_status xrp_device_sync(struct xrp_device *device)
 	return XRP_STATUS_FAILURE;
 
 }
+
+enum xrp_status xrp_device_init_done(struct xrp_device *device)
+{
+
+	struct xrp_dsp_sync_v2 *shared_sync = device->dsp_cmd;
+	xrp_s32ri(XRP_DSP_SYNC_DSP_TO_HOST, &shared_sync->sync);
+	dcache_region_writeback(&shared_sync->sync,
+				sizeof(shared_sync->sync));
+
+	xrp_hw_wait_device_irq();
+	return XRP_STATUS_SUCCESS;
+}
+
+
 enum xrp_status xrp_device_command_dispatch(struct xrp_device *device)
 {
 

+ 11 - 0
src/xrp-dsp/xrp_dsp_hw_simple.c

@@ -80,6 +80,17 @@ void xrp_hw_send_host_irq(void)
 	}
 }
 
+uint32_t xrp_hw_is_host_irq_pending(void)
+{
+	switch (host_irq_mode) {
+	case XRP_IRQ_LEVEL:
+		return  xrp_l32ai(host_mmio(host_irq_offset))& BIT(host_irq_bit);
+	default:
+		return 0;
+	}
+
+}
+
 void xrp_hw_wait_device_irq(void)
 {
 #if XCHAL_HAVE_INTERRUPTS