|
@@ -65,16 +65,14 @@ log
|
|
|
.DMA of external memory to external memory is not supported
|
|
|
.DMA of local memory to local memory is not supported
|
|
|
.DMA that switches direction during the transfer is not supported
|
|
|
- .moves two-dimensional (2-D) data tiles between the IVP-EP core¡¦s local data RAMs (DRam0 and DRam1) and memories external to the core accessed via AXI
|
|
|
+ .moves two-dimensional (2-D) data tiles between the IVP-EP coreˇs local data RAMs (DRam0 and DRam1) and memories external to the core accessed via AXI
|
|
|
|
|
|
local ram
|
|
|
/\
|
|
|
|
|
|
|
- 512b
|
|
|
|
|
|
|
micro DMA controller
|
|
|
|
|
|
|
- 128b
|
|
|
|
|
|
|
\/
|
|
|
external ram
|
|
@@ -82,50 +80,41 @@ log
|
|
|
.register
|
|
|
IVP_RER
|
|
|
IVP_WER
|
|
|
- ƒÞ Enabling DMA
|
|
|
- ƒÞ Enabling NMI interrupt for error (descriptor and bus errors) reporting
|
|
|
- ƒÞ Pointers to a circular buffer of DMA descriptors
|
|
|
- ƒÞ Number of DMA descriptors to process
|
|
|
- ƒÞ Status registers
|
|
|
+ Enabling DMA
|
|
|
+ Enabling NMI interrupt for error (descriptor and bus errors) reporting
|
|
|
+ Pointers to a circular buffer of DMA descriptors
|
|
|
+ Number of DMA descriptors to process
|
|
|
+ Status registers
|
|
|
.DMA completion may be signaled in the following ways:
|
|
|
- ƒÞ Reading a status or progress register that can be polled with an IVP_RER operation.
|
|
|
- ƒÞ Setting up a short DMA transaction to write a memory location with a completion flag.
|
|
|
- ƒÞ Generating an edge-triggered interrupt when enabled by a descriptor field.
|
|
|
- .DMA can only access the IVP-EP core¡¦s DRams, not its IRam.
|
|
|
+ Reading a status or progress register that can be polled with an IVP_RER operation.
|
|
|
+ Setting up a short DMA transaction to write a memory location with a completion flag.
|
|
|
+ enerating an edge-triggered interrupt when enabled by a descriptor field.
|
|
|
+ .DMA can only access the IVP-EP coreˇs DRams, not its IRam.
|
|
|
.A DMA transaction is generally defined by the following parameters:
|
|
|
- ƒÞ Source and destination addresses
|
|
|
- ƒÞ Source and destination pitch (distance from the start of one row to the start of the next row in a 2-D transfer)
|
|
|
- ƒÞ Number of rows to transfer and number of bytes to transfer per row
|
|
|
- ƒÞ Block size limit for PIF requests
|
|
|
- ƒÞ Number of outstanding requests limit
|
|
|
- ƒÞ Control for completion interrupt notification
|
|
|
+ Source and destination addresses
|
|
|
+ Source and destination pitch (distance from the start of one row to the start of the next row in a 2-D transfer)
|
|
|
+ Number of rows to transfer and number of bytes to transfer per row
|
|
|
+ Block size limit for PIF requests
|
|
|
+ Number of outstanding requests limit
|
|
|
+ Control for completion interrupt notification
|
|
|
.Descriptors have the following properties:
|
|
|
- ƒÞ Size 32B
|
|
|
- ƒÞ Aligned to 32B
|
|
|
- .mem footpring
|
|
|
- 0x101C Reserved
|
|
|
- 0x1018 Reserved
|
|
|
- 0x1014 Destination Pitch
|
|
|
- 0x1010 Source Pitch
|
|
|
- 0x100C Num of Rows
|
|
|
- 0x1008 Control
|
|
|
- 0x1004 Destination Address
|
|
|
- 0x1000 Source Address
|
|
|
+ Size 32B
|
|
|
+ Aligned to 32B
|
|
|
.Block size limit (i.e. maximum size) for DMA
|
|
|
0: Block 2 (32 bytes)
|
|
|
1: Block 4 (64 bytes)
|
|
|
2: Block 8 (128 bytes)
|
|
|
3: Block 16 (256 bytes)
|
|
|
.Transfers with row lengths of 16 B or less have the following additional requirements:
|
|
|
- ƒÞ The number of bytes per row must be 1, 2, 4, 8, or 16
|
|
|
- ƒÞ Both the source and destination addresses must have the same 16B alignment
|
|
|
- ƒÞ The source and destination addresses must be aligned to the number of bytes per row
|
|
|
- .Transfers with row lengths greater than 16B transfer each row using one or more block (or burst) transactions. Block transaction sizes are 2, 4, 8, or 16 transfers, corresponding to 32B, 64B, 128B, or 256B respectively. The same block transaction size is used for the entire transfer ¡V i.e., for all rows and all block transactions within each row. The following additional requirements apply:
|
|
|
- ƒÞ There must be a block transaction size that meets the following requirements ¡V each row transfer will use the largest block size meeting these requirements that is no larger than the maximum block size specified in the descriptor:
|
|
|
- ƒÞ The number of bytes per row is an integer multiple of the block size
|
|
|
- ƒÞ The external memory address (source or destination) is aligned to the size of the block transaction
|
|
|
- ƒÞ The local memory address (source or destination) is aligned to the smaller of the local memory width (64 B) or the block transaction length
|
|
|
- ƒÞ The row transfer must not cross a local memory DRam boundary
|
|
|
+ The number of bytes per row must be 1, 2, 4, 8, or 16
|
|
|
+ Both the source and destination addresses must have the same 16B alignment
|
|
|
+ The source and destination addresses must be aligned to the number of bytes per row
|
|
|
+ .Transfers with row lengths greater than 16B transfer each row using one or more block (or burst) transactions. Block transaction sizes are 2, 4, 8, or 16 transfers, corresponding to 32B, 64B, 128B, or 256B respectively. The same block transaction size is used for the entire transfer  i.e., for all rows and all block transactions within each row. The following additional requirements apply:
|
|
|
+ There must be a block transaction size that meets the following requirements  each row transfer will use the largest block size meeting these requirements that is no larger than the maximum block size specified in the descriptor:
|
|
|
+ The number of bytes per row is an integer multiple of the block size
|
|
|
+ The external memory address (source or destination) is aligned to the size of the block transaction
|
|
|
+ The local memory address (source or destination) is aligned to the smaller of the local memory width (64 B) or the block transaction length
|
|
|
+ The row transfer must not cross a local memory DRam boundary
|
|
|
****************************************************************************************/
|
|
|
/****************************************************************************************
|
|
|
declaration
|
|
@@ -158,15 +147,15 @@ TBOOL freeTcm(void* ptr);
|
|
|
/****************************************************************************************
|
|
|
|
|
|
****************************************************************************************/
|
|
|
-static volatile uint32_t idxDmaCnt[DMA_DIR_MAX];
|
|
|
-static int32_t idma_requests[DMA_DIR_MAX][DMA_DESCR_CNT];
|
|
|
-static uint32_t dmaAlignment = 0;
|
|
|
+static volatile uint32_t idxDmaCnt[DMA_DIR_MAX] _LOCAL_RAM0_;
|
|
|
+static int32_t idma_requests[DMA_DIR_MAX][DMA_DESCR_CNT] _LOCAL_RAM0_;
|
|
|
+static uint32_t dmaAlignment _LOCAL_RAM0_ = 0;
|
|
|
|
|
|
//static xv_dmaObject ALIGN64 dmaObj _LOCAL_DRAM0_;
|
|
|
static xvTileManager ALIGN64 g_TMObj _LOCAL_RAM0_;
|
|
|
|
|
|
|
|
|
-static idma_max_block_t idma_block_index;
|
|
|
+static idma_max_block_t idma_block_index _LOCAL_RAM0_;
|
|
|
//static xvFrame* frame;
|
|
|
//static xvTile * tile;
|
|
|
|
|
@@ -216,7 +205,7 @@ static void intrCallbackFunc1(void *pCallBackStr)
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
-static TMDMA g_TMDMA = {
|
|
|
+static TMDMA g_TMDMA _LOCAL_RAM0_ = {
|
|
|
.init = init,
|
|
|
.uninit = uninit,
|
|
|
.setup = setup,
|
|
@@ -380,7 +369,7 @@ config(xvTile * tile_obj,
|
|
|
TUINT32
|
|
|
load(xvTile * tile_obj, uint64_t pdst64, uint64_t psrc64, uint32_t srcPitchBytes, uint32_t dstPitchBytes, uint32_t numRows, uint32_t numBytesPerRow, uint32_t interruptOnCompletion)
|
|
|
{
|
|
|
- //
|
|
|
+
|
|
|
numBytesPerRow = (_ALIGN_(numBytesPerRow,dmaAlignment) > dstPitchBytes) ? dstPitchBytes : _ALIGN_(numBytesPerRow,dmaAlignment);
|
|
|
|
|
|
#ifndef _USE_IDMA_
|
|
@@ -639,22 +628,21 @@ align_check(xvTile * tile_obj,
|
|
|
|
|
|
/*
|
|
|
.Transfers with row lengths of 16 B or less have the following additional requirements:
|
|
|
- ƒÞ The number of bytes per row must be 1, 2, 4, 8, or 16
|
|
|
- ƒÞ Both the source and destination addresses must have the same 16B alignment
|
|
|
- ƒÞ The source and destination addresses must be aligned to the number of bytes per row
|
|
|
+ The number of bytes per row must be 1, 2, 4, 8, or 16
|
|
|
+ Both the source and destination addresses must have the same 16B alignment
|
|
|
+ The source and destination addresses must be aligned to the number of bytes per row
|
|
|
.Transfers with row lengths greater than 16B transfer each row using one or more block (or burst) transactions.
|
|
|
Block transaction sizes are 2, 4, 8, or 16 transfers, corresponding to 32B, 64B, 128B, or 256B respectively.
|
|
|
- The same block transaction size is used for the entire transfer ¡V i.e., for all rows and all block transactions
|
|
|
+ The same block transaction size is used for the entire transfer  i.e., for all rows and all block transactions
|
|
|
within each row. The following additional requirements apply:
|
|
|
- ƒÞ There must be a block transaction size that meets the following requirements ¡V each row transfer will use
|
|
|
+ There must be a block transaction size that meets the following requirements  each row transfer will use
|
|
|
the largest block size meeting these requirements that is no larger than the maximum block size specified
|
|
|
in the descriptor:
|
|
|
- ƒÞ The number of bytes per row is an integer multiple of the block size
|
|
|
- ƒÞ The external memory address (source or destination) is aligned to the size of the block transaction
|
|
|
- ƒÞ The local memory address (source or destination) is aligned to the smaller of the local memory width (64 B)
|
|
|
+ The number of bytes per row is an integer multiple of the block size
|
|
|
+ The external memory address (source or destination) is aligned to the size of the block transaction
|
|
|
+ The local memory address (source or destination) is aligned to the smaller of the local memory width (64 B)
|
|
|
or the block transaction length
|
|
|
- ƒÞ The row transfer must not cross a local memory DRam boundary
|
|
|
-
|
|
|
+ The row transfer must not cross a local memory DRam boundary
|
|
|
*/
|
|
|
if ( 16 >= numBytesPerRow ) {
|
|
|
for ( i=1; i<=5; i++ ) {
|