dw-mipi-csi.h 6.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
  4. *
  5. * Synopsys DesignWare MIPI CSI-2 Host controller driver
  6. *
  7. * Author: Luis Oliveira <Luis.Oliveira@synopsys.com>
  8. */
  9. #ifndef _DW_MIPI_CSI_H__
  10. #define _DW_MIPI_CSI_H__
  11. #include <linux/delay.h>
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/io.h>
  15. #include <linux/phy/phy.h>
  16. #include <linux/delay.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/of.h>
  19. #include <linux/of_graph.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/ratelimit.h>
  22. #include <linux/reset.h>
  23. #include <linux/videodev2.h>
  24. #include <linux/wait.h>
  25. #include <dw-mipi-csi-pltfrm.h>
  26. /* Advanced features */
  27. #define IPI_DT_OVERWRITE BIT(0)
  28. #define DATA_TYPE_OVERWRITE(dt) (((dt) & GENMASK(5, 0)) << 8)
  29. #define LINE_EVENT_SELECTION(n) ((n) << 16)
  30. enum line_event {
  31. EVSELAUTO = 0,
  32. EVSELPROG = 1,
  33. };
  34. #define EN_VIDEO BIT(17)
  35. #define EN_LINE_START BIT(18)
  36. #define EN_NULL BIT(19)
  37. #define EN_BLANKING BIT(20)
  38. #define EN_EMBEDDED BIT(21)
  39. #define IPI_SYNC_EVENT_MODE(n) ((n) << 24)
  40. enum sync_event {
  41. SYNCEVFSN = 0,
  42. SYNCEVFS = 1,
  43. };
  44. /* DW MIPI CSI-2 register addresses*/
  45. struct R_CSI2 {
  46. u16 VERSION;
  47. u16 N_LANES;
  48. u16 CTRL_RESETN;
  49. u16 INTERRUPT;
  50. u16 DATA_IDS_1;
  51. u16 DATA_IDS_2;
  52. u16 DATA_IDS_VC_1;
  53. u16 DATA_IDS_VC_2;
  54. u16 IPI_MODE;
  55. u16 IPI_VCID;
  56. u16 IPI_DATA_TYPE;
  57. u16 IPI_MEM_FLUSH;
  58. u16 IPI_HSA_TIME;
  59. u16 IPI_HBP_TIME;
  60. u16 IPI_HSD_TIME;
  61. u16 IPI_HLINE_TIME;
  62. u16 IPI_SOFTRSTN;
  63. u16 IPI_ADV_FEATURES;
  64. u16 IPI_VSA_LINES;
  65. u16 IPI_VBP_LINES;
  66. u16 IPI_VFP_LINES;
  67. u16 IPI_VACTIVE_LINES;
  68. u16 VC_EXTENSION;
  69. u16 INT_PHY_FATAL;
  70. u16 MASK_INT_PHY_FATAL;
  71. u16 FORCE_INT_PHY_FATAL;
  72. u16 INT_PKT_FATAL;
  73. u16 MASK_INT_PKT_FATAL;
  74. u16 FORCE_INT_PKT_FATAL;
  75. u16 INT_FRAME_FATAL;
  76. u16 MASK_INT_FRAME_FATAL;
  77. u16 FORCE_INT_FRAME_FATAL;
  78. u16 INT_PHY;
  79. u16 MASK_INT_PHY;
  80. u16 FORCE_INT_PHY;
  81. u16 INT_PKT;
  82. u16 MASK_INT_PKT;
  83. u16 FORCE_INT_PKT;
  84. u16 INT_LINE;
  85. u16 MASK_INT_LINE;
  86. u16 FORCE_INT_LINE;
  87. u16 INT_IPI;
  88. u16 MASK_INT_IPI;
  89. u16 FORCE_INT_IPI;
  90. u16 ST_BNDRY_FRAME_FATAL;
  91. u16 MSK_BNDRY_FRAME_FATAL;
  92. u16 FORCE_BNDRY_FRAME_FATAL;
  93. u16 ST_SEQ_FRAME_FATAL;
  94. u16 MSK_SEQ_FRAME_FATAL;
  95. u16 FORCE_SEQ_FRAME_FATAL;
  96. u16 ST_CRC_FRAME_FATAL;
  97. u16 MSK_CRC_FRAME_FATAL;
  98. u16 FORCE_CRC_FRAME_FATAL;
  99. u16 ST_PLD_CRC_FATAL;
  100. u16 MSK_PLD_CRC_FATAL;
  101. u16 FORCE_PLD_CRC_FATAL;
  102. u16 ST_DATA_ID;
  103. u16 MSK_DATA_ID;
  104. u16 FORCE_DATA_ID;
  105. u16 ST_ECC_CORRECT;
  106. u16 MSK_ECC_CORRECT;
  107. u16 FORCE_ECC_CORRECT;
  108. u16 IPI2_MODE;
  109. u16 IPI3_MODE;
  110. u16 IPI2_VCID;
  111. u16 IPI3_VCID;
  112. u16 IPI2_DATA_TYPE;
  113. u16 IPI3_DATA_TYPE;
  114. u16 IPI2_MEM_FLUSH;
  115. u16 IPI3_MEM_FLUSH;
  116. u16 IPI2_HSA_TIME;
  117. u16 IPI2_HBP_TIME;
  118. u16 IPI2_HSD_TIME;
  119. u16 IPI3_HSA_TIME;
  120. u16 IPI3_HBP_TIME;
  121. u16 IPI3_HSD_TIME;
  122. u16 IPI2_ADV_FEATURES;
  123. u16 IPI3_ADV_FEATURES;
  124. u16 IPI2_INT_PHY_FATAL;
  125. u16 IPI3_INT_PHY_FATAL;
  126. u16 IPI2_MASK_INT_PHY_FATAL;
  127. u16 IPI3_MASK_INT_PHY_FATAL;
  128. };
  129. /* Interrupt Masks */
  130. struct interrupt_type {
  131. u32 PHY_FATAL;
  132. u32 PKT_FATAL;
  133. u32 FRAME_FATAL;
  134. u32 PHY;
  135. u32 PKT;
  136. u32 LINE;
  137. u32 IPI;
  138. u32 BNDRY_FRAME_FATAL;
  139. u32 SEQ_FRAME_FATAL;
  140. u32 CRC_FRAME_FATAL;
  141. u32 PLD_CRC_FATAL;
  142. u32 DATA_ID;
  143. u32 ECC_CORRECTED;
  144. };
  145. /* IPI Data Types */
  146. enum data_type {
  147. CSI_2_YUV420_8 = 0x18,
  148. CSI_2_YUV420_10 = 0x19,
  149. CSI_2_YUV420_8_LEG = 0x1A,
  150. CSI_2_YUV420_8_SHIFT = 0x1C,
  151. CSI_2_YUV420_10_SHIFT = 0x1D,
  152. CSI_2_YUV422_8 = 0x1E,
  153. CSI_2_YUV422_10 = 0x1F,
  154. CSI_2_RGB444 = 0x20,
  155. CSI_2_RGB555 = 0x21,
  156. CSI_2_RGB565 = 0x22,
  157. CSI_2_RGB666 = 0x23,
  158. CSI_2_RGB888 = 0x24,
  159. CSI_2_RAW6 = 0x28,
  160. CSI_2_RAW7 = 0x29,
  161. CSI_2_RAW8 = 0x2A,
  162. CSI_2_RAW10 = 0x2B,
  163. CSI_2_RAW12 = 0x2C,
  164. CSI_2_RAW14 = 0x2D,
  165. CSI_2_RAW16 = 0x2E,
  166. CSI_2_RAW20 = 0x2F,
  167. USER_DEFINED_1 = 0x30,
  168. USER_DEFINED_2 = 0x31,
  169. USER_DEFINED_3 = 0x32,
  170. USER_DEFINED_4 = 0x33,
  171. USER_DEFINED_5 = 0x34,
  172. USER_DEFINED_6 = 0x35,
  173. USER_DEFINED_7 = 0x36,
  174. USER_DEFINED_8 = 0x37,
  175. };
  176. /* DWC MIPI CSI-2 output types */
  177. enum output {
  178. IPI_OUT = 0,
  179. IDI_OUT = 1,
  180. BOTH_OUT = 2
  181. };
  182. /* IPI color components */
  183. enum color_mode {
  184. COLOR48 = 0,
  185. COLOR16 = 1
  186. };
  187. /* IPI cut through */
  188. enum cut_through {
  189. CTINACTIVE = 0,
  190. CTACTIVE = 1
  191. };
  192. /* IPI output types */
  193. enum ipi_output {
  194. CAMERA_TIMING = 0,
  195. AUTO_TIMING = 1
  196. };
  197. /* Format template */
  198. struct mipi_fmt {
  199. u32 mbus_code;
  200. u8 depth;
  201. u32 width;
  202. u32 height;
  203. };
  204. struct mipi_dt {
  205. u32 hex;
  206. char *name;
  207. };
  208. /* CSI specific configuration */
  209. struct csi_data {
  210. u32 num_lanes;
  211. u32 dphy_freq; //MBPS
  212. u32 pclk;
  213. u32 fps;
  214. u32 bpp;
  215. u32 output;
  216. bool ipi1_en;
  217. bool ipi2_en;
  218. bool ipi3_en;
  219. u32 ipi_mode;
  220. u32 ipi_adv_features;
  221. u32 ipi_cut_through;
  222. u32 ipi_color_mode;
  223. u32 ipi_auto_flush;
  224. u32 virtual_ch;
  225. u32 ipi2_virtual_ch;
  226. u32 ipi3_virtual_ch;
  227. u32 hsa;
  228. u32 hbp;
  229. u32 hsd;
  230. u32 ipi2_hsa;
  231. u32 ipi2_hbp;
  232. u32 ipi2_hsd;
  233. u32 ipi3_hsa;
  234. u32 ipi3_hbp;
  235. u32 ipi3_hsd;
  236. u32 htotal;
  237. u32 vsa;
  238. u32 vbp;
  239. u32 vfp;
  240. u32 vactive;
  241. };
  242. /* Structure to embed device driver information */
  243. struct dw_csi {
  244. //struct v4l2_subdev sd;
  245. //struct video_device vdev;
  246. //struct v4l2_device v4l2_dev;
  247. struct device *dev;
  248. //struct media_pad pads[CSI_PADS_NUM];
  249. struct mipi_fmt *fmt;
  250. //struct v4l2_mbus_framefmt format;
  251. void __iomem *base_address;
  252. void __iomem *demo;
  253. void __iomem *csc;
  254. int ctrl_irq_number;
  255. int demosaic_irq;
  256. struct csi_data hw;
  257. struct reset_control *rst;
  258. struct phy *phy;
  259. struct dw_csih_pdata *config;
  260. struct mutex lock; /* protect resources sharing */
  261. spinlock_t slock; /* interrupt handling lock */
  262. u8 ipi_dt;
  263. u8 index;
  264. u8 hw_version_major;
  265. u16 hw_version_minor;
  266. };
  267. void dw_mipi_csi_reset(struct dw_csi *csi_dev);
  268. int dw_mipi_csi_mask_irq_power_off(struct dw_csi *csi_dev);
  269. int dw_mipi_csi_hw_stdby(struct dw_csi *csi_dev);
  270. void dw_mipi_csi_set_ipi_fmt(struct dw_csi *csi_dev);
  271. void dw_mipi_csi_start(struct dw_csi *csi_dev);
  272. void dw_mipi_csi_stop(struct dw_csi *csi_dev);
  273. int dw_mipi_csi_irq_handler(struct dw_csi *csi_dev);
  274. void dw_mipi_csi_get_version(struct dw_csi *csi_dev);
  275. int dw_mipi_csi_specific_mappings(struct dw_csi *csi_dev);
  276. void dw_mipi_csi_fill_timings(struct dw_csi *dev, uint32_t width, uint32_t height);
  277. void dw_mipi_csi_dump(struct dw_csi *csi_dev);
  278. //#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  279. int dw_csi_create_capabilities_sysfs(struct platform_device *pdev);
  280. int dw_csi_remove_capabilities_sysfs(struct platform_device *pdev);
  281. //#endif
  282. int dw_mipi_csi_s_power(struct dw_csi *dev, int on);
  283. int dw_mipi_csi_log_status(struct dw_csi *dev);
  284. static inline void dw_mipi_csi_write(struct dw_csi *dev,
  285. u32 address, u32 data)
  286. {
  287. writel(data, dev->base_address + address);
  288. }
  289. static inline u32 dw_mipi_csi_read(struct dw_csi *dev, u32 address)
  290. {
  291. return readl(dev->base_address + address);
  292. }
  293. #endif /*_DW_MIPI_CSI_H__ */