dw-mipi-csi.c 21 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
  4. *
  5. * Synopsys DesignWare MIPI CSI-2 Host controller driver
  6. * Core MIPI CSI-2 functions
  7. *
  8. * Author: Luis Oliveira <Luis.Oliveira@synopsys.com>
  9. */
  10. #include "dw-mipi-csi.h"
  11. static struct R_CSI2 reg = {
  12. .VERSION = 0x00,
  13. .N_LANES = 0x04,
  14. .CTRL_RESETN = 0x08,
  15. .INTERRUPT = 0x0C,
  16. .DATA_IDS_1 = 0x10,
  17. .DATA_IDS_2 = 0x14,
  18. .IPI_MODE = 0x80,
  19. .IPI_VCID = 0x84,
  20. .IPI_DATA_TYPE = 0x88,
  21. .IPI_MEM_FLUSH = 0x8C,
  22. .IPI_HSA_TIME = 0x90,
  23. .IPI_HBP_TIME = 0x94,
  24. .IPI_HSD_TIME = 0x98,
  25. .IPI_HLINE_TIME = 0x9C,
  26. .IPI_SOFTRSTN = 0xA0,
  27. .IPI_ADV_FEATURES = 0xAC,
  28. .IPI_VSA_LINES = 0xB0,
  29. .IPI_VBP_LINES = 0xB4,
  30. .IPI_VFP_LINES = 0xB8,
  31. .IPI_VACTIVE_LINES = 0xBC,
  32. .INT_PHY_FATAL = 0xe0,
  33. .MASK_INT_PHY_FATAL = 0xe4,
  34. .FORCE_INT_PHY_FATAL = 0xe8,
  35. .INT_PKT_FATAL = 0xf0,
  36. .MASK_INT_PKT_FATAL = 0xf4,
  37. .FORCE_INT_PKT_FATAL = 0xf8,
  38. .INT_PHY = 0x110,
  39. .MASK_INT_PHY = 0x114,
  40. .FORCE_INT_PHY = 0x118,
  41. .INT_LINE = 0x130,
  42. .MASK_INT_LINE = 0x134,
  43. .FORCE_INT_LINE = 0x138,
  44. .INT_IPI = 0x140,
  45. .MASK_INT_IPI = 0x144,
  46. .FORCE_INT_IPI = 0x148,
  47. .IPI2_MODE = 0x200,
  48. .IPI3_MODE = 0x220,
  49. .IPI2_VCID = 0x204,
  50. .IPI3_VCID = 0x224,
  51. .IPI2_DATA_TYPE = 0x208,
  52. .IPI3_DATA_TYPE = 0x228,
  53. .IPI2_MEM_FLUSH = 0x20c,
  54. .IPI3_MEM_FLUSH = 0x22c,
  55. .IPI2_HSA_TIME = 0x210,
  56. .IPI2_HBP_TIME = 0x214,
  57. .IPI2_HSD_TIME = 0x218,
  58. .IPI3_HSA_TIME = 0x230,
  59. .IPI3_HBP_TIME = 0x234,
  60. .IPI3_HSD_TIME = 0x238,
  61. .IPI2_ADV_FEATURES = 0x21c,
  62. .IPI3_ADV_FEATURES = 0x23c,
  63. .IPI2_INT_PHY_FATAL = 0x150,
  64. .IPI3_INT_PHY_FATAL = 0x160,
  65. .IPI2_MASK_INT_PHY_FATAL = 0x154,
  66. .IPI3_MASK_INT_PHY_FATAL = 0x164,
  67. };
  68. struct interrupt_type csi_int = {
  69. .PHY_FATAL = BIT(0),
  70. .PKT_FATAL = BIT(1),
  71. .PHY = BIT(16),
  72. };
  73. #define dw_print(VAR) \
  74. dev_info(csi_dev->dev, "%s: 0x%x: %X\n", "##VAR##",\
  75. VAR, dw_mipi_csi_read(csi_dev, VAR))
  76. void dw_mipi_csi_write_part(struct dw_csi *dev, u32 address, u32 data,
  77. u8 shift, u8 width)
  78. {
  79. u32 mask = (1 << width) - 1;
  80. u32 temp = dw_mipi_csi_read(dev, address);
  81. temp &= ~(mask << shift);
  82. temp |= (data & mask) << shift;
  83. dw_mipi_csi_write(dev, address, temp);
  84. }
  85. void dw_mipi_csi_reset(struct dw_csi *csi_dev)
  86. {
  87. dw_mipi_csi_write(csi_dev, reg.CTRL_RESETN, 0);
  88. usleep_range(100, 200);
  89. dw_mipi_csi_write(csi_dev, reg.CTRL_RESETN, 1);
  90. }
  91. int dw_mipi_csi_mask_irq_power_off(struct dw_csi *csi_dev)
  92. {
  93. if (csi_dev->hw_version_major == 1) {
  94. /* set only one lane (lane 0) as active (ON) */
  95. dw_mipi_csi_write(csi_dev, reg.N_LANES, 0);
  96. dw_mipi_csi_write(csi_dev, reg.MASK_INT_PHY_FATAL, 0);
  97. dw_mipi_csi_write(csi_dev, reg.IPI2_MASK_INT_PHY_FATAL, 0);
  98. dw_mipi_csi_write(csi_dev, reg.IPI3_MASK_INT_PHY_FATAL, 0);
  99. dw_mipi_csi_write(csi_dev, reg.MASK_INT_PKT_FATAL, 0);
  100. dw_mipi_csi_write(csi_dev, reg.MASK_INT_PHY, 0);
  101. dw_mipi_csi_write(csi_dev, reg.MASK_INT_LINE, 0);
  102. dw_mipi_csi_write(csi_dev, reg.MASK_INT_IPI, 0);
  103. /* only for version 1.30 */
  104. if (csi_dev->hw_version_minor == 30)
  105. dw_mipi_csi_write(csi_dev,
  106. reg.MASK_INT_FRAME_FATAL, 0);
  107. dw_mipi_csi_write(csi_dev, reg.CTRL_RESETN, 0);
  108. /* only for version 1.40 */
  109. if (csi_dev->hw_version_minor == 40) {
  110. dw_mipi_csi_write(csi_dev,
  111. reg.MSK_BNDRY_FRAME_FATAL, 0);
  112. dw_mipi_csi_write(csi_dev,
  113. reg.MSK_SEQ_FRAME_FATAL, 0);
  114. dw_mipi_csi_write(csi_dev,
  115. reg.MSK_CRC_FRAME_FATAL, 0);
  116. dw_mipi_csi_write(csi_dev, reg.MSK_PLD_CRC_FATAL, 0);
  117. dw_mipi_csi_write(csi_dev, reg.MSK_DATA_ID, 0);
  118. dw_mipi_csi_write(csi_dev, reg.MSK_ECC_CORRECT, 0);
  119. }
  120. }
  121. return 0;
  122. }
  123. int dw_mipi_csi_hw_stdby(struct dw_csi *csi_dev)
  124. {
  125. if (csi_dev->hw_version_major == 1) {
  126. /* set only one lane (lane 0) as active (ON) */
  127. dw_mipi_csi_reset(csi_dev);
  128. dw_mipi_csi_write(csi_dev, reg.N_LANES, 0);
  129. phy_init(csi_dev->phy);
  130. /* only for version 1.30 */
  131. if (csi_dev->hw_version_minor == 30)
  132. dw_mipi_csi_write(csi_dev,
  133. reg.MASK_INT_FRAME_FATAL,
  134. GENMASK(31, 0));
  135. /* common */
  136. dw_mipi_csi_write(csi_dev, reg.MASK_INT_PHY_FATAL,
  137. GENMASK(8, 0));
  138. dw_mipi_csi_write(csi_dev, reg.IPI2_MASK_INT_PHY_FATAL,
  139. GENMASK(8, 0));
  140. dw_mipi_csi_write(csi_dev, reg.IPI3_MASK_INT_PHY_FATAL,
  141. GENMASK(8, 0));
  142. dw_mipi_csi_write(csi_dev, reg.MASK_INT_PKT_FATAL,
  143. GENMASK(1, 0));
  144. dw_mipi_csi_write(csi_dev, reg.MASK_INT_PHY, GENMASK(23, 0));
  145. dw_mipi_csi_write(csi_dev, reg.MASK_INT_LINE, GENMASK(23, 0));
  146. dw_mipi_csi_write(csi_dev, reg.MASK_INT_IPI, GENMASK(5, 0));
  147. /* only for version 1.40 */
  148. if (csi_dev->hw_version_minor == 40) {
  149. dw_mipi_csi_write(csi_dev,
  150. reg.MSK_BNDRY_FRAME_FATAL,
  151. GENMASK(31, 0));
  152. dw_mipi_csi_write(csi_dev,
  153. reg.MSK_SEQ_FRAME_FATAL,
  154. GENMASK(31, 0));
  155. dw_mipi_csi_write(csi_dev,
  156. reg.MSK_CRC_FRAME_FATAL,
  157. GENMASK(31, 0));
  158. dw_mipi_csi_write(csi_dev,
  159. reg.MSK_PLD_CRC_FATAL,
  160. GENMASK(31, 0));
  161. dw_mipi_csi_write(csi_dev,
  162. reg.MSK_DATA_ID, GENMASK(31, 0));
  163. dw_mipi_csi_write(csi_dev,
  164. reg.MSK_ECC_CORRECT, GENMASK(31, 0));
  165. }
  166. }
  167. return 0;
  168. }
  169. void dw_mipi_csi_set_ipi_fmt(struct dw_csi *csi_dev)
  170. {
  171. struct device *dev = csi_dev->dev;
  172. if (csi_dev->ipi_dt) {
  173. dw_mipi_csi_write(csi_dev, reg.IPI_DATA_TYPE, csi_dev->ipi_dt);
  174. dw_mipi_csi_write(csi_dev, reg.IPI2_DATA_TYPE, csi_dev->ipi_dt);
  175. dw_mipi_csi_write(csi_dev, reg.IPI3_DATA_TYPE, csi_dev->ipi_dt);
  176. /*switch (csi_dev->ipi_dt) {
  177. case CSI_2_YUV420_8:
  178. //case CSI_2_YUV420_8_LEG:
  179. case CSI_2_YUV420_8_SHIFT:
  180. break;
  181. case CSI_2_YUV420_10:
  182. case CSI_2_YUV420_10_SHIFT:
  183. break;
  184. }*/
  185. } else {
  186. switch (csi_dev->fmt->mbus_code) {
  187. case MEDIA_BUS_FMT_RGB666_1X18:
  188. csi_dev->ipi_dt = CSI_2_RGB666;
  189. break;
  190. case MEDIA_BUS_FMT_RGB565_2X8_BE:
  191. case MEDIA_BUS_FMT_RGB565_2X8_LE:
  192. csi_dev->ipi_dt = CSI_2_RGB565;
  193. break;
  194. case MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE:
  195. case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
  196. csi_dev->ipi_dt = CSI_2_RGB555;
  197. break;
  198. case MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE:
  199. case MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE:
  200. csi_dev->ipi_dt = CSI_2_RGB444;
  201. break;
  202. break;
  203. case MEDIA_BUS_FMT_RGB888_2X12_LE:
  204. case MEDIA_BUS_FMT_RGB888_2X12_BE:
  205. csi_dev->ipi_dt = CSI_2_RGB888;
  206. break;
  207. case MEDIA_BUS_FMT_SBGGR10_1X10:
  208. case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE:
  209. csi_dev->ipi_dt = CSI_2_RAW10;
  210. break;
  211. case MEDIA_BUS_FMT_SBGGR12_1X12:
  212. csi_dev->ipi_dt = CSI_2_RAW12;
  213. break;
  214. case MEDIA_BUS_FMT_SBGGR14_1X14:
  215. csi_dev->ipi_dt = CSI_2_RAW14;
  216. break;
  217. case MEDIA_BUS_FMT_SBGGR16_1X16:
  218. csi_dev->ipi_dt = CSI_2_RAW16;
  219. break;
  220. case MEDIA_BUS_FMT_SBGGR8_1X8:
  221. csi_dev->ipi_dt = CSI_2_RAW8;
  222. break;
  223. case MEDIA_BUS_FMT_YVYU8_1X16:
  224. csi_dev->ipi_dt = CSI_2_YUV422_8;
  225. break;
  226. case MEDIA_BUS_FMT_VYUY8_1X16:
  227. csi_dev->ipi_dt = CSI_2_YUV422_8;
  228. break;
  229. case MEDIA_BUS_FMT_UYVY10_1X20:
  230. csi_dev->ipi_dt = CSI_2_YUV422_10;
  231. break;
  232. case MEDIA_BUS_FMT_YUYV8_1X16:
  233. csi_dev->ipi_dt = CSI_2_YUV420_8_LEG;
  234. break;
  235. case MEDIA_BUS_FMT_UYVY8_1X16:
  236. csi_dev->ipi_dt = CSI_2_YUV420_8;
  237. break;
  238. case MEDIA_BUS_FMT_VUY8_1X24:
  239. csi_dev->ipi_dt = CSI_2_YUV420_10;
  240. break;
  241. case MEDIA_BUS_FMT_Y8_1X8:
  242. csi_dev->ipi_dt = CSI_2_RAW8;
  243. break;
  244. case MEDIA_BUS_FMT_Y10_1X10:
  245. csi_dev->ipi_dt = CSI_2_RAW8;
  246. break;
  247. #if 0/*modify by wuyi*/
  248. case MEDIA_BUS_FMT_SBGGR6_1X8:
  249. csi_dev->ipi_dt = CSI_2_RAW6;
  250. break;
  251. case MEDIA_BUS_FMT_SBGGR7_1X8:
  252. csi_dev->ipi_dt = CSI_2_RAW7;
  253. break;
  254. #endif
  255. default:
  256. break;
  257. }
  258. dw_mipi_csi_write(csi_dev, reg.IPI_DATA_TYPE, csi_dev->ipi_dt);
  259. dw_mipi_csi_write(csi_dev, reg.IPI2_DATA_TYPE, csi_dev->ipi_dt);
  260. dw_mipi_csi_write(csi_dev, reg.IPI3_DATA_TYPE, csi_dev->ipi_dt);
  261. }
  262. dev_info(dev, "Selected IPI Data Type 0x%X\n", csi_dev->ipi_dt);
  263. }
  264. void dw_mipi_csi_fill_timings(struct dw_csi *dev, uint32_t width, uint32_t height)
  265. {
  266. dev->hw.virtual_ch = 0;
  267. dev->hw.ipi_color_mode = COLOR48;
  268. dev->hw.ipi_auto_flush = 1;
  269. dev->hw.ipi_mode = CAMERA_TIMING;
  270. dev->hw.ipi_cut_through = CTINACTIVE;
  271. dev->hw.ipi_adv_features = LINE_EVENT_SELECTION(EVSELAUTO);
  272. dev->hw.htotal = width + dev->hw.hsa +
  273. dev->hw.hbp + dev->hw.hsd;
  274. dev->hw.vactive = height;
  275. dev->hw.output = 2;
  276. dev->hw.ipi1_en = false;
  277. dev_dbg(dev->dev, "*********** timings *********\n");
  278. dev_dbg(dev->dev, "Horizontal Sync Active: %d\n", dev->hw.hsa);
  279. dev_dbg(dev->dev, "Horizontal Back Porch: %d\n", dev->hw.hbp);
  280. dev_dbg(dev->dev, "Horizontal Width: %d\n", width);
  281. dev_dbg(dev->dev, "Horizontal Total: %d\n", dev->hw.htotal);
  282. dev_dbg(dev->dev, "Vertical Sync Active: %d\n", dev->hw.vsa);
  283. dev_dbg(dev->dev, "Vertical Back Porch: %d\n", dev->hw.vbp);
  284. dev_dbg(dev->dev, "Vertical Front Porch: %d\n", dev->hw.vfp);
  285. dev_dbg(dev->dev, "Vertical Active: %d\n", dev->hw.vactive);
  286. }
  287. void dw_mipi_csi_stop(struct dw_csi *csi_dev)
  288. {
  289. /* address | data, | shift | width */
  290. if (csi_dev->hw.ipi1_en == 0) {
  291. dw_mipi_csi_write_part(csi_dev, reg.IPI_MODE, 0, 24, 1);
  292. }
  293. if (csi_dev->hw.ipi2_en == 0) {
  294. dw_mipi_csi_write_part(csi_dev, reg.IPI2_MODE, 0, 24, 1);
  295. }
  296. if (csi_dev->hw.ipi3_en == 0) {
  297. dw_mipi_csi_write_part(csi_dev, reg.IPI3_MODE, 0, 24, 1);
  298. }
  299. }
  300. void dw_mipi_csi_start(struct dw_csi *csi_dev)
  301. {
  302. struct device *dev = csi_dev->dev;
  303. dw_mipi_csi_write(csi_dev, reg.N_LANES, (csi_dev->hw.num_lanes - 1));
  304. dev_info(dev, "number of lanes: %d\n", csi_dev->hw.num_lanes);
  305. /* IPI Related Configuration */
  306. if (csi_dev->hw.output == IPI_OUT || csi_dev->hw.output == BOTH_OUT) {
  307. if (csi_dev->hw_version_major >= 1) {
  308. if (csi_dev->hw_version_minor >= 21) {
  309. dw_mipi_csi_write(csi_dev,
  310. reg.IPI_ADV_FEATURES,
  311. csi_dev->hw.ipi_adv_features);
  312. dw_mipi_csi_write(csi_dev,
  313. reg.IPI2_ADV_FEATURES,
  314. csi_dev->hw.ipi_adv_features);
  315. dw_mipi_csi_write(csi_dev,
  316. reg.IPI3_ADV_FEATURES,
  317. csi_dev->hw.ipi_adv_features);
  318. }
  319. if (csi_dev->hw_version_minor >= 30) {
  320. dw_mipi_csi_write(csi_dev,
  321. reg.IPI_SOFTRSTN, 0x1 | (0x1 << 4) | (0x1 << 8));
  322. }
  323. }
  324. /* address | data, | shift | width */
  325. if (csi_dev->hw.ipi1_en) {
  326. dw_mipi_csi_write_part(csi_dev, reg.IPI_MODE, 1, 24, 1);
  327. }
  328. if (csi_dev->hw.ipi2_en) {
  329. dw_mipi_csi_write_part(csi_dev, reg.IPI2_MODE, 1, 24, 1);
  330. }
  331. if (csi_dev->hw.ipi3_en) {
  332. dw_mipi_csi_write_part(csi_dev, reg.IPI3_MODE, 1, 24, 1);
  333. }
  334. dw_mipi_csi_write_part(csi_dev,
  335. reg.IPI_MODE,
  336. csi_dev->hw.ipi_mode,
  337. 0, 1);
  338. dw_mipi_csi_write_part(csi_dev,
  339. reg.IPI2_MODE,
  340. csi_dev->hw.ipi_mode,
  341. 0, 1);
  342. dw_mipi_csi_write_part(csi_dev,
  343. reg.IPI3_MODE,
  344. csi_dev->hw.ipi_mode,
  345. 0, 1);
  346. if (csi_dev->hw.ipi_mode == CAMERA_TIMING) {
  347. dw_mipi_csi_write(csi_dev,
  348. reg.IPI_ADV_FEATURES,
  349. LINE_EVENT_SELECTION(EVSELPROG) |
  350. EN_VIDEO);
  351. /*
  352. EN_VIDEO |
  353. EN_LINE_START |
  354. EN_NULL |
  355. EN_BLANKING |
  356. EN_EMBEDDED);
  357. */
  358. dw_mipi_csi_write(csi_dev,
  359. reg.IPI2_ADV_FEATURES,
  360. LINE_EVENT_SELECTION(EVSELPROG) |
  361. EN_VIDEO |
  362. EN_LINE_START |
  363. EN_NULL |
  364. EN_BLANKING |
  365. EN_EMBEDDED);
  366. dw_mipi_csi_write(csi_dev,
  367. reg.IPI3_ADV_FEATURES,
  368. LINE_EVENT_SELECTION(EVSELPROG) |
  369. EN_VIDEO |
  370. EN_LINE_START |
  371. EN_NULL |
  372. EN_BLANKING |
  373. EN_EMBEDDED);
  374. }
  375. dw_mipi_csi_write_part(csi_dev,
  376. reg.IPI_MODE,
  377. csi_dev->hw.ipi_color_mode,
  378. 8, 1);
  379. dw_mipi_csi_write_part(csi_dev,
  380. reg.IPI_MODE,
  381. csi_dev->hw.ipi_cut_through,
  382. 16, 1);
  383. dw_mipi_csi_write_part(csi_dev,
  384. reg.IPI2_MODE,
  385. csi_dev->hw.ipi_color_mode,
  386. 8, 1);
  387. dw_mipi_csi_write_part(csi_dev,
  388. reg.IPI2_MODE,
  389. csi_dev->hw.ipi_cut_through,
  390. 16, 1);
  391. dw_mipi_csi_write_part(csi_dev,
  392. reg.IPI3_MODE,
  393. csi_dev->hw.ipi_color_mode,
  394. 8, 1);
  395. dw_mipi_csi_write_part(csi_dev,
  396. reg.IPI3_MODE,
  397. csi_dev->hw.ipi_cut_through,
  398. 16, 1);
  399. dw_mipi_csi_write_part(csi_dev,
  400. reg.IPI_VCID,
  401. csi_dev->hw.virtual_ch,
  402. 0, 2);
  403. dw_mipi_csi_write_part(csi_dev,
  404. reg.IPI2_VCID,
  405. csi_dev->hw.ipi2_virtual_ch,
  406. 0, 2);
  407. dw_mipi_csi_write_part(csi_dev,
  408. reg.IPI3_VCID,
  409. csi_dev->hw.ipi3_virtual_ch,
  410. 0, 2);
  411. dw_mipi_csi_write_part(csi_dev,
  412. reg.IPI_MEM_FLUSH,
  413. csi_dev->hw.ipi_auto_flush,
  414. 8, 1);
  415. dw_mipi_csi_write_part(csi_dev,
  416. reg.IPI2_MEM_FLUSH,
  417. csi_dev->hw.ipi_auto_flush,
  418. 8, 1);
  419. dw_mipi_csi_write_part(csi_dev,
  420. reg.IPI3_MEM_FLUSH,
  421. csi_dev->hw.ipi_auto_flush,
  422. 8, 1);
  423. dev_vdbg(dev, "*********** config *********\n");
  424. dev_vdbg(dev, "IPI enable: %s\n",
  425. csi_dev->hw.output ? "YES" : "NO");
  426. dev_vdbg(dev, "video mode transmission type: %s timming\n",
  427. csi_dev->hw.ipi_mode ? "controller" : "camera");
  428. dev_vdbg(dev, "Color Mode: %s\n",
  429. csi_dev->hw.ipi_color_mode ? "16 bits" : "48 bits");
  430. dev_vdbg(dev, "Cut Through Mode: %s\n",
  431. csi_dev->hw.ipi_cut_through ? "enable" : "disable");
  432. dev_vdbg(dev, "IPI1 Virtual Channel: %d\n",
  433. csi_dev->hw.virtual_ch);
  434. dev_vdbg(dev, "IPI2 Virtual Channel: %d\n",
  435. csi_dev->hw.ipi2_virtual_ch);
  436. dev_vdbg(dev, "IPI3 Virtual Channel: %d\n",
  437. csi_dev->hw.ipi3_virtual_ch);
  438. dev_vdbg(dev, "Auto-flush: %d\n",
  439. csi_dev->hw.ipi_auto_flush);
  440. dw_mipi_csi_write(csi_dev, reg.IPI_SOFTRSTN, 0x1 | (0x1 << 4) | (0x1 << 8));
  441. if (csi_dev->hw.ipi_mode == AUTO_TIMING)
  442. phy_power_on(csi_dev->phy);
  443. dw_mipi_csi_write(csi_dev,
  444. reg.IPI_HSA_TIME, csi_dev->hw.hsa);
  445. dw_mipi_csi_write(csi_dev,
  446. reg.IPI_HBP_TIME, csi_dev->hw.hbp);
  447. dw_mipi_csi_write(csi_dev,
  448. reg.IPI_HSD_TIME, csi_dev->hw.hsd);
  449. dw_mipi_csi_write(csi_dev,
  450. reg.IPI2_HSA_TIME, csi_dev->hw.ipi2_hsa);
  451. dw_mipi_csi_write(csi_dev,
  452. reg.IPI2_HBP_TIME, csi_dev->hw.ipi2_hbp);
  453. dw_mipi_csi_write(csi_dev,
  454. reg.IPI2_HSD_TIME, csi_dev->hw.ipi2_hsd);
  455. dw_mipi_csi_write(csi_dev,
  456. reg.IPI3_HSA_TIME, csi_dev->hw.ipi3_hsa);
  457. dw_mipi_csi_write(csi_dev,
  458. reg.IPI3_HBP_TIME, csi_dev->hw.ipi3_hbp);
  459. dw_mipi_csi_write(csi_dev,
  460. reg.IPI3_HSD_TIME, csi_dev->hw.ipi3_hsd);
  461. dw_mipi_csi_write(csi_dev,
  462. reg.IPI_HLINE_TIME, csi_dev->hw.htotal);
  463. dw_mipi_csi_write(csi_dev,
  464. reg.IPI_VSA_LINES, csi_dev->hw.vsa);
  465. dw_mipi_csi_write(csi_dev,
  466. reg.IPI_VBP_LINES, csi_dev->hw.vbp);
  467. dw_mipi_csi_write(csi_dev,
  468. reg.IPI_VFP_LINES, csi_dev->hw.vfp);
  469. dw_mipi_csi_write(csi_dev,
  470. reg.IPI_VACTIVE_LINES, csi_dev->hw.vactive);
  471. }
  472. phy_power_on(csi_dev->phy);
  473. }
  474. int dw_mipi_csi_irq_handler(struct dw_csi *csi_dev)
  475. {
  476. struct device *dev = csi_dev->dev;
  477. u32 global_int_status, i_sts;
  478. unsigned long flags;
  479. spin_lock_irqsave(&csi_dev->slock, flags);
  480. global_int_status = dw_mipi_csi_read(csi_dev, reg.INTERRUPT);
  481. if (global_int_status & csi_int.PHY_FATAL) {
  482. i_sts = dw_mipi_csi_read(csi_dev, reg.INT_PHY_FATAL);
  483. dev_err_ratelimited(dev, "int %08X: PHY FATAL: %08X\n",
  484. reg.INT_PHY_FATAL, i_sts);
  485. i_sts = dw_mipi_csi_read(csi_dev, reg.IPI2_INT_PHY_FATAL);
  486. dev_err_ratelimited(dev, "int %08X: IPI2 PHY FATAL: %08X\n",
  487. reg.IPI2_INT_PHY_FATAL, i_sts);
  488. i_sts = dw_mipi_csi_read(csi_dev, reg.IPI3_INT_PHY_FATAL);
  489. dev_err_ratelimited(dev, "int %08X: IPI2 PHY FATAL: %08X\n",
  490. reg.IPI3_INT_PHY_FATAL, i_sts);
  491. }
  492. if (global_int_status & csi_int.PKT_FATAL) {
  493. i_sts = dw_mipi_csi_read(csi_dev, reg.INT_PKT_FATAL);
  494. dev_err_ratelimited(dev, "int %08X: PKT FATAL: %08X\n",
  495. reg.INT_PKT_FATAL, i_sts);
  496. }
  497. if (global_int_status & csi_int.FRAME_FATAL &&
  498. csi_dev->hw_version_major == 1 &&
  499. csi_dev->hw_version_minor == 30) {
  500. i_sts = dw_mipi_csi_read(csi_dev, reg.INT_FRAME_FATAL);
  501. dev_err_ratelimited(dev, "int %08X: FRAME FATAL: %08X\n",
  502. reg.INT_FRAME_FATAL, i_sts);
  503. }
  504. if (global_int_status & csi_int.PHY) {
  505. i_sts = dw_mipi_csi_read(csi_dev, reg.INT_PHY);
  506. dev_err_ratelimited(dev, "int %08X: PHY: %08X\n",
  507. reg.INT_PHY, i_sts);
  508. }
  509. if (global_int_status & csi_int.PKT &&
  510. csi_dev->hw_version_major == 1 &&
  511. csi_dev->hw_version_minor <= 30) {
  512. i_sts = dw_mipi_csi_read(csi_dev, reg.INT_PKT);
  513. dev_err_ratelimited(dev, "int %08X: PKT: %08X\n",
  514. reg.INT_PKT, i_sts);
  515. }
  516. if (global_int_status & csi_int.LINE) {
  517. i_sts = dw_mipi_csi_read(csi_dev, reg.INT_LINE);
  518. dev_err_ratelimited(dev, "int %08X: LINE: %08X\n",
  519. reg.INT_LINE, i_sts);
  520. }
  521. if (global_int_status & csi_int.IPI) {
  522. i_sts = dw_mipi_csi_read(csi_dev, reg.INT_IPI);
  523. dev_err_ratelimited(dev, "int %08X: IPI: %08X\n",
  524. reg.INT_IPI, i_sts);
  525. }
  526. if (global_int_status & csi_int.BNDRY_FRAME_FATAL) {
  527. i_sts = dw_mipi_csi_read(csi_dev, reg.ST_BNDRY_FRAME_FATAL);
  528. dev_err_ratelimited(dev,
  529. "int %08X: ST_BNDRY_FRAME_FATAL: %08X\n",
  530. reg.ST_BNDRY_FRAME_FATAL, i_sts);
  531. }
  532. if (global_int_status & csi_int.SEQ_FRAME_FATAL) {
  533. i_sts = dw_mipi_csi_read(csi_dev, reg.ST_SEQ_FRAME_FATAL);
  534. dev_err_ratelimited(dev,
  535. "int %08X: ST_SEQ_FRAME_FATAL: %08X\n",
  536. reg.ST_SEQ_FRAME_FATAL, i_sts);
  537. }
  538. if (global_int_status & csi_int.CRC_FRAME_FATAL) {
  539. i_sts = dw_mipi_csi_read(csi_dev, reg.ST_CRC_FRAME_FATAL);
  540. dev_err_ratelimited(dev,
  541. "int %08X: ST_CRC_FRAME_FATAL: %08X\n",
  542. reg.ST_CRC_FRAME_FATAL, i_sts);
  543. }
  544. if (global_int_status & csi_int.PLD_CRC_FATAL) {
  545. i_sts = dw_mipi_csi_read(csi_dev, reg.ST_PLD_CRC_FATAL);
  546. dev_err_ratelimited(dev,
  547. "int %08X: ST_PLD_CRC_FATAL: %08X\n",
  548. reg.ST_PLD_CRC_FATAL, i_sts);
  549. }
  550. if (global_int_status & csi_int.DATA_ID) {
  551. i_sts = dw_mipi_csi_read(csi_dev, reg.ST_DATA_ID);
  552. dev_err_ratelimited(dev, "int %08X: ST_DATA_ID: %08X\n",
  553. reg.ST_DATA_ID, i_sts);
  554. }
  555. if (global_int_status & csi_int.ECC_CORRECTED) {
  556. i_sts = dw_mipi_csi_read(csi_dev, reg.ST_ECC_CORRECT);
  557. dev_err_ratelimited(dev, "int %08X: ST_ECC_CORRECT: %08X\n",
  558. reg.ST_ECC_CORRECT, i_sts);
  559. }
  560. spin_unlock_irqrestore(&csi_dev->slock, flags);
  561. return 1;
  562. }
  563. void dw_mipi_csi_get_version(struct dw_csi *csi_dev)
  564. {
  565. u32 hw_version;
  566. hw_version = dw_mipi_csi_read(csi_dev, reg.VERSION);
  567. csi_dev->hw_version_major = (u8)((hw_version >> 24) - '0');
  568. csi_dev->hw_version_minor = (u8)((hw_version >> 16) - '0');
  569. csi_dev->hw_version_minor = csi_dev->hw_version_minor * 10;
  570. csi_dev->hw_version_minor += (u8)((hw_version >> 8) - '0');
  571. }
  572. int dw_mipi_csi_specific_mappings(struct dw_csi *csi_dev)
  573. {
  574. struct device *dev = csi_dev->dev;
  575. if (csi_dev->hw_version_major == 1) {
  576. if (csi_dev->hw_version_minor == 30) {
  577. /*
  578. * Hardware registers that were
  579. * exclusive to version < 1.40
  580. */
  581. reg.INT_FRAME_FATAL = 0x100;
  582. reg.MASK_INT_FRAME_FATAL = 0x104;
  583. reg.FORCE_INT_FRAME_FATAL = 0x108;
  584. reg.INT_PKT = 0x120;
  585. reg.MASK_INT_PKT = 0x124;
  586. reg.FORCE_INT_PKT = 0x128;
  587. /* interrupt source present until this release */
  588. csi_int.PKT = BIT(17);
  589. csi_int.LINE = BIT(18);
  590. csi_int.IPI = BIT(19);
  591. csi_int.FRAME_FATAL = BIT(2);
  592. } else if (csi_dev->hw_version_minor == 40) {
  593. /*
  594. * HW registers that were added
  595. * to version 1.40
  596. */
  597. reg.ST_BNDRY_FRAME_FATAL = 0x280;
  598. reg.MSK_BNDRY_FRAME_FATAL = 0x284;
  599. reg.FORCE_BNDRY_FRAME_FATAL = 0x288;
  600. reg.ST_SEQ_FRAME_FATAL = 0x290;
  601. reg.MSK_SEQ_FRAME_FATAL = 0x294;
  602. reg.FORCE_SEQ_FRAME_FATAL = 0x298;
  603. reg.ST_CRC_FRAME_FATAL = 0x2a0;
  604. reg.MSK_CRC_FRAME_FATAL = 0x2a4;
  605. reg.FORCE_CRC_FRAME_FATAL = 0x2a8;
  606. reg.ST_PLD_CRC_FATAL = 0x2b0;
  607. reg.MSK_PLD_CRC_FATAL = 0x2b4;
  608. reg.FORCE_PLD_CRC_FATAL = 0x2b8;
  609. reg.ST_DATA_ID = 0x2c0;
  610. reg.MSK_DATA_ID = 0x2c4;
  611. reg.FORCE_DATA_ID = 0x2c8;
  612. reg.ST_ECC_CORRECT = 0x2d0;
  613. reg.MSK_ECC_CORRECT = 0x2d4;
  614. reg.FORCE_ECC_CORRECT = 0x2d8;
  615. reg.DATA_IDS_VC_1 = 0x0;
  616. reg.DATA_IDS_VC_2 = 0x0;
  617. reg.VC_EXTENSION = 0x0;
  618. /* interrupts map were changed */
  619. csi_int.LINE = BIT(17);
  620. csi_int.IPI = BIT(18);
  621. csi_int.BNDRY_FRAME_FATAL = BIT(2);
  622. csi_int.SEQ_FRAME_FATAL = BIT(3);
  623. csi_int.CRC_FRAME_FATAL = BIT(4);
  624. csi_int.PLD_CRC_FATAL = BIT(5);
  625. csi_int.DATA_ID = BIT(6);
  626. csi_int.ECC_CORRECTED = BIT(7);
  627. } else {
  628. dev_info(dev, "Version minor not supported.");
  629. }
  630. } else {
  631. dev_info(dev, "Version major not supported.");
  632. }
  633. return 0;
  634. }
  635. void dw_mipi_csi_dump(struct dw_csi *csi_dev)
  636. {
  637. dw_print(reg.VERSION);
  638. dw_print(reg.N_LANES);
  639. dw_print(reg.CTRL_RESETN);
  640. dw_print(reg.INTERRUPT);
  641. dw_print(reg.DATA_IDS_1);
  642. dw_print(reg.DATA_IDS_2);
  643. dw_print(reg.IPI_MODE);
  644. dw_print(reg.IPI_VCID);
  645. dw_print(reg.IPI_DATA_TYPE);
  646. dw_print(reg.IPI_MEM_FLUSH);
  647. dw_print(reg.IPI_HSA_TIME);
  648. dw_print(reg.IPI_HBP_TIME);
  649. dw_print(reg.IPI_HSD_TIME);
  650. dw_print(reg.IPI_HLINE_TIME);
  651. dw_print(reg.IPI_SOFTRSTN);
  652. dw_print(reg.IPI_ADV_FEATURES);
  653. dw_print(reg.IPI_VSA_LINES);
  654. dw_print(reg.IPI_VBP_LINES);
  655. dw_print(reg.IPI_VFP_LINES);
  656. dw_print(reg.IPI_VACTIVE_LINES);
  657. dw_print(reg.IPI_DATA_TYPE);
  658. dw_print(reg.VERSION);
  659. dw_print(reg.IPI_ADV_FEATURES);
  660. }