dw-dphy-rx.h 5.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
  4. *
  5. * Synopsys DesignWare MIPI D-PHY controller driver
  6. *
  7. * Author: Luis Oliveira <luis.oliveira@synopsys.com>
  8. */
  9. #ifndef __PHY_SNPS_DPHY_RX_H__
  10. #define __PHY_SNPS_DPHY_RX_H__
  11. #include <linux/debugfs.h>
  12. #include <linux/delay.h>
  13. #include <linux/gpio.h>
  14. #include <linux/io.h>
  15. #include <linux/kernel.h>
  16. #include <linux/module.h>
  17. #include <linux/of.h>
  18. #include <linux/of_address.h>
  19. #include <linux/of_gpio.h>
  20. #include <linux/phy/phy.h>
  21. #include <linux/phy/phy-mipi-dphy.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/spinlock.h>
  24. /* DPHY interface register bank*/
  25. #define R_CSI2_DPHY_SHUTDOWNZ 0x0
  26. #define R_CSI2_DPHY_RSTZ 0x4
  27. #define R_CSI2_DPHY_RX 0x8
  28. #define R_CSI2_DPHY_STOPSTATE 0xC
  29. #define R_CSI2_DPHY_TST_CTRL0 0x10
  30. #define R_CSI2_DPHY_TST_CTRL1 0x14
  31. #define R_CSI2_DPHY2_TST_CTRL0 0x18
  32. #define R_CSI2_DPHY2_TST_CTRL1 0x1C
  33. enum dphy_id_mask {
  34. DPHY_ID_LANE_SUPPORT = 0,
  35. DPHY_ID_IF = 4,
  36. DPHY_ID_GEN = 8,
  37. };
  38. enum dphy_gen_values {
  39. GEN1,
  40. GEN2,
  41. GEN3,
  42. };
  43. enum dphy_interface_length {
  44. BIT8 = 8,
  45. BIT12 = 12,
  46. };
  47. enum tst_ctrl0 {
  48. PHY_TESTCLR,
  49. PHY_TESTCLK,
  50. };
  51. enum tst_ctrl1 {
  52. PHY_TESTDIN = 0,
  53. PHY_TESTDOUT = 8,
  54. PHY_TESTEN = 16,
  55. };
  56. enum lanes_config_values {
  57. CTRL_4_LANES,
  58. CTRL_8_LANES,
  59. };
  60. enum dphy_tc {
  61. CFGCLKFREQRANGE_TX = 0x02,
  62. CFGCLKFREQRANGE_RX = 0x05,
  63. BYPASS = 0x20,
  64. IO_DS = 0x30,
  65. };
  66. enum dphy_8bit_interface_addr {
  67. BANDGAP_CTRL = 0x24,
  68. HS_RX_CTRL_LANE0 = 0x42,
  69. HSFREQRANGE_8BIT = 0x44,
  70. OSC_FREQ_TARGET_RX0_LSB = 0x4e,
  71. OSC_FREQ_TARGET_RX0_MSB = 0x4f,
  72. HS_RX_CTRL_LANE1 = 0x52,
  73. OSC_FREQ_TARGET_RX1_LSB = 0x5e,
  74. OSC_FREQ_TARGET_RX1_MSB = 0x5f,
  75. RX_SKEW_CAL = 0x7e,
  76. HS_RX_CTRL_LANE2 = 0x82,
  77. OSC_FREQ_TARGET_RX2_LSB = 0x8e,
  78. OSC_FREQ_TARGET_RX2_MSB = 0x8f,
  79. HS_RX_CTRL_LANE3 = 0x92,
  80. OSC_FREQ_TARGET_RX3_LSB = 0x9e,
  81. OSC_FREQ_TARGET_RX3_MSB = 0x9f,
  82. };
  83. enum dphy_12bit_interface_addr {
  84. RX_SYS_0 = 0x01,
  85. RX_SYS_1 = 0x02,
  86. RX_SYS_3 = 0x05,
  87. RX_SYS_7 = 0x08,
  88. RX_SYS_9 = 0x0a,
  89. RX_RX_STARTUP_OVR_0 = 0xe0,
  90. RX_RX_STARTUP_OVR_1 = 0xe1,
  91. RX_RX_STARTUP_OVR_2 = 0xe2,
  92. RX_RX_STARTUP_OVR_3 = 0xe3,
  93. RX_RX_STARTUP_OVR_4 = 0xe4,
  94. RX_RX_STARTUP_OVR_5 = 0xe5,
  95. RX_RX_STARTUP_OVR_17 = 0xf1,
  96. RX_RX_DUAL_PHY_0 = 0x133,
  97. RX_RX_CB_1 = 0x1ab,
  98. RX_RX_CB_2 = 0x1ac,
  99. RX_RX_CLKLANE_LANE_6 = 0x307,
  100. };
  101. //#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  102. /* Testchip interface register bank */
  103. #define IDLYCFG 0x00
  104. #define IDLYSEL 0x04
  105. #define IDLYCNTINVAL 0x08
  106. #define IDLYCNTOUTVAL 0x0c
  107. #define DPHY1REGRSTN 0x10
  108. #define DPHYZCALSTAT 0x14
  109. #define DPHYZCALCTRL 0x18
  110. #define DPHYLANE0STAT 0x1c
  111. #define DPHYLANE1STAT 0x20
  112. #define DPHYLANE2STAT 0x24
  113. #define DPHYLANE3STAT 0x28
  114. #define DPHYCLKSTAT 0x2c
  115. #define DPHYZCLKCTRL 0x30
  116. #define TCGENPURPOSOUT 0x34
  117. #define TCGENPURPOSIN 0x38
  118. #define DPHYGENERICOUT 0x3c
  119. #define DPHYGENERICIN 0x40
  120. #define DPHYGLUEIFTESTER 0x180
  121. #define DPHYID 0x100
  122. #define DPHY_DEFAULT_FREQ 300000
  123. enum glueiftester {
  124. RESET = 0,
  125. TX_PHY = 0x100 | (0x1 << 4),
  126. RX_PHY = 0x100 | (0x2 << 4),
  127. GLUELOGIC = 0x100 | (0x4 << 4),
  128. };
  129. //#endif
  130. /**
  131. * struct phy specifies associated phy component
  132. * struct cfg to pass mipi dphy specific configurations
  133. * @lanes_config lanes configuration
  134. * @dphy_freq operating frequency of the d-phy (mbps)
  135. * @phy_type dphy can be of two types, passed here
  136. * @dphy_gen dphy can be of three generations, passed here
  137. * @dphy_te_len bus width
  138. * @max_lanes maximum number of lanes
  139. * @lp_time time in low-power
  140. * @base_address memmory address of dphy test interface
  141. * @dphy1_if_addr gluelogic dphy 1 memmory address of interface
  142. * @dphy2_if_addr gluelogic dphy 2 memmory address of interface
  143. * @config_8l eight lanes configuration
  144. */
  145. struct dw_dphy_rx {
  146. struct phy *phy;
  147. struct phy_configure_opts_mipi_dphy *cfg;
  148. u32 lanes_config;
  149. u32 dphy_freq; //MBPS
  150. u32 phy_type;
  151. u32 dphy_gen;
  152. u32 dphy_te_len;
  153. u32 max_lanes;
  154. u32 lp_time;
  155. u32 dphyglueiftester;
  156. u32 sysreg_mipi_csi_ctrl;
  157. void __iomem *base_address;
  158. //#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  159. void __iomem *dphy1_if_addr;
  160. void __iomem *dphy2_if_addr;
  161. u8 config_8l;
  162. u8 (*get_config_8l)(struct device *dev, struct dw_dphy_rx *dphy);
  163. //#endif
  164. u8 (*phy_register)(struct device *dev);
  165. void (*phy_unregister)(struct device *dev);
  166. };
  167. int dw_dphy_init(struct phy *phy);
  168. int dw_dphy_reset(struct phy *phy);
  169. int dw_dphy_power_off(struct phy *phy);
  170. int dw_dphy_power_on(struct phy *phy);
  171. u8 dw_dphy_setup_config(struct dw_dphy_rx *dphy);
  172. void dw_dphy_write(struct dw_dphy_rx *dphy, u32 address, u32 data);
  173. u32 dw_dphy_read(struct dw_dphy_rx *dphy, u32 address);
  174. int dw_dphy_te_read(struct dw_dphy_rx *dphy, u32 addr);
  175. //#if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  176. u32 dw_dphy_if_read(struct dw_dphy_rx *dphy, u32 address);
  177. int dw_dphy_if_get_idelay(struct dw_dphy_rx *dphy);
  178. int dw_dphy_if_set_idelay_lane(struct dw_dphy_rx *dphy, u8 dly, u8 lane);
  179. int dw_dphy_create_capabilities_sysfs(struct platform_device *pdev);
  180. int dw_dphy_remove_capabilities_sysfs(struct platform_device *pdev);
  181. static inline
  182. u32 dw_dphy_if_read_msk(struct dw_dphy_rx *dphy,
  183. u32 address, u8 shift, u8 width)
  184. {
  185. return (dw_dphy_if_read(dphy, address) >> shift) & ((1 << width) - 1);
  186. }
  187. //#endif /*IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)*/
  188. static inline struct phy *dw_dphy_xlate(struct device *dev,
  189. struct of_phandle_args *args)
  190. {
  191. struct dw_dphy_rx *dphy = dev_get_drvdata(dev);
  192. return dphy->phy;
  193. }
  194. static inline
  195. u32 dw_dphy_read_msk(struct dw_dphy_rx *dev, u32 address, u8 shift, u8 width)
  196. {
  197. return (dw_dphy_read(dev, address) >> shift) & ((1 << width) - 1);
  198. }
  199. #endif /*__PHY_SNPS_DPHY_RX_H__*/