dw-dphy-rx.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
  4. *
  5. * Synopsys DesignWare MIPI D-PHY controller driver
  6. * Core functions
  7. *
  8. * Author: Luis Oliveira <luis.oliveira@synopsys.com>
  9. */
  10. #include "dw-dphy-rx.h"
  11. #include "bm_csi_dphy.h"
  12. #include "bm_printk.h"
  13. #include <linux/io.h>
  14. struct range_dphy_gen2 {
  15. u32 freq;
  16. u8 hsfregrange;
  17. };
  18. struct range_dphy_gen2 range_gen2[] = {
  19. { 80, 0x00 }, { 90, 0x10 }, { 100, 0x20 }, { 110, 0x30 },
  20. { 120, 0x01 }, { 130, 0x11 }, { 140, 0x21 }, { 150, 0x31 },
  21. { 160, 0x02 }, { 170, 0x12 }, { 180, 0x22 }, { 190, 0x32 },
  22. { 205, 0x03 }, { 220, 0x13 }, { 235, 0x23 }, { 250, 0x33 },
  23. { 275, 0x04 }, { 300, 0x14 }, { 325, 0x05 }, { 350, 0x15 },
  24. { 400, 0x25 }, { 450, 0x06 }, { 500, 0x16 }, { 550, 0x07 },
  25. { 600, 0x17 }, { 650, 0x08 }, { 700, 0x18 }, { 750, 0x09 },
  26. { 800, 0x19 }, { 850, 0x29 }, { 900, 0x39 }, { 950, 0x0A },
  27. { 1000, 0x1A }, { 1050, 0x2A }, { 1100, 0x3A }, { 1150, 0x0B },
  28. { 1200, 0x1B }, { 1250, 0x2B }, { 1300, 0x3B }, { 1350, 0x0C },
  29. { 1400, 0x1C }, { 1450, 0x2C }, { 1500, 0x3C }, { 1550, 0x0D },
  30. { 1600, 0x1D }, { 1650, 0x2D }, { 1700, 0x0E }, { 1750, 0x1E },
  31. { 1800, 0x2E }, { 1850, 0x3E }, { 1900, 0x0F }, { 1950, 0x1F },
  32. { 2000, 0x2F },
  33. };
  34. struct range_dphy_gen3 {
  35. u32 freq;
  36. u8 hsfregrange;
  37. u32 osc_freq_target;
  38. };
  39. #if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  40. struct range_dphy_gen3 range_gen3[] = {
  41. { 80, 0x00, 0x1B6 }, { 90, 0x10, 0x1B6 }, { 100, 0x20, 0x1B6 },
  42. { 110, 0x30, 0x1B6 }, { 120, 0x01, 0x1B6 }, { 130, 0x11, 0x1B6 },
  43. { 140, 0x21, 0x1B6 }, { 150, 0x31, 0x1B6 }, { 160, 0x02, 0x1B6 },
  44. { 170, 0x12, 0x1B6 }, { 180, 0x22, 0x1B6 }, { 190, 0x32, 0x1B6 },
  45. { 205, 0x03, 0x1B6 }, { 220, 0x13, 0x1B6 }, { 235, 0x23, 0x1B6 },
  46. { 250, 0x33, 0x1B6 }, { 275, 0x04, 0x1B6 }, { 300, 0x14, 0x1B6 },
  47. { 325, 0x25, 0x1B6 }, { 350, 0x35, 0x1B6 }, { 400, 0x05, 0x1B6 },
  48. { 450, 0x16, 0x1B6 }, { 500, 0x26, 0x1B6 }, { 550, 0x37, 0x1B6 },
  49. { 600, 0x07, 0x1B6 }, { 650, 0x18, 0x1B6 }, { 700, 0x28, 0x1B6 },
  50. { 750, 0x39, 0x1B6 }, { 800, 0x09, 0x1B6 }, { 850, 0x19, 0x1B6 },
  51. { 900, 0x29, 0x1B6 }, { 950, 0x3A, 0x1B6 }, { 1000, 0x0A, 0x1B6 },
  52. { 1050, 0x1A, 0x1B6 }, { 1100, 0x2A, 0x1B6 }, { 1150, 0x3B, 0x1B6 },
  53. { 1200, 0x0B, 0x1B6 }, { 1250, 0x1B, 0x1B6 }, { 1300, 0x2B, 0x1B6 },
  54. { 1350, 0x3C, 0x1B6 }, { 1400, 0x0C, 0x1B6 }, { 1450, 0x1C, 0x1B6 },
  55. { 1500, 0x2C, 0x1B6 }, { 1550, 0x3D, 0x10F }, { 1600, 0x0D, 0x118 },
  56. { 1650, 0x1D, 0x121 }, { 1700, 0x2E, 0x12A }, { 1750, 0x3E, 0x132 },
  57. { 1800, 0x0E, 0x13B }, { 1850, 0x1E, 0x144 }, { 1900, 0x2F, 0x14D },
  58. { 1950, 0x3F, 0x155 }, { 2000, 0x0F, 0x15E }, { 2050, 0x40, 0x167 },
  59. { 2100, 0x41, 0x170 }, { 2150, 0x42, 0x178 }, { 2200, 0x43, 0x181 },
  60. { 2250, 0x44, 0x18A }, { 2300, 0x45, 0x193 }, { 2350, 0x46, 0x19B },
  61. { 2400, 0x47, 0x1A4 }, { 2450, 0x48, 0x1AD }, { 2500, 0x49, 0x1B6 }
  62. };
  63. #else
  64. //for asic
  65. struct range_dphy_gen3 range_gen3[] = { //TODO 根据手册更新osc_freq_target的值。
  66. { 80, 0x00, 460 }, { 90, 0x10, 460 }, { 100, 0x20, 460 },
  67. { 110, 0x30, 460 }, { 120, 0x01, 460 }, { 130, 0x11, 460 },
  68. { 140, 0x21, 460 }, { 150, 0x31, 460 }, { 160, 0x02, 460 },
  69. { 170, 0x12, 460 }, { 180, 0x22, 460 }, { 190, 0x32, 460 },
  70. { 205, 0x03, 460 }, { 220, 0x13, 460 }, { 235, 0x23, 460 },
  71. { 250, 0x33, 460 }, { 275, 0x04, 460 }, { 300, 0x14, 460 },
  72. { 325, 0x25, 460 }, { 350, 0x35, 460 }, { 400, 0x05, 460 },
  73. { 450, 0x16, 460 }, { 500, 0x26, 460 }, { 550, 0x37, 460 },
  74. { 600, 0x07, 460 }, { 650, 0x18, 460 }, { 700, 0x28, 460 },
  75. { 750, 0x39, 460 }, { 800, 0x09, 460 }, { 850, 0x19, 460 },
  76. { 900, 0x29, 460 }, { 950, 0x3A, 460 }, { 1000, 0x0A, 460 },
  77. { 1050, 0x1A, 460 }, { 1100, 0x2A, 460 }, { 1150, 0x3B, 460 },
  78. { 1200, 0x0B, 460 }, { 1250, 0x1B, 460 }, { 1300, 0x2B, 460 },
  79. { 1350, 0x3C, 460 }, { 1400, 0x0C, 460 }, { 1450, 0x1C, 460 },
  80. { 1500, 0x2C, 460 }, { 1550, 0x3D, 285 }, { 1600, 0x0D, 295 },
  81. { 1650, 0x1D, 304 }, { 1700, 0x2E, 313 }, { 1750, 0x3E, 322 },
  82. { 1800, 0x0E, 331 }, { 1850, 0x1E, 341 }, { 1900, 0x2F, 350 },
  83. { 1950, 0x3F, 359 }, { 2000, 0x0F, 368 }, { 2050, 0x40, 377 },
  84. { 2100, 0x41, 387 }, { 2150, 0x42, 396 }, { 2200, 0x43, 405 },
  85. { 2250, 0x44, 414 }, { 2300, 0x45, 423 }, { 2350, 0x46, 432 },
  86. { 2400, 0x47, 442 }, { 2450, 0x48, 451 }, { 2500, 0x49, 460 }
  87. };
  88. #endif
  89. u8 dw_dphy_setup_config(struct dw_dphy_rx *dphy)
  90. {
  91. #if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  92. #if 0
  93. int ret;
  94. if (dphy->max_lanes == CTRL_4_LANES) {
  95. dev_vdbg(&dphy->phy->dev, "CONFIG 4L\n");
  96. return CTRL_4_LANES;
  97. }
  98. if (IS_ENABLED(CONFIG_OF)) {
  99. ret = gpio_request(dphy->config_8l, "config");
  100. if (ret < 0) {
  101. dev_vdbg(&dphy->phy->dev,
  102. "could not acquire config (err=%d)\n", ret);
  103. return ret;
  104. }
  105. ret = gpio_get_value(dphy->config_8l);
  106. gpio_free(dphy->config_8l);
  107. } else {
  108. ret = dphy->config_8l;
  109. }
  110. dev_vdbg(&dphy->phy->dev,
  111. "Booting in [%s] mode\n",
  112. ret == CTRL_8_LANES ? "8L" : "4+4L");
  113. return ret;
  114. #endif
  115. #endif /* CONFIG_DWC_MIPI_TC_DPHY_GEN3 */
  116. return CTRL_4_LANES;
  117. }
  118. extern int k_bm_visys_write_reg(uint32_t offset, uint32_t value);
  119. extern int k_bm_visys_read_reg(uint32_t offset, uint32_t *value);
  120. void dw_dphy_if_write(struct dw_dphy_rx *dphy, u32 address, u32 data)
  121. {
  122. //writel(data, dphy->dphy1_if_addr + address);
  123. k_bm_visys_write_reg(address, data);
  124. }
  125. u32 dw_dphy_if_read(struct dw_dphy_rx *dphy, u32 address)
  126. {
  127. u32 if1 = 0;
  128. //if1 = readl(dphy->dphy1_if_addr + address);
  129. k_bm_visys_read_reg(address, &if1);
  130. return if1;
  131. }
  132. void dw_dphy_write(struct dw_dphy_rx *dphy, u32 address, u32 data)
  133. {
  134. writel(data, dphy->base_address + address);
  135. if (dphy->lanes_config == CTRL_4_LANES)
  136. return;
  137. return;
  138. if (address == R_CSI2_DPHY_TST_CTRL0)
  139. iowrite32(data, dphy->base_address + R_CSI2_DPHY2_TST_CTRL0);
  140. else if (address == R_CSI2_DPHY_TST_CTRL1)
  141. iowrite32(data, dphy->base_address + R_CSI2_DPHY2_TST_CTRL1);
  142. }
  143. u32 dw_dphy_read(struct dw_dphy_rx *dphy, u32 address)
  144. {
  145. int dphy1 = 0, dphy2 = 0;
  146. dphy1 = readl(dphy->base_address + address);
  147. if (dphy->lanes_config == CTRL_4_LANES)
  148. goto end;
  149. goto end;
  150. if (address == R_CSI2_DPHY_TST_CTRL0)
  151. dphy2 = ioread32(dphy->base_address + R_CSI2_DPHY2_TST_CTRL0);
  152. else if (address == R_CSI2_DPHY_TST_CTRL1)
  153. dphy2 = ioread32(dphy->base_address + R_CSI2_DPHY2_TST_CTRL1);
  154. else
  155. return -ENODEV;
  156. end:
  157. return dphy1;
  158. }
  159. void dw_dphy_write_msk(struct dw_dphy_rx *dev, u32 address, u32 data, u8 shift,
  160. u8 width)
  161. {
  162. u32 temp = dw_dphy_read(dev, address);
  163. u32 mask = (1 << width) - 1;
  164. temp &= ~(mask << shift);
  165. temp |= (data & mask) << shift;
  166. dw_dphy_write(dev, address, temp);
  167. }
  168. static void dw_dphy_te_12b_write(struct dw_dphy_rx *dphy, u16 addr, u8 data)
  169. {
  170. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1);
  171. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1);
  172. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 1, PHY_TESTEN, 1);
  173. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1);
  174. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0x00, PHY_TESTDIN, 8);
  175. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1);
  176. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1);
  177. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, (u8)(addr >> 8),
  178. PHY_TESTDIN, 8);
  179. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1);
  180. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1);
  181. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 1, PHY_TESTEN, 1);
  182. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1);
  183. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, (u8)addr, PHY_TESTDIN,
  184. 8);
  185. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1);
  186. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1);
  187. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, (u8)data, PHY_TESTDIN,
  188. 8);
  189. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1);
  190. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1);
  191. }
  192. static void dw_dphy_te_8b_write(struct dw_dphy_rx *dphy, u8 addr, u8 data)
  193. {
  194. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1);
  195. dw_dphy_write(dphy, R_CSI2_DPHY_TST_CTRL1, addr);
  196. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 1, PHY_TESTEN, 1);
  197. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1);
  198. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1);
  199. dw_dphy_write(dphy, R_CSI2_DPHY_TST_CTRL1, data);
  200. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1);
  201. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1);
  202. }
  203. static void dw_dphy_te_write(struct dw_dphy_rx *dphy, u16 addr, u8 data)
  204. {
  205. dphy->dphy_te_len = BIT12;
  206. if (dphy->dphy_te_len == BIT12)
  207. dw_dphy_te_12b_write(dphy, addr, data);
  208. else
  209. dw_dphy_te_8b_write(dphy, addr, data);
  210. }
  211. static int dw_dphy_te_12b_read(struct dw_dphy_rx *dphy, u32 addr)
  212. {
  213. u8 ret;
  214. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1);
  215. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1);
  216. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 1, PHY_TESTEN, 1);
  217. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1);
  218. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0x00, PHY_TESTDIN, 8);
  219. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1);
  220. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1);
  221. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, (u8)(addr >> 8),
  222. PHY_TESTDIN, 8);
  223. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1);
  224. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1);
  225. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 1, PHY_TESTEN, 1);
  226. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1);
  227. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, (u8)addr, PHY_TESTDIN,
  228. 8);
  229. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1);
  230. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0x00, 0, PHY_TESTDIN);
  231. ret = dw_dphy_read_msk(dphy, R_CSI2_DPHY_TST_CTRL1, PHY_TESTDOUT, 8);
  232. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1);
  233. return ret;
  234. }
  235. static int dw_dphy_te_8b_read(struct dw_dphy_rx *dphy, u32 addr)
  236. {
  237. u8 ret;
  238. dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 0);
  239. dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 0);
  240. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 1, PHY_TESTEN, 1);
  241. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1);
  242. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, addr, PHY_TESTDIN, 8);
  243. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1);
  244. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1);
  245. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTDIN, 8);
  246. ret = dw_dphy_read_msk(dphy, R_CSI2_DPHY_TST_CTRL1, PHY_TESTDOUT, 8);
  247. dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 1);
  248. dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 1);
  249. return ret;
  250. }
  251. int dw_dphy_te_read(struct dw_dphy_rx *dphy, u32 addr)
  252. {
  253. int ret;
  254. if (dphy->dphy_te_len == BIT12)
  255. ret = dw_dphy_te_12b_read(dphy, addr);
  256. else
  257. ret = dw_dphy_te_12b_read(dphy, addr);
  258. //ret = dw_dphy_te_8b_read(dphy, addr);
  259. return ret;
  260. }
  261. #if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  262. static void dw_dphy_if_init(struct dw_dphy_rx *dphy)
  263. {
  264. bm_info("enter %s\n", __func__);
  265. //dw_dphy_if_write(dphy, dphy->dphy1_if_addr, RESET);
  266. //dw_dphy_if_write(dphy, dphy->dphy1_if_addr, TX_PHY);
  267. //dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLR, 1);
  268. //dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLR, 1);
  269. //dw_dphy_if_write(dphy, DPHYZCALCTRL, 0);
  270. //dw_dphy_if_write(dphy, DPHYZCALCTRL, 1);
  271. dw_dphy_if_write(dphy, dphy->dphyglueiftester, RESET);
  272. dw_dphy_if_write(dphy, dphy->dphyglueiftester, GLUELOGIC);
  273. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLR, 1);
  274. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLR, 1);
  275. //dw_dphy_if_write(dphy, DPHYZCALCTRL, 0);
  276. //dw_dphy_if_write(dphy, DPHYZCALCTRL, 1);
  277. dw_dphy_if_write(dphy, dphy->dphyglueiftester, RESET);
  278. dw_dphy_if_write(dphy, dphy->dphyglueiftester, RX_PHY);
  279. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLR, 1);
  280. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLR, 1);
  281. //dw_dphy_if_write(dphy, DPHYZCALCTRL, 0);
  282. //dw_dphy_if_write(dphy, DPHYZCALCTRL, 1);
  283. }
  284. #endif
  285. static void dw_dphy_gen3_12bit_tc_power_up(struct dw_dphy_rx *dphy, uint8_t hsfregrange)
  286. {
  287. #if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  288. dw_dphy_if_write(dphy, dphy->dphyglueiftester, RESET);
  289. dw_dphy_if_write(dphy, dphy->dphyglueiftester, GLUELOGIC); //用fpga时候是写到子板专有寄存器内,芯片要写到visys reg
  290. dw_dphy_te_write(dphy, CFGCLKFREQRANGE_RX, 0x1C); //TODO ASCI 改为通过vi sys寄存器去配置src clk
  291. dw_dphy_te_write(dphy, 0x6, hsfregrange); //TODO ASCI 改为通过vi sys寄存器去配置src clk
  292. #endif
  293. #if !IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  294. u32 reg_val = 0;
  295. reg_val = dw_dphy_if_read(dphy, dphy->sysreg_mipi_csi_ctrl); //TODO ASCI 改为通过vi sys寄存器去配置src clk
  296. reg_val &= ~0x3f;
  297. reg_val |= 0x1c;
  298. dw_dphy_if_write(dphy, dphy->sysreg_mipi_csi_ctrl, reg_val); //TODO ASCI 改为通过vi sys寄存器去配置src clk
  299. reg_val &= ~(0x7f << 8);
  300. reg_val |= (hsfregrange << 8);
  301. dw_dphy_if_write(dphy, dphy->sysreg_mipi_csi_ctrl, reg_val); //TODO ASCI 改为通过vi sys寄存器去配置src clk
  302. #endif
  303. /* CLKSEL | UPDATEPLL | SHADOW_CLEAR | SHADOW_CTRL | FORCEPLL */
  304. //dw_dphy_te_write(dphy, BYPASS, 0x3F);
  305. /* IO_DS3 | IO_DS2 | IO_DS1 | IO_DS0 */
  306. #if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  307. if ((dphy->dphy_freq/1000) > 1500) {
  308. dw_dphy_te_write(dphy, IO_DS, 0x0F);
  309. }
  310. dw_dphy_if_write(dphy, dphy->dphyglueiftester, RESET);
  311. dw_dphy_if_write(dphy, dphy->dphyglueiftester, RX_PHY | 0x2);
  312. #endif
  313. }
  314. static void dw_dphy_gen3_8bit_tc_power_up(struct dw_dphy_rx *dphy)
  315. {
  316. u32 input_freq = dphy->dphy_freq / 1000;
  317. #if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  318. dw_dphy_if_write(dphy, dphy->dphyglueiftester, RESET);
  319. dw_dphy_if_write(dphy, dphy->dphyglueiftester, GLUELOGIC);
  320. dw_dphy_te_write(dphy, CFGCLKFREQRANGE_RX, 0x1C);
  321. dw_dphy_if_write(dphy, dphy->dphyglueiftester, RESET);
  322. dw_dphy_if_write(dphy, dphy->dphyglueiftester, RX_PHY);
  323. #endif
  324. dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX0_MSB, 0x03);
  325. dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX0_LSB, 0x02);
  326. dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX1_MSB, 0x03);
  327. dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX1_LSB, 0x02);
  328. dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX2_MSB, 0x03);
  329. dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX2_LSB, 0x02);
  330. dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX3_MSB, 0x03);
  331. dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX3_LSB, 0x02);
  332. dw_dphy_te_write(dphy, BANDGAP_CTRL, 0x80);
  333. if (input_freq < 2000)
  334. dw_dphy_te_write(dphy, HS_RX_CTRL_LANE0, 0xC0);
  335. if (input_freq < 1000) {
  336. dw_dphy_te_write(dphy, HS_RX_CTRL_LANE1, 0xC0);
  337. dw_dphy_te_write(dphy, HS_RX_CTRL_LANE2, 0xC0);
  338. dw_dphy_te_write(dphy, HS_RX_CTRL_LANE3, 0xC0);
  339. }
  340. }
  341. int dw_dphy_g118_settle(struct dw_dphy_rx *dphy)
  342. {
  343. u32 input_freq, total_settle, settle_time, byte_clk, lp_time;
  344. lp_time = dphy->lp_time;
  345. input_freq = dphy->dphy_freq / 1000;
  346. settle_time = (8 * (1000000 / (input_freq))) + 115000;
  347. byte_clk = (8000000 / (input_freq));
  348. total_settle = (settle_time + lp_time * 1000) / byte_clk;
  349. if (total_settle > 0xFF)
  350. total_settle = 0xFF;
  351. return total_settle;
  352. }
  353. static void dw_dphy_pwr_down(struct dw_dphy_rx *dphy)
  354. {
  355. dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 0);
  356. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1);
  357. if (dphy->lanes_config == CTRL_8_LANES)
  358. dw_dphy_write_msk(dphy, R_CSI2_DPHY2_TST_CTRL0, 0, PHY_TESTCLK, 1);
  359. dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 0);
  360. }
  361. static void dw_dphy_pwr_up(struct dw_dphy_rx *dphy)
  362. {
  363. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1);
  364. if (dphy->lanes_config == CTRL_8_LANES)
  365. dw_dphy_write_msk(dphy, R_CSI2_DPHY2_TST_CTRL0, 1, PHY_TESTCLK,
  366. 1);
  367. dev_vdbg(&dphy->phy->dev, "DPHY power up.\n");
  368. dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 1);
  369. udelay(1);
  370. dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 1);
  371. udelay(1);
  372. }
  373. static int dw_dphy_gen3_12bit_configure(struct dw_dphy_rx *dphy, int abphy_flag)
  374. {
  375. u32 input_freq = dphy->dphy_freq;
  376. u8 range = 0;
  377. u32 reg_val = 0;
  378. dev_vdbg(&dphy->phy->dev, "12bit: PHY GEN 3: Freq: %u\n", input_freq);
  379. for (range = 0; (range < ARRAY_SIZE(range_gen3) - 1) &&
  380. ((input_freq / 1000) > range_gen3[range].freq);
  381. range++);
  382. input_freq /= 1000;
  383. dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 0);
  384. dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 0);
  385. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLR, 1);
  386. udelay(1);
  387. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLR, 1);
  388. dw_dphy_gen3_12bit_tc_power_up(dphy, range_gen3[range].hsfregrange);
  389. //uint8_t lp_time = dphy->lp_time;
  390. //dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_17, lp_time);//SET SETTLE TIME
  391. //位置1
  392. #if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  393. dw_dphy_te_write(dphy, RX_SYS_1, range_gen3[range].hsfregrange);
  394. dw_dphy_te_write(dphy, RX_SYS_0, 0x20);
  395. dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_2, 0xcc);
  396. #else
  397. //used for asic
  398. if (input_freq > 1500) {
  399. dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_2, (u8)(range_gen3[range].osc_freq_target & 0xff));
  400. dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_3, (u8)(range_gen3[range].osc_freq_target >> 8));
  401. }
  402. #endif
  403. #if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  404. dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_4, 0x21); //TODO fpga val=0x21, chip val=0x11
  405. dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_5, 0x01); //TODO 顺序位置配置可能需要调到位置1
  406. #else
  407. reg_val = dw_dphy_te_read(dphy, RX_RX_STARTUP_OVR_4);
  408. reg_val &= ~(0xf0);
  409. reg_val |= (1 << 4);
  410. dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_4, reg_val);
  411. if (input_freq > 1500) {
  412. reg_val = dw_dphy_te_read(dphy, RX_RX_STARTUP_OVR_4);
  413. reg_val |= 1;
  414. dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_4, reg_val); //TODO fpga val=0x21, chip val=0x11
  415. }
  416. reg_val = dw_dphy_te_read(dphy, RX_RX_STARTUP_OVR_5);
  417. reg_val |= 1;
  418. dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_5, reg_val); //TODO 顺序位置配置可能需要调到位置1
  419. reg_val = dw_dphy_te_read(dphy, RX_RX_CB_1); //TODO used to chip
  420. reg_val &= ~0x3;
  421. reg_val |= 2;
  422. dw_dphy_te_write(dphy, RX_RX_CB_1, reg_val); //TODO used to chip
  423. reg_val = dw_dphy_te_read(dphy, RX_RX_CB_2); //TODO used to chip
  424. reg_val |= (1 << 6);
  425. dw_dphy_te_write(dphy, RX_RX_CB_2, reg_val); //TODO used to chip
  426. if (abphy_flag) {
  427. reg_val = dw_dphy_te_read(dphy, RX_RX_CLKLANE_LANE_6); //TODO used to chip
  428. reg_val |= (1 << 7);
  429. dw_dphy_te_write(dphy, RX_RX_CLKLANE_LANE_6, reg_val); //TODO used to chip
  430. }
  431. if (input_freq <= 1500) {
  432. reg_val = dw_dphy_te_read(dphy, 0x607); //TODO used to chip
  433. reg_val |= 0x3f;
  434. dw_dphy_te_write(dphy, 0x607, reg_val); //TODO used to chip
  435. reg_val = dw_dphy_te_read(dphy, 0x807); //TODO used to chip
  436. reg_val |= 0x3f;
  437. dw_dphy_te_write(dphy, 0x807, reg_val); //TODO used to chip
  438. reg_val = dw_dphy_te_read(dphy, 0xa07); //TODO used to chip
  439. reg_val |= 0x3f;
  440. dw_dphy_te_write(dphy, 0xa07, reg_val); //TODO used to chip
  441. reg_val = dw_dphy_te_read(dphy, 0xc07); //TODO used to chip
  442. reg_val |= 0x3f;
  443. dw_dphy_te_write(dphy, 0xc07, reg_val); //TODO used to chip
  444. } else {
  445. dw_dphy_te_write(dphy, RX_SYS_9, 0x43); //TODO used to chip
  446. }
  447. //for chip dphy->sysreg_mipi_csi_ctrl: csi2_0, csi2_1, csi2_2 -> 0x140, 0x144, 0x148
  448. reg_val = dw_dphy_if_read(dphy, dphy->sysreg_mipi_csi_ctrl);
  449. reg_val |= (1 << 28) | (1 << 25) | (7 << 20);
  450. dw_dphy_if_write(dphy, dphy->sysreg_mipi_csi_ctrl, reg_val); //TODO set visys reg basedir_0 =1, set visys reg forcerxmode_0123=1
  451. #endif
  452. udelay(1);
  453. if (dphy->phy_type) {
  454. #if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  455. dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_1, 0x01);
  456. dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_0, 0x80);
  457. #endif
  458. }
  459. #if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  460. dw_dphy_te_write(dphy, RX_SYS_3, 0x59);
  461. #endif
  462. if (dphy->phy_type || input_freq <= 1500) {
  463. reg_val = dw_dphy_te_read(dphy, RX_SYS_7);
  464. reg_val |= (1 << 5);
  465. dw_dphy_te_write(dphy, RX_SYS_7, reg_val);
  466. }
  467. dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 1);
  468. udelay(1);
  469. dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 1);
  470. udelay(600);
  471. //TODO set visys reg mipi_csi2x2_a_forcerxmode_0=0 这个先不要配置,应该不需要设置为0
  472. reg_val = dw_dphy_if_read(dphy, dphy->sysreg_mipi_csi_ctrl);
  473. reg_val &= ~((1 << 25) | (7 << 20));
  474. dw_dphy_if_write(dphy, dphy->sysreg_mipi_csi_ctrl, reg_val); //TODO set visys reg basedir_0 =1, set visys reg forcerxmode_0123=0
  475. return 0;
  476. }
  477. static void dw_dphy_combination_4lane_switch_master(struct dw_dphy_rx *dphy)
  478. {
  479. u32 sys_reg_val = 0;
  480. sys_reg_val = dw_dphy_if_read(dphy, dphy->sysreg_mipi_csi_ctrl);
  481. sys_reg_val |= 1;
  482. dw_dphy_if_write(dphy, dphy->sysreg_mipi_csi_ctrl, sys_reg_val); //切换寄存器到master
  483. }
  484. static void dw_dphy_combination_4lane_switch_slave(struct dw_dphy_rx *dphy)
  485. {
  486. u32 sys_reg_val = 0;
  487. sys_reg_val = dw_dphy_if_read(dphy, dphy->sysreg_mipi_csi_ctrl);
  488. sys_reg_val &= ~1;
  489. dw_dphy_if_write(dphy, dphy->sysreg_mipi_csi_ctrl, sys_reg_val); //切换寄存器到slave
  490. }
  491. #if !IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  492. //用于dphy 两个2lane组合成4lane的模式下phy初始化
  493. static int dw_dphy_12bit_combination_4lane_configure(struct dw_dphy_rx *dphy)
  494. {
  495. u32 input_freq = dphy->dphy_freq;
  496. u32 phy_reg_val = 0;
  497. u8 range = 0;
  498. dw_dphy_pwr_down(dphy);
  499. dev_vdbg(&dphy->phy->dev, "12bit: PHY GEN 3: Freq: %u\n", input_freq);
  500. for (range = 0; (range < ARRAY_SIZE(range_gen3) - 1) &&
  501. ((input_freq / 1000) > range_gen3[range].freq);
  502. range++);
  503. //Define master PHY and slave PHY and configure each accordingly
  504. //(this choice needs to be coherent with wiring connections mentioned above):
  505. dw_dphy_combination_4lane_switch_master(dphy);
  506. dw_dphy_te_write(dphy, RX_RX_DUAL_PHY_0, 0x01); //2lane合并为4lane,设置master
  507. dw_dphy_combination_4lane_switch_slave(dphy);
  508. dw_dphy_te_write(dphy, RX_RX_DUAL_PHY_0, 0x00); //2lane合并为4lane,设置slave
  509. //Configure master PHY clock lane to drive long channel clock
  510. dw_dphy_combination_4lane_switch_master(dphy);
  511. phy_reg_val = dw_dphy_te_read(dphy, RX_RX_CLKLANE_LANE_6);
  512. phy_reg_val |= (1 << 2);
  513. dw_dphy_te_write(dphy, RX_RX_CLKLANE_LANE_6, phy_reg_val); //2lane合并为4lane,设置master
  514. dw_dphy_combination_4lane_switch_slave(dphy);
  515. phy_reg_val &= ~(1 << 2);
  516. dw_dphy_te_write(dphy, RX_RX_CLKLANE_LANE_6, phy_reg_val); //2lane合并为4lane,设置slave
  517. //Configure both master and slave PHY data lanes to get clock from long channel:
  518. dw_dphy_combination_4lane_switch_master(dphy);
  519. phy_reg_val = dw_dphy_te_read(dphy, 0x508);
  520. phy_reg_val |= (1 << 5);
  521. dw_dphy_te_write(dphy, 0x508, phy_reg_val); //2lane合并为4lane,设置slave
  522. dw_dphy_combination_4lane_switch_slave(dphy);
  523. phy_reg_val = dw_dphy_te_read(dphy, 0x508);
  524. phy_reg_val |= (1 << 5);
  525. dw_dphy_te_write(dphy, 0x508, phy_reg_val); //2lane合并为4lane,设置slave
  526. dw_dphy_combination_4lane_switch_master(dphy);
  527. phy_reg_val = dw_dphy_te_read(dphy, 0x708);
  528. phy_reg_val |= (1 << 5);
  529. dw_dphy_te_write(dphy, 0x708, phy_reg_val); //2lane合并为4lane,设置slave
  530. dw_dphy_combination_4lane_switch_slave(dphy);
  531. phy_reg_val = dw_dphy_te_read(dphy, 0x708);
  532. phy_reg_val |= (1 << 5);
  533. dw_dphy_te_write(dphy, 0x708, phy_reg_val); //2lane合并为4lane,设置slave
  534. dw_dphy_combination_4lane_switch_master(dphy);
  535. phy_reg_val = dw_dphy_te_read(dphy, 0x908);
  536. phy_reg_val |= (1 << 5);
  537. dw_dphy_te_write(dphy, 0x908, phy_reg_val); //2lane合并为4lane,设置slave
  538. dw_dphy_combination_4lane_switch_slave(dphy);
  539. phy_reg_val = dw_dphy_te_read(dphy, 0x908);
  540. phy_reg_val |= (1 << 5);
  541. dw_dphy_te_write(dphy, 0x908, phy_reg_val); //2lane合并为4lane,设置slave
  542. dw_dphy_combination_4lane_switch_master(dphy);
  543. phy_reg_val = dw_dphy_te_read(dphy, 0xB08);
  544. phy_reg_val |= (1 << 5);
  545. dw_dphy_te_write(dphy, 0xB08, phy_reg_val); //2lane合并为4lane,设置slave
  546. dw_dphy_combination_4lane_switch_slave(dphy);
  547. phy_reg_val = dw_dphy_te_read(dphy, 0xB08);
  548. phy_reg_val |= (1 << 5);
  549. dw_dphy_te_write(dphy, 0xB08, phy_reg_val); //2lane合并为4lane,设置slave
  550. //Configure slave PHY clock lane to bypass long channel clock to DDR clock:
  551. dw_dphy_combination_4lane_switch_master(dphy);
  552. phy_reg_val = dw_dphy_te_read(dphy, 0x308);
  553. phy_reg_val &= ~(1 << 3);
  554. dw_dphy_te_write(dphy, 0x308, phy_reg_val); //2lane合并为4lane,设置slave
  555. dw_dphy_combination_4lane_switch_slave(dphy);
  556. phy_reg_val = dw_dphy_te_read(dphy, 0x308);
  557. phy_reg_val |= (1 << 3);
  558. dw_dphy_te_write(dphy, 0x308, phy_reg_val); //2lane合并为4lane,设置slave
  559. //Override slave PHY DDR clock lane enable (DPHYHSRX_div124 module):
  560. dw_dphy_combination_4lane_switch_slave(dphy);
  561. phy_reg_val = dw_dphy_te_read(dphy, 0x0e1);
  562. phy_reg_val |= (1 << 1);
  563. dw_dphy_te_write(dphy, 0x0e1, phy_reg_val); //2lane合并为4lane,设置slave
  564. phy_reg_val = dw_dphy_te_read(dphy, RX_RX_CLKLANE_LANE_6);
  565. phy_reg_val |= (1 << 3);
  566. dw_dphy_te_write(dphy, RX_RX_CLKLANE_LANE_6, phy_reg_val); //2lane合并为4lane,设置slave
  567. //Turn off slave PHY LP-RX clock lane:
  568. dw_dphy_combination_4lane_switch_slave(dphy);
  569. phy_reg_val = dw_dphy_te_read(dphy, 0x304);
  570. phy_reg_val &= ~0x1f;
  571. phy_reg_val |= 0xa;
  572. dw_dphy_te_write(dphy, 0x304, phy_reg_val); //2lane合并为4lane,设置slave
  573. //Configure both PHYs as described in“Start-Up Sequence” on page 81
  574. //until step enable_n and enableclk=1'b1 (skip step Configure register
  575. //0x307 to set rxclk_rxhs_pull_long_channel_if_rw signal (bit 8) to 1'b1).
  576. dw_dphy_gen3_12bit_configure(dphy, 1);
  577. //Set shutdownz=1'b1 in master and slave PHYs.
  578. dw_dphy_combination_4lane_switch_master(dphy);
  579. dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 1);
  580. dw_dphy_combination_4lane_switch_slave(dphy);
  581. dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 1);
  582. //Release reset for master PHY (rstz=1'b1).
  583. dw_dphy_combination_4lane_switch_master(dphy);
  584. dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 1);
  585. udelay(1);
  586. //Release reset for slave PHY (rstz=1'b1).
  587. dw_dphy_combination_4lane_switch_slave(dphy);
  588. dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 1);
  589. udelay(600);
  590. //Set forcerxmode_n in master and slave PHY = 1'b0.
  591. //???
  592. #if 0
  593. dw_dphy_gen3_12bit_tc_power_up(dphy, range_gen3[range].hsfregrange);
  594. //uint8_t lp_time = dphy->lp_time;
  595. //dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_17, lp_time);//SET SETTLE TIME
  596. //位置1
  597. dw_dphy_te_write(dphy, RX_SYS_1, range_gen3[range].hsfregrange);
  598. dw_dphy_te_write(dphy, RX_SYS_0, 0x20);
  599. #if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  600. dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_2, 0xcc);
  601. #else
  602. //used for asic
  603. dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_2, (u8)(range_gen3[range].osc_freq_target & 0xff));
  604. #endif
  605. dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_3,
  606. (u8)(range_gen3[range].osc_freq_target >> 8));
  607. #if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  608. dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_4, 0x21); //TODO fpga val=0x21, chip val=0x11
  609. dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_5, 0x01); //TODO 顺序位置配置可能需要调到位置1
  610. #else
  611. dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_4, 0x11); //TODO fpga val=0x21, chip val=0x11
  612. dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_5, 0x01); //TODO 顺序位置配置可能需要调到位置1
  613. dw_dphy_te_write(dphy, RX_RX_CB_1, 0x02); //TODO used to chip
  614. dw_dphy_te_write(dphy, RX_RX_CB_2, 0x1 << 6); //TODO used to chip
  615. dw_dphy_te_write(dphy, RX_SYS_9, 0x43); //TODO used to chip
  616. dw_dphy_te_write(dphy, RX_RX_CLKLANE_LANE_6, 0x1 << 7); //TODO used to chip
  617. //for chip dphy->dphyglueiftester : csi2_0, csi2_1, csi2_2 -> 0x140, 0x144, 0x148
  618. reg_val = dw_dphy_if_read(dphy, dphy->dphyglueiftester);
  619. reg_val |= (1 << 28) | (1 << 25);
  620. dw_dphy_if_write(dphy, dphy->dphyglueiftester, reg_val); //TODO set visys reg basedir_0 =1, set visys reg forcerxmode_0=1
  621. #endif
  622. if (dphy->phy_type) {
  623. dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_1, 0x01);
  624. dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_0, 0x80);
  625. }
  626. dw_dphy_te_write(dphy, RX_SYS_3, 0x59);
  627. dw_dphy_te_write(dphy, RX_SYS_7, 0x38);
  628. if (dphy->phy_type || input_freq <= 1500)
  629. dw_dphy_te_write(dphy, RX_SYS_7, 0x38);
  630. //TODO set visys reg mipi_csi2x2_a_forcerxmode_0=0 这个先不要配置,应该不需要设置为0
  631. //reg_val &= ~(1 << 25);
  632. //dw_dphy_if_write(dphy, dphy->dphyglueiftester, reg_val);
  633. #endif
  634. return 0;
  635. }
  636. #endif
  637. static int dw_dphy_gen3_8bit_configure(struct dw_dphy_rx *dphy)
  638. {
  639. u32 input_freq = dphy->dphy_freq;
  640. u8 data;
  641. u8 range = 0;
  642. dev_vdbg(&dphy->phy->dev, "8bit: PHY GEN 3: Freq: %u\n", input_freq);
  643. for (range = 0; (range < ARRAY_SIZE(range_gen3) - 1) &&
  644. ((input_freq / 1000) > range_gen3[range].freq);
  645. range++)
  646. ;
  647. dw_dphy_te_write(dphy, RX_SKEW_CAL, dw_dphy_g118_settle(dphy));
  648. data = 1 << 7 | range_gen3[range].hsfregrange;
  649. dw_dphy_te_write(dphy, HSFREQRANGE_8BIT, data);
  650. dw_dphy_gen3_8bit_tc_power_up(dphy);
  651. return 0;
  652. }
  653. static int dw_dphy_gen2_configure(struct dw_dphy_rx *dphy)
  654. {
  655. u32 input_freq = dphy->dphy_freq;
  656. u8 data;
  657. u8 range = 0;
  658. /* provide an initial active-high test clear pulse in TESTCLR */
  659. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLR, 1);
  660. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLR, 1);
  661. dev_vdbg(&dphy->phy->dev, "PHY GEN 2: Freq: %u\n", input_freq);
  662. for (range = 0; (range < ARRAY_SIZE(range_gen2) - 1) &&
  663. ((input_freq / 1000) > range_gen2[range].freq); range++)
  664. ;
  665. data = range_gen2[range].hsfregrange << 1;
  666. dw_dphy_te_write(dphy, HSFREQRANGE_8BIT, data);
  667. return 0;
  668. }
  669. static int dw_dphy_configure(struct dw_dphy_rx *dphy)
  670. {
  671. bm_info("enter %s\n", __func__);
  672. dw_dphy_pwr_down(dphy);
  673. dphy->dphy_gen = GEN3;
  674. if (dphy->dphy_gen == GEN3) {
  675. #if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  676. dw_dphy_if_init(dphy);
  677. #endif
  678. dphy->dphy_te_len = BIT12;
  679. if (dphy->dphy_te_len == BIT12)
  680. dw_dphy_gen3_12bit_configure(dphy, 1);
  681. else
  682. dw_dphy_gen3_8bit_configure(dphy);
  683. } else {
  684. dw_dphy_gen2_configure(dphy);
  685. }
  686. dw_dphy_pwr_up(dphy);
  687. return 0;
  688. }
  689. #if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  690. #if 0
  691. int dw_dphy_if_set_idelay(struct dw_dphy_rx *dphy, u8 dly, u8 cells)
  692. {
  693. u32 val = 0;
  694. dw_dphy_if_write(dphy, IDLYCFG, 0);
  695. dw_dphy_if_write(dphy, IDLYSEL, cells);
  696. dw_dphy_if_write(dphy, IDLYCNTINVAL, dly);
  697. /* Pulse Value Set */
  698. dw_dphy_if_write(dphy, IDLYCFG, 1);
  699. usleep_range(10, 20);
  700. dw_dphy_if_write(dphy, IDLYCFG, 0);
  701. /* Pulse IDELAY CTRL Reset */
  702. dw_dphy_if_write(dphy, DPHY1REGRSTN, 0);
  703. usleep_range(10, 20);
  704. dw_dphy_if_write(dphy, DPHY1REGRSTN, 1);
  705. /* Get Value*/
  706. val = dw_dphy_if_read(dphy, IDLYCNTOUTVAL);
  707. if (val != dly) {
  708. dev_vdbg(&dphy->phy->dev,
  709. "odelay config failed, set %d get %d", dly, val);
  710. return -EINVAL;
  711. }
  712. return 0;
  713. }
  714. int dw_dphy_if_get_idelay(struct dw_dphy_rx *dphy)
  715. {
  716. return dw_dphy_if_read(dphy, IDLYCNTOUTVAL);
  717. }
  718. int dw_dphy_if_set_idelay_lane(struct dw_dphy_rx *dphy, u8 dly, u8 lane)
  719. {
  720. int cell;
  721. switch (lane) {
  722. case 0:
  723. for (cell = 3; cell <= 10; cell++)
  724. dw_dphy_if_set_idelay(dphy, dly, cell);
  725. break;
  726. case 1:
  727. for (cell = 14; cell <= 21; cell++)
  728. dw_dphy_if_set_idelay(dphy, dly, cell);
  729. break;
  730. case 2:
  731. for (cell = 24; cell <= 31; cell++)
  732. dw_dphy_if_set_idelay(dphy, dly, cell);
  733. break;
  734. case 3:
  735. for (cell = 34; cell <= 41; cell++)
  736. dw_dphy_if_set_idelay(dphy, dly, cell);
  737. break;
  738. case 4: /* ALL */
  739. dw_dphy_if_set_idelay(dphy, dly, 0x7F);
  740. break;
  741. default:
  742. dev_err(&dphy->phy->dev, "Lane Value not recognized\n");
  743. return -1;
  744. }
  745. return 0;
  746. }
  747. #endif
  748. #endif
  749. int dw_dphy_init(struct phy *phy)
  750. {
  751. struct dw_dphy_rx *dphy = phy_get_drvdata(phy);
  752. dev_warn(&dphy->phy->dev, "Init DPHY.\n");
  753. dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 0);
  754. dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 0);
  755. return 0;
  756. }
  757. static int dw_dphy_set_phy_state(struct dw_dphy_rx *dphy, u32 on)
  758. {
  759. u8 hs_freq;
  760. bm_info("enter %s\n", __func__);
  761. dphy->lanes_config = dw_dphy_setup_config(dphy);
  762. if (dphy->dphy_te_len == BIT12)
  763. hs_freq = RX_SYS_1;
  764. else
  765. hs_freq = HSFREQRANGE_8BIT;
  766. if (on) {
  767. dw_dphy_configure(dphy);
  768. dev_info(&dphy->phy->dev,
  769. "HS Code: 0X%x\n", dw_dphy_te_read(dphy, hs_freq));
  770. } else {
  771. dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 0);
  772. dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 0);
  773. }
  774. return 0;
  775. }
  776. int dw_dphy_power_on(struct phy *phy)
  777. {
  778. struct dw_dphy_rx *dphy = phy_get_drvdata(phy);
  779. dev_info(&dphy->phy->dev, "DPHY Power ON\n");
  780. bm_info("enter %s\n", __func__);
  781. dphy->phy_type = 1;
  782. return dw_dphy_set_phy_state(dphy, 1);
  783. }
  784. int dw_dphy_power_off(struct phy *phy)
  785. {
  786. struct dw_dphy_rx *dphy = phy_get_drvdata(phy);
  787. return dw_dphy_set_phy_state(dphy, 0);
  788. }
  789. int dw_dphy_reset(struct phy *phy)
  790. {
  791. struct dw_dphy_rx *dphy = phy_get_drvdata(phy);
  792. dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 0);
  793. usleep_range(100, 200);
  794. dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 1);
  795. return 0;
  796. }