dw-csi-plat.c 9.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
  4. *
  5. * Synopsys DesignWare MIPI CSI-2 Host controller driver.
  6. * Platform driver
  7. *
  8. * Author: Luis Oliveira <luis.oliveira@synopsys.com>
  9. */
  10. #include "dw-csi-data.h"
  11. #include "dw-dphy-data.h"
  12. #include "dw-csi-plat.h"
  13. #include "bm_csi_hw.h"
  14. const struct mipi_dt csi_dt[] = {
  15. {
  16. .hex = CSI_2_YUV420_8,
  17. .name = "YUV420_8bits",
  18. }, {
  19. .hex = CSI_2_YUV420_10,
  20. .name = "YUV420_10bits",
  21. }, {
  22. .hex = CSI_2_YUV420_8_LEG,
  23. .name = "YUV420_8bits_LEGACY",
  24. }, {
  25. .hex = CSI_2_YUV420_8_SHIFT,
  26. .name = "YUV420_8bits_SHIFT",
  27. }, {
  28. .hex = CSI_2_YUV420_10_SHIFT,
  29. .name = "YUV420_10bits_SHIFT",
  30. }, {
  31. .hex = CSI_2_YUV422_8,
  32. .name = "YUV442_8bits",
  33. }, {
  34. .hex = CSI_2_YUV422_10,
  35. .name = "YUV442_10bits",
  36. }, {
  37. .hex = CSI_2_RGB444,
  38. .name = "RGB444",
  39. }, {
  40. .hex = CSI_2_RGB555,
  41. .name = "RGB555",
  42. }, {
  43. .hex = CSI_2_RGB565,
  44. .name = "RGB565",
  45. }, {
  46. .hex = CSI_2_RGB666,
  47. .name = "RGB666",
  48. }, {
  49. .hex = CSI_2_RGB888,
  50. .name = "RGB888",
  51. }, {
  52. .hex = CSI_2_RAW6,
  53. .name = "RAW6",
  54. }, {
  55. .hex = CSI_2_RAW7,
  56. .name = "RAW7",
  57. }, {
  58. .hex = CSI_2_RAW8,
  59. .name = "RAW8",
  60. }, {
  61. .hex = CSI_2_RAW10,
  62. .name = "RAW10",
  63. }, {
  64. .hex = CSI_2_RAW12,
  65. .name = "RAW12",
  66. }, {
  67. .hex = CSI_2_RAW14,
  68. .name = "RAW14",
  69. }, {
  70. .hex = CSI_2_RAW16,
  71. .name = "RAW16",
  72. },
  73. };
  74. static struct mipi_fmt *
  75. find_dw_mipi_csi_format(uint32_t mbus_code)
  76. {
  77. unsigned int i;
  78. pr_info("%s entered mbus: 0x%x\n", __func__, mbus_code);
  79. for (i = 0; i < ARRAY_SIZE(dw_mipi_csi_formats); i++)
  80. if (mbus_code == dw_mipi_csi_formats[i].mbus_code) {
  81. pr_info("Found mbus 0x%x\n", dw_mipi_csi_formats[i].mbus_code);
  82. return &dw_mipi_csi_formats[i];
  83. }
  84. return NULL;
  85. }
  86. int dw_mipi_csi_enum_mbus_code(int index, uint32_t *code)
  87. {
  88. if (index != 0)
  89. return -EINVAL;
  90. *code = dw_mipi_csi_formats[index].mbus_code;
  91. return 0;
  92. }
  93. static struct mipi_fmt *
  94. dw_mipi_csi_try_format(uint32_t mbus_code)
  95. {
  96. struct mipi_fmt *fmt;
  97. fmt = find_dw_mipi_csi_format(mbus_code);
  98. if (!fmt)
  99. fmt = &dw_mipi_csi_formats[0];
  100. return fmt;
  101. }
  102. struct mipi_fmt *
  103. dw_mipi_csi_get_format(struct dw_csi *dev)
  104. {
  105. dev_info(dev->dev,
  106. "%s got v4l2_mbus_pixelcode. 0x%x\n", __func__,
  107. dev->fmt->mbus_code);
  108. dev_info(dev->dev,
  109. "%s got width. 0x%x\n", __func__,
  110. dev->fmt->width);
  111. dev_info(dev->dev,
  112. "%s got height. 0x%x\n", __func__,
  113. dev->fmt->height);
  114. return dev->fmt;
  115. }
  116. int
  117. dw_mipi_csi_set_fmt(struct platform_device *pdev,
  118. uint32_t mbus_code, uint32_t width, uint32_t height)
  119. {
  120. struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev);
  121. struct dw_csi *dev = &drvdata->csi_dev;
  122. struct mipi_fmt *dev_fmt = NULL;
  123. int i;
  124. dev_info(dev->dev,
  125. "%s got mbus_pixelcode. 0x%x\n", __func__,
  126. mbus_code);
  127. dev_fmt = dw_mipi_csi_try_format(mbus_code);
  128. dev_info(dev->dev,
  129. "%s got v4l2_mbus_pixelcode. 0x%x\n", __func__,
  130. dev_fmt->mbus_code);
  131. if (!dev_fmt)
  132. return -EINVAL;
  133. if (dev_fmt) {
  134. dev->fmt->mbus_code = dev_fmt->mbus_code;
  135. dev->fmt->width = width;
  136. dev->fmt->height = height;
  137. dw_mipi_csi_set_ipi_fmt(dev);
  138. }
  139. dev_info(dev->dev, "Width: %d, Height: %d of Demo\n", width, height);
  140. if (width > 0 && height > 0) {
  141. dw_mipi_csi_fill_timings(dev, width, height);
  142. /*
  143. demo_writel(dev,
  144. DEMO_ACTIVE_WIDTH, fmt->format.width);
  145. demo_writel(dev,
  146. DEMO_ACTIVE_HEIGHT, fmt->format.height);
  147. */
  148. dev_vdbg(dev->dev,
  149. "(core/demosaic) : width=%d/%d, height=%d/%d\n",
  150. dev->hw.htotal - (dev->hw.hbp
  151. + dev->hw.hsd
  152. + dev->hw.hsa),
  153. width,
  154. dev->hw.vactive,
  155. height);
  156. dev_info(dev->dev,
  157. "(core/demosaic) : width=%d/%d, height=%d/%d\n",
  158. dev->hw.htotal - (dev->hw.hbp
  159. + dev->hw.hsd
  160. + dev->hw.hsa),
  161. width,
  162. dev->hw.vactive,
  163. height);
  164. } else {
  165. dev_vdbg(dev->dev, "%s unacceptable values 0x%x.\n",
  166. __func__, width);
  167. dev_vdbg(dev->dev, "%s unacceptable values 0x%x.\n",
  168. __func__, height);
  169. dev_info(dev->dev, "%s unacceptable values 0x%x.\n",
  170. __func__, width);
  171. dev_info(dev->dev, "%s unacceptable values 0x%x.\n",
  172. __func__, height);
  173. return -EINVAL;
  174. }
  175. for (i = 0; i < ARRAY_SIZE(csi_dt); i++)
  176. if (csi_dt[i].hex == dev->ipi_dt) {
  177. dev_vdbg(dev->dev, "Using data type %s\n",
  178. csi_dt[i].name);
  179. dev_info(dev->dev, "Using data type %s\n",
  180. csi_dt[i].name);
  181. }
  182. return 0;
  183. }
  184. int
  185. dw_mipi_csi_get_fmt(struct platform_device *pdev,
  186. struct mipi_fmt *fmt)
  187. {
  188. struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev);
  189. struct dw_csi *dev = &drvdata->csi_dev;
  190. struct mipi_fmt *mf = dw_mipi_csi_get_format(dev);
  191. if (!mf)
  192. return -EINVAL;
  193. mutex_lock(&dev->lock);
  194. *fmt = *mf;
  195. mutex_unlock(&dev->lock);
  196. return 0;
  197. }
  198. int dw_mipi_csi_s_power(struct dw_csi *dev, int on)
  199. {
  200. dev_info(dev->dev, "%s: on=%d\n", __func__, on);
  201. if (on) {
  202. dw_dphy_power_on(dev->phy);
  203. dw_mipi_csi_hw_stdby(dev);
  204. dw_mipi_csi_start(dev);
  205. } else {
  206. phy_power_off(dev->phy);
  207. dw_mipi_csi_mask_irq_power_off(dev);
  208. /* reset data type */
  209. dev->ipi_dt = 0x0;
  210. }
  211. return 0;
  212. }
  213. int dw_mipi_csi_log_status(struct dw_csi *dev)
  214. {
  215. dw_mipi_csi_dump(dev);
  216. return 0;
  217. }
  218. #if IS_ENABLED(CONFIG_VIDEO_ADV_DEBUG)
  219. int
  220. dw_mipi_csi_g_register(struct v4l2_subdev *sd, uint32_t reg)
  221. {
  222. struct bm_csi_drvdata *drvdata = platform_get_drvdata(pdev);
  223. struct dw_csi *dev = &drvdata->csi_dev;
  224. dev_vdbg(dev->dev, "%s: reg=%llu\n", __func__, reg);
  225. reg->val = dw_mipi_csi_read(dev, reg);
  226. return 0;
  227. }
  228. #endif
  229. #if 0
  230. static int dw_mipi_csi_init_cfg(struct v4l2_subdev *sd,
  231. struct v4l2_subdev_pad_config *cfg)
  232. {
  233. struct v4l2_mbus_framefmt *format =
  234. v4l2_subdev_get_try_format(sd, cfg, 0);
  235. format->colorspace = V4L2_COLORSPACE_SRGB;
  236. format->code = MEDIA_BUS_FMT_RGB888_1X24;
  237. format->field = V4L2_FIELD_NONE;
  238. return 0;
  239. }
  240. #endif
  241. static irqreturn_t dw_mipi_csi_irq1(int irq, void *dev_id)
  242. {
  243. struct dw_csi *csi_dev = dev_id;
  244. dw_mipi_csi_irq_handler(csi_dev);
  245. return IRQ_HANDLED;
  246. }
  247. extern int k_bm_visys_write_reg(uint32_t offset, uint32_t value);
  248. extern int k_bm_visys_read_reg(uint32_t offset, uint32_t *value);
  249. void dw_csi_soc_reset(void)
  250. {
  251. #define VISYS_SW_RST 0x100
  252. uint32_t reg_val = 0;
  253. k_bm_visys_read_reg(VISYS_SW_RST, &reg_val);
  254. reg_val &= ~(1 << 16);
  255. k_bm_visys_write_reg(VISYS_SW_RST, reg_val);
  256. reg_val |= 1 << 16;
  257. k_bm_visys_write_reg(VISYS_SW_RST, reg_val);
  258. }
  259. #define MIPI_CSI_PIXELCLK 0x30
  260. #define MIPI_CSI_PIXELSRC_CLK 2376000000 //hz
  261. int dw_csi_set_pixclk(uint32_t freq_hz)
  262. {
  263. uint32_t reg_val = 0;
  264. uint32_t div = (MIPI_CSI_PIXELSRC_CLK + (MIPI_CSI_PIXELSRC_CLK % freq_hz)) / freq_hz;
  265. if (freq_hz > MIPI_CSI_PIXELSRC_CLK || div > 0xf) {
  266. return -1;
  267. }
  268. k_bm_visys_read_reg(MIPI_CSI_PIXELCLK, &reg_val);
  269. reg_val &= ~0xf;
  270. reg_val |= div;
  271. k_bm_visys_write_reg(MIPI_CSI_PIXELCLK, reg_val);
  272. return 0;
  273. }
  274. int dw_csi_get_pixclk(uint32_t *freq_hz)
  275. {
  276. uint32_t reg_val = 0;
  277. uint32_t div = 0;
  278. k_bm_visys_read_reg(MIPI_CSI_PIXELCLK, &reg_val);
  279. div = reg_val & 0xf;
  280. *freq_hz = MIPI_CSI_PIXELSRC_CLK / div;
  281. return 0;
  282. }
  283. static const struct of_device_id dw_mipi_csi_of_match[];
  284. int dw_csi_probe(struct platform_device *pdev)
  285. {
  286. struct device *dev = &pdev->dev;
  287. struct dw_csi *csi;
  288. struct dw_dphy_rx *dphy;
  289. struct dw_csih_pdata *pdata;
  290. struct bm_csi_drvdata *drvdata;
  291. int ret;
  292. if (!IS_ENABLED(CONFIG_OF))
  293. dev_vdbg(dev, "Probing started\n");
  294. /* Resource allocation */
  295. drvdata = platform_get_drvdata(pdev);
  296. csi = &drvdata->csi_dev;
  297. dphy = drvdata->dphy;
  298. pdata = &drvdata->csi_pdata;
  299. mutex_init(&csi->lock);
  300. spin_lock_init(&csi->slock);
  301. csi->dev = dev;
  302. /*set csi phy*/
  303. csi->phy = dphy->phy;
  304. csi->base_address = drvdata->base;
  305. if (IS_ERR(csi->base_address)) {
  306. dev_err(dev, "base address not set.\n");
  307. return PTR_ERR(csi->base_address);
  308. }
  309. csi->ctrl_irq_number = drvdata->irq_num;
  310. if (csi->ctrl_irq_number < 0) {
  311. dev_err(dev, "irq number %d not set.\n", csi->ctrl_irq_number);
  312. ret = csi->ctrl_irq_number;
  313. goto end;
  314. }
  315. ret = devm_request_irq(dev, csi->ctrl_irq_number,
  316. dw_mipi_csi_irq1, IRQF_SHARED,
  317. dev_name(dev), csi);
  318. if (ret) {
  319. dev_err(dev, "irq csi %d failed\n", pdata->id);
  320. goto end;
  321. }
  322. csi->fmt = &dw_mipi_csi_formats[0];
  323. csi->fmt->mbus_code = dw_mipi_csi_formats[0].mbus_code;
  324. /*
  325. to do pad init
  326. */
  327. csi->hw.num_lanes = pdata->lanes;
  328. csi->hw.pclk = pdata->pclk;
  329. csi->hw.fps = pdata->fps;
  330. csi->hw.dphy_freq = pdata->hs_freq;
  331. csi->hw.ipi_mode = CAMERA_TIMING;
  332. csi->hw.ipi_color_mode = COLOR16;
  333. //csi soc reset
  334. dw_csi_soc_reset();
  335. dw_csi_create_capabilities_sysfs(pdev);
  336. dw_mipi_csi_get_version(csi);
  337. dw_mipi_csi_specific_mappings(csi);
  338. dw_mipi_csi_mask_irq_power_off(csi);
  339. dev_info(dev, "DW MIPI CSI-2 Host registered successfully HW v%u.%u\n",
  340. csi->hw_version_major, csi->hw_version_minor);
  341. ret = phy_reset(csi->phy);
  342. if (ret) {
  343. dev_err(&csi->phy->dev, "phy init failed --> %d\n", ret);
  344. goto end;
  345. }
  346. ret = phy_init(csi->phy);
  347. if (ret) {
  348. dev_err(&csi->phy->dev, "phy init failed --> %d\n", ret);
  349. goto end;
  350. }
  351. return 0;
  352. end:
  353. return ret;
  354. }
  355. int dw_csi_remove(struct platform_device *pdev)
  356. {
  357. struct bm_csi_drvdata *drvdata;
  358. drvdata = platform_get_drvdata(pdev);
  359. dw_csi_remove_capabilities_sysfs(pdev);
  360. //struct dw_csi *mipi_csi = &drvdata->csi_dev;
  361. //csi soc reset
  362. dw_csi_soc_reset();
  363. dev_info(&pdev->dev, "DW MIPI CSI-2 Host module removed\n");
  364. return 0;
  365. }
  366. MODULE_LICENSE("GPL v2");
  367. MODULE_AUTHOR("Luis Oliveira <luis.oliveira@synopsys.com>");
  368. MODULE_DESCRIPTION("Synopsys DesignWare MIPI CSI-2 Host Platform driver");