quark.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <init.h>
  8. #include <mmc.h>
  9. #include <asm/cache.h>
  10. #include <asm/io.h>
  11. #include <asm/ioapic.h>
  12. #include <asm/irq.h>
  13. #include <asm/mrccache.h>
  14. #include <asm/mtrr.h>
  15. #include <asm/pci.h>
  16. #include <asm/post.h>
  17. #include <asm/arch/device.h>
  18. #include <asm/arch/msg_port.h>
  19. #include <asm/arch/quark.h>
  20. #include <linux/delay.h>
  21. static void quark_setup_mtrr(void)
  22. {
  23. u32 base, mask;
  24. int i;
  25. disable_caches();
  26. /* mark the VGA RAM area as uncacheable */
  27. msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_A0000,
  28. MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
  29. msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_B0000,
  30. MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
  31. /* mark other fixed range areas as cacheable */
  32. msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_00000,
  33. MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
  34. msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_40000,
  35. MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
  36. msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_80000,
  37. MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
  38. msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_90000,
  39. MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
  40. for (i = MTRR_FIX_4K_C0000; i <= MTRR_FIX_4K_FC000; i++)
  41. msg_port_write(MSG_PORT_HOST_BRIDGE, i,
  42. MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
  43. /* variable range MTRR#0: ROM area */
  44. mask = ~(CONFIG_SYS_MONITOR_LEN - 1);
  45. base = CONFIG_SYS_TEXT_BASE & mask;
  46. msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ROM),
  47. base | MTRR_TYPE_WRBACK);
  48. msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ROM),
  49. mask | MTRR_PHYS_MASK_VALID);
  50. /* variable range MTRR#1: eSRAM area */
  51. mask = ~(ESRAM_SIZE - 1);
  52. base = CONFIG_ESRAM_BASE & mask;
  53. msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ESRAM),
  54. base | MTRR_TYPE_WRBACK);
  55. msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ESRAM),
  56. mask | MTRR_PHYS_MASK_VALID);
  57. /* enable both variable and fixed range MTRRs */
  58. msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_DEF_TYPE,
  59. MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN);
  60. enable_caches();
  61. }
  62. static void quark_setup_bars(void)
  63. {
  64. /* GPIO - D31:F0:R44h */
  65. qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA,
  66. CONFIG_GPIO_BASE | IO_BAR_EN);
  67. /* ACPI PM1 Block - D31:F0:R48h */
  68. qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK,
  69. CONFIG_ACPI_PM1_BASE | IO_BAR_EN);
  70. /* GPE0 - D31:F0:R4Ch */
  71. qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK,
  72. CONFIG_ACPI_GPE0_BASE | IO_BAR_EN);
  73. /* WDT - D31:F0:R84h */
  74. qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA,
  75. CONFIG_WDT_BASE | IO_BAR_EN);
  76. /* RCBA - D31:F0:RF0h */
  77. qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA,
  78. CONFIG_RCBA_BASE | MEM_BAR_EN);
  79. /* ACPI P Block - Msg Port 04:R70h */
  80. msg_port_write(MSG_PORT_RMU, PBLK_BA,
  81. CONFIG_ACPI_PBLK_BASE | IO_BAR_EN);
  82. /* SPI DMA - Msg Port 04:R7Ah */
  83. msg_port_write(MSG_PORT_RMU, SPI_DMA_BA,
  84. CONFIG_SPI_DMA_BASE | IO_BAR_EN);
  85. /* PCIe ECAM */
  86. msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL,
  87. CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
  88. msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG,
  89. CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
  90. }
  91. static void quark_pcie_early_init(void)
  92. {
  93. /*
  94. * Step1: Assert PCIe signal PERST#
  95. *
  96. * The CPU interface to the PERST# signal is platform dependent.
  97. * Call the board-specific codes to perform this task.
  98. */
  99. board_assert_perst();
  100. /* Step2: PHY common lane reset */
  101. msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_PHY_LANE_RST);
  102. /* wait 1 ms for PHY common lane reset */
  103. mdelay(1);
  104. /* Step3: PHY sideband interface reset and controller main reset */
  105. msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG,
  106. PCIE_PHY_SB_RST | PCIE_CTLR_MAIN_RST);
  107. /* wait 80ms for PLL to lock */
  108. mdelay(80);
  109. /* Step4: Controller sideband interface reset */
  110. msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_SB_RST);
  111. /* wait 20ms for controller sideband interface reset */
  112. mdelay(20);
  113. /* Step5: De-assert PERST# */
  114. board_deassert_perst();
  115. /* Step6: Controller primary interface reset */
  116. msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_PRI_RST);
  117. /* Mixer Load Lane 0 */
  118. msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L0,
  119. (1 << 6) | (1 << 7));
  120. /* Mixer Load Lane 1 */
  121. msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L1,
  122. (1 << 6) | (1 << 7));
  123. }
  124. static void quark_usb_early_init(void)
  125. {
  126. /* The sequence below comes from Quark firmware writer guide */
  127. msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_GLOBAL_PORT,
  128. 1 << 1, (1 << 6) | (1 << 7));
  129. msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_COMPBG,
  130. (1 << 8) | (1 << 9), (1 << 7) | (1 << 10));
  131. msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29);
  132. msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL1, 1 << 1);
  133. msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_PLL1,
  134. (1 << 3) | (1 << 4) | (1 << 5), 1 << 6);
  135. msg_port_alt_clrbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29);
  136. msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 24);
  137. }
  138. static void quark_thermal_early_init(void)
  139. {
  140. /* The sequence below comes from Quark firmware writer guide */
  141. /* thermal sensor mode config */
  142. msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1,
  143. (1 << 3) | (1 << 4) | (1 << 5), 1 << 5);
  144. msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1,
  145. (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) |
  146. (1 << 12), 1 << 9);
  147. msg_port_alt_setbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 14);
  148. msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 17);
  149. msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 18);
  150. msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG2, 0xffff, 0x011f);
  151. msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff, 0x17);
  152. msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3,
  153. (1 << 8) | (1 << 9), 1 << 8);
  154. msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff000000);
  155. msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG4,
  156. 0x7ff800, 0xc8 << 11);
  157. /* thermal monitor catastrophic trip set point (105 celsius) */
  158. msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff, 155);
  159. /* thermal monitor catastrophic trip clear point (0 celsius) */
  160. msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff0000, 50 << 16);
  161. /* take thermal sensor out of reset */
  162. msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG4, 1 << 0);
  163. /* enable thermal monitor */
  164. msg_port_setbits(MSG_PORT_RMU, TS_MODE, 1 << 15);
  165. /* lock all thermal configuration */
  166. msg_port_setbits(MSG_PORT_RMU, RMU_CTRL, (1 << 5) | (1 << 6));
  167. }
  168. static void quark_enable_legacy_seg(void)
  169. {
  170. msg_port_setbits(MSG_PORT_HOST_BRIDGE, HMISC2,
  171. HMISC2_SEGE | HMISC2_SEGF | HMISC2_SEGAB);
  172. }
  173. int arch_cpu_init(void)
  174. {
  175. int ret;
  176. post_code(POST_CPU_INIT);
  177. ret = x86_cpu_init_f();
  178. if (ret)
  179. return ret;
  180. /*
  181. * Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs
  182. * are accessed indirectly via the message port and not the traditional
  183. * MSR mechanism. Only UC, WT and WB cache types are supported.
  184. */
  185. quark_setup_mtrr();
  186. /*
  187. * Quark SoC has some non-standard BARs (excluding PCI standard BARs)
  188. * which need be initialized with suggested values
  189. */
  190. quark_setup_bars();
  191. /* Initialize USB2 PHY */
  192. quark_usb_early_init();
  193. /* Initialize thermal sensor */
  194. quark_thermal_early_init();
  195. /* Turn on legacy segments (A/B/E/F) decode to system RAM */
  196. quark_enable_legacy_seg();
  197. return 0;
  198. }
  199. int arch_cpu_init_dm(void)
  200. {
  201. /*
  202. * Initialize PCIe controller
  203. *
  204. * Quark SoC holds the PCIe controller in reset following a power on.
  205. * U-Boot needs to release the PCIe controller from reset. The PCIe
  206. * controller (D23:F0/F1) will not be visible in PCI configuration
  207. * space and any access to its PCI configuration registers will cause
  208. * system hang while it is held in reset.
  209. */
  210. quark_pcie_early_init();
  211. return 0;
  212. }
  213. int checkcpu(void)
  214. {
  215. return 0;
  216. }
  217. int print_cpuinfo(void)
  218. {
  219. post_code(POST_CPU_INFO);
  220. return default_print_cpuinfo();
  221. }
  222. static void quark_pcie_init(void)
  223. {
  224. u32 val;
  225. /* PCIe upstream non-posted & posted request size */
  226. qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_CCFG,
  227. CCFG_UPRS | CCFG_UNRS);
  228. qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_CCFG,
  229. CCFG_UPRS | CCFG_UNRS);
  230. /* PCIe packet fast transmit mode (IPF) */
  231. qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MPC2, MPC2_IPF);
  232. qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MPC2, MPC2_IPF);
  233. /* PCIe message bus idle counter (SBIC) */
  234. qrk_pci_read_config_dword(QUARK_PCIE0, PCIE_RP_MBC, &val);
  235. val |= MBC_SBIC;
  236. qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MBC, val);
  237. qrk_pci_read_config_dword(QUARK_PCIE1, PCIE_RP_MBC, &val);
  238. val |= MBC_SBIC;
  239. qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MBC, val);
  240. }
  241. static void quark_usb_init(void)
  242. {
  243. u32 bar;
  244. /* Change USB EHCI packet buffer OUT/IN threshold */
  245. qrk_pci_read_config_dword(QUARK_USB_EHCI, PCI_BASE_ADDRESS_0, &bar);
  246. writel((0x7f << 16) | 0x7f, bar + EHCI_INSNREG01);
  247. /* Disable USB device interrupts */
  248. qrk_pci_read_config_dword(QUARK_USB_DEVICE, PCI_BASE_ADDRESS_0, &bar);
  249. writel(0x7f, bar + USBD_INT_MASK);
  250. writel((0xf << 16) | 0xf, bar + USBD_EP_INT_MASK);
  251. writel((0xf << 16) | 0xf, bar + USBD_EP_INT_STS);
  252. }
  253. static void quark_irq_init(void)
  254. {
  255. struct quark_rcba *rcba;
  256. u32 base;
  257. qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
  258. base &= ~MEM_BAR_EN;
  259. rcba = (struct quark_rcba *)base;
  260. /*
  261. * Route Quark PCI device interrupt pin to PIRQ
  262. *
  263. * Route device#23's INTA/B/C/D to PIRQA/B/C/D
  264. * Route device#20,21's INTA/B/C/D to PIRQE/F/G/H
  265. */
  266. writew(PIRQC, &rcba->rmu_ir);
  267. writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12),
  268. &rcba->d23_ir);
  269. writew(PIRQD, &rcba->core_ir);
  270. writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12),
  271. &rcba->d20d21_ir);
  272. }
  273. int arch_early_init_r(void)
  274. {
  275. quark_pcie_init();
  276. quark_usb_init();
  277. quark_irq_init();
  278. return 0;
  279. }
  280. int arch_misc_init(void)
  281. {
  282. #ifdef CONFIG_ENABLE_MRC_CACHE
  283. /*
  284. * We intend not to check any return value here, as even MRC cache
  285. * is not saved successfully, it is not a severe error that will
  286. * prevent system from continuing to boot.
  287. */
  288. mrccache_save();
  289. #endif
  290. /* Assign a unique I/O APIC ID */
  291. io_apic_set_id(1);
  292. return 0;
  293. }
  294. void board_final_init(void)
  295. {
  296. struct quark_rcba *rcba;
  297. u32 base, val;
  298. qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
  299. base &= ~MEM_BAR_EN;
  300. rcba = (struct quark_rcba *)base;
  301. /* Initialize 'Component ID' to zero */
  302. val = readl(&rcba->esd);
  303. val &= ~0xff0000;
  304. writel(val, &rcba->esd);
  305. /* Lock HMBOUND for security */
  306. msg_port_setbits(MSG_PORT_HOST_BRIDGE, HM_BOUND, HM_BOUND_LOCK);
  307. return;
  308. }