Kconfig 2.8 KB

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  1. # SPDX-License-Identifier: GPL-2.0+
  2. #
  3. # Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
  4. config INTEL_QUARK
  5. bool
  6. select HAVE_RMU
  7. select ARCH_EARLY_INIT_R
  8. select ARCH_MISC_INIT
  9. imply ENABLE_MRC_CACHE
  10. imply ETH_DESIGNWARE
  11. imply ICH_SPI
  12. imply INTEL_ICH6_GPIO
  13. imply MMC
  14. imply MMC_PCI
  15. imply MMC_SDHCI
  16. imply MMC_SDHCI_SDMA
  17. imply SPI_FLASH
  18. imply SYS_NS16550
  19. imply USB
  20. imply USB_EHCI_HCD
  21. if INTEL_QUARK
  22. config HAVE_RMU
  23. bool "Add a Remote Management Unit (RMU) binary"
  24. help
  25. Select this option to add a Remote Management Unit (RMU) binary
  26. to the resulting U-Boot image. It is a data block (up to 64K) of
  27. machine-specific code which must be put in the flash for the RMU
  28. within the Quark SoC processor to access when powered up before
  29. system BIOS is executed.
  30. config RMU_FILE
  31. string "Remote Management Unit (RMU) binary filename"
  32. depends on HAVE_RMU
  33. default "rmu.bin"
  34. help
  35. The filename of the file to use as Remote Management Unit (RMU)
  36. binary in the board directory.
  37. config RMU_ADDR
  38. hex "Remote Management Unit (RMU) binary location"
  39. depends on HAVE_RMU
  40. default 0xfff00000
  41. help
  42. The location of the RMU binary is determined by a strap. It must be
  43. put in flash at a location matching the strap-determined base address.
  44. The default base address of 0xfff00000 indicates that the binary must
  45. be located at offset 0 from the beginning of a 1MB flash device.
  46. config HAVE_CMC
  47. bool
  48. default HAVE_RMU
  49. config CMC_FILE
  50. string
  51. depends on HAVE_CMC
  52. default RMU_FILE
  53. config CMC_ADDR
  54. hex
  55. depends on HAVE_CMC
  56. default RMU_ADDR
  57. config ESRAM_BASE
  58. hex
  59. default 0x80000000
  60. help
  61. Embedded SRAM (eSRAM) memory-mapped base address.
  62. config PCIE_ECAM_BASE
  63. hex
  64. default 0xe0000000
  65. config RCBA_BASE
  66. hex
  67. default 0xfed1c000
  68. help
  69. Root Complex register block memory-mapped base address.
  70. config ACPI_PM1_BASE
  71. hex
  72. default 0x1000
  73. help
  74. ACPI Power Management 1 (PM1) i/o-mapped base address.
  75. This device is defined in ACPI specification, with 16 bytes in size.
  76. config ACPI_PBLK_BASE
  77. hex
  78. default 0x1010
  79. help
  80. ACPI Processor Block (PBLK) i/o-mapped base address.
  81. This device is defined in ACPI specification, with 16 bytes in size.
  82. config SPI_DMA_BASE
  83. hex
  84. default 0x1020
  85. help
  86. SPI DMA i/o-mapped base address.
  87. config GPIO_BASE
  88. hex
  89. default 0x1080
  90. help
  91. GPIO i/o-mapped base address.
  92. config ACPI_GPE0_BASE
  93. hex
  94. default 0x1100
  95. help
  96. ACPI General Purpose Event 0 (GPE0) i/o-mapped base address.
  97. This device is defined in ACPI specification, with 64 bytes in size.
  98. config WDT_BASE
  99. hex
  100. default 0x1140
  101. help
  102. Watchdog timer i/o-mapped base address.
  103. config SYS_CAR_ADDR
  104. hex
  105. default ESRAM_BASE
  106. config SYS_CAR_SIZE
  107. hex
  108. default 0x8000
  109. help
  110. Space in bytes in eSRAM used as Cache-As-ARM (CAR).
  111. Note this size must not exceed eSRAM's total size.
  112. config X86_TSC_TIMER_EARLY_FREQ
  113. int
  114. default 400
  115. endif