irq.c 8.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <errno.h>
  8. #include <fdtdec.h>
  9. #include <irq.h>
  10. #include <log.h>
  11. #include <malloc.h>
  12. #include <asm/global_data.h>
  13. #include <asm/io.h>
  14. #include <asm/irq.h>
  15. #include <asm/pci.h>
  16. #include <asm/pirq_routing.h>
  17. #include <asm/tables.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. /**
  20. * pirq_reg_to_linkno() - Convert a PIRQ routing register offset to link number
  21. *
  22. * @priv: IRQ router driver's priv data
  23. * @reg: PIRQ routing register offset from the base address
  24. * @return: PIRQ link number (0 for PIRQA, 1 for PIRQB, etc)
  25. */
  26. static inline int pirq_reg_to_linkno(struct irq_router *priv, int reg)
  27. {
  28. int linkno = 0;
  29. if (priv->has_regmap) {
  30. struct pirq_regmap *map = priv->regmap;
  31. int i;
  32. for (i = 0; i < priv->link_num; i++) {
  33. if (reg - priv->link_base == map->offset) {
  34. linkno = map->link;
  35. break;
  36. }
  37. map++;
  38. }
  39. } else {
  40. linkno = reg - priv->link_base;
  41. }
  42. return linkno;
  43. }
  44. /**
  45. * pirq_linkno_to_reg() - Convert a PIRQ link number to routing register offset
  46. *
  47. * @priv: IRQ router driver's priv data
  48. * @linkno: PIRQ link number (0 for PIRQA, 1 for PIRQB, etc)
  49. * @return: PIRQ routing register offset from the base address
  50. */
  51. static inline int pirq_linkno_to_reg(struct irq_router *priv, int linkno)
  52. {
  53. int reg = 0;
  54. if (priv->has_regmap) {
  55. struct pirq_regmap *map = priv->regmap;
  56. int i;
  57. for (i = 0; i < priv->link_num; i++) {
  58. if (linkno == map->link) {
  59. reg = map->offset + priv->link_base;
  60. break;
  61. }
  62. map++;
  63. }
  64. } else {
  65. reg = linkno + priv->link_base;
  66. }
  67. return reg;
  68. }
  69. bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq)
  70. {
  71. struct irq_router *priv = dev_get_priv(dev);
  72. u8 pirq;
  73. if (priv->config == PIRQ_VIA_PCI)
  74. dm_pci_read_config8(dev->parent,
  75. pirq_linkno_to_reg(priv, link), &pirq);
  76. else
  77. pirq = readb((uintptr_t)priv->ibase +
  78. pirq_linkno_to_reg(priv, link));
  79. pirq &= 0xf;
  80. /* IRQ# 0/1/2/8/13 are reserved */
  81. if (pirq < 3 || pirq == 8 || pirq == 13)
  82. return false;
  83. return pirq == irq ? true : false;
  84. }
  85. int pirq_translate_link(struct udevice *dev, int link)
  86. {
  87. struct irq_router *priv = dev_get_priv(dev);
  88. return pirq_reg_to_linkno(priv, link);
  89. }
  90. void pirq_assign_irq(struct udevice *dev, int link, u8 irq)
  91. {
  92. struct irq_router *priv = dev_get_priv(dev);
  93. /* IRQ# 0/1/2/8/13 are reserved */
  94. if (irq < 3 || irq == 8 || irq == 13)
  95. return;
  96. if (priv->config == PIRQ_VIA_PCI)
  97. dm_pci_write_config8(dev->parent,
  98. pirq_linkno_to_reg(priv, link), irq);
  99. else
  100. writeb(irq, (uintptr_t)priv->ibase +
  101. pirq_linkno_to_reg(priv, link));
  102. }
  103. static struct irq_info *check_dup_entry(struct irq_info *slot_base,
  104. int entry_num, int bus, int device)
  105. {
  106. struct irq_info *slot = slot_base;
  107. int i;
  108. for (i = 0; i < entry_num; i++) {
  109. if (slot->bus == bus && slot->devfn == (device << 3))
  110. break;
  111. slot++;
  112. }
  113. return (i == entry_num) ? NULL : slot;
  114. }
  115. static inline void fill_irq_info(struct irq_router *priv, struct irq_info *slot,
  116. int bus, int device, int pin, int pirq)
  117. {
  118. slot->bus = bus;
  119. slot->devfn = (device << 3) | 0;
  120. slot->irq[pin - 1].link = pirq_linkno_to_reg(priv, pirq);
  121. slot->irq[pin - 1].bitmap = priv->irq_mask;
  122. }
  123. static int create_pirq_routing_table(struct udevice *dev)
  124. {
  125. struct irq_router *priv = dev_get_priv(dev);
  126. const void *blob = gd->fdt_blob;
  127. int node;
  128. int len, count;
  129. const u32 *cell;
  130. struct pirq_regmap *map;
  131. struct irq_routing_table *rt;
  132. struct irq_info *slot, *slot_base;
  133. int irq_entries = 0;
  134. int i;
  135. int ret;
  136. node = dev_of_offset(dev);
  137. /* extract the bdf from fdt_pci_addr */
  138. priv->bdf = dm_pci_get_bdf(dev->parent);
  139. ret = fdt_stringlist_search(blob, node, "intel,pirq-config", "pci");
  140. if (!ret) {
  141. priv->config = PIRQ_VIA_PCI;
  142. } else {
  143. ret = fdt_stringlist_search(blob, node, "intel,pirq-config",
  144. "ibase");
  145. if (!ret)
  146. priv->config = PIRQ_VIA_IBASE;
  147. else
  148. return -EINVAL;
  149. }
  150. cell = fdt_getprop(blob, node, "intel,pirq-link", &len);
  151. if (!cell || len != 8)
  152. return -EINVAL;
  153. priv->link_base = fdt_addr_to_cpu(cell[0]);
  154. priv->link_num = fdt_addr_to_cpu(cell[1]);
  155. if (priv->link_num > CONFIG_MAX_PIRQ_LINKS) {
  156. debug("Limiting supported PIRQ link number from %d to %d\n",
  157. priv->link_num, CONFIG_MAX_PIRQ_LINKS);
  158. priv->link_num = CONFIG_MAX_PIRQ_LINKS;
  159. }
  160. cell = fdt_getprop(blob, node, "intel,pirq-regmap", &len);
  161. if (cell) {
  162. if (len % sizeof(struct pirq_regmap))
  163. return -EINVAL;
  164. count = len / sizeof(struct pirq_regmap);
  165. if (count < priv->link_num) {
  166. printf("Number of pirq-regmap entires is wrong\n");
  167. return -EINVAL;
  168. }
  169. count = priv->link_num;
  170. priv->regmap = calloc(count, sizeof(struct pirq_regmap));
  171. if (!priv->regmap)
  172. return -ENOMEM;
  173. priv->has_regmap = true;
  174. map = priv->regmap;
  175. for (i = 0; i < count; i++) {
  176. map->link = fdt_addr_to_cpu(cell[0]);
  177. map->offset = fdt_addr_to_cpu(cell[1]);
  178. cell += sizeof(struct pirq_regmap) / sizeof(u32);
  179. map++;
  180. }
  181. }
  182. priv->irq_mask = fdtdec_get_int(blob, node,
  183. "intel,pirq-mask", PIRQ_BITMAP);
  184. if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) {
  185. /* Reserve IRQ9 for SCI */
  186. priv->irq_mask &= ~(1 << 9);
  187. }
  188. if (priv->config == PIRQ_VIA_IBASE) {
  189. int ibase_off;
  190. ibase_off = fdtdec_get_int(blob, node, "intel,ibase-offset", 0);
  191. if (!ibase_off)
  192. return -EINVAL;
  193. /*
  194. * Here we assume that the IBASE register has already been
  195. * properly configured by U-Boot before.
  196. *
  197. * By 'valid' we mean:
  198. * 1) a valid memory space carved within system memory space
  199. * assigned to IBASE register block.
  200. * 2) memory range decoding is enabled.
  201. * Hence we don't do any santify test here.
  202. */
  203. dm_pci_read_config32(dev->parent, ibase_off, &priv->ibase);
  204. priv->ibase &= ~0xf;
  205. }
  206. priv->actl_8bit = fdtdec_get_bool(blob, node, "intel,actl-8bit");
  207. priv->actl_addr = fdtdec_get_int(blob, node, "intel,actl-addr", 0);
  208. cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
  209. if (!cell || len % sizeof(struct pirq_routing))
  210. return -EINVAL;
  211. count = len / sizeof(struct pirq_routing);
  212. rt = calloc(1, sizeof(struct irq_routing_table));
  213. if (!rt)
  214. return -ENOMEM;
  215. /* Populate the PIRQ table fields */
  216. rt->signature = PIRQ_SIGNATURE;
  217. rt->version = PIRQ_VERSION;
  218. rt->rtr_bus = PCI_BUS(priv->bdf);
  219. rt->rtr_devfn = (PCI_DEV(priv->bdf) << 3) | PCI_FUNC(priv->bdf);
  220. rt->rtr_vendor = PCI_VENDOR_ID_INTEL;
  221. rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31;
  222. slot_base = rt->slots;
  223. /* Now fill in the irq_info entries in the PIRQ table */
  224. for (i = 0; i < count;
  225. i++, cell += sizeof(struct pirq_routing) / sizeof(u32)) {
  226. struct pirq_routing pr;
  227. pr.bdf = fdt_addr_to_cpu(cell[0]);
  228. pr.pin = fdt_addr_to_cpu(cell[1]);
  229. pr.pirq = fdt_addr_to_cpu(cell[2]);
  230. debug("irq_info %d: b.d.f %x.%x.%x INT%c PIRQ%c\n",
  231. i, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf),
  232. PCI_FUNC(pr.bdf), 'A' + pr.pin - 1,
  233. 'A' + pr.pirq);
  234. slot = check_dup_entry(slot_base, irq_entries,
  235. PCI_BUS(pr.bdf), PCI_DEV(pr.bdf));
  236. if (slot) {
  237. debug("found entry for bus %d device %d, ",
  238. PCI_BUS(pr.bdf), PCI_DEV(pr.bdf));
  239. if (slot->irq[pr.pin - 1].link) {
  240. debug("skipping\n");
  241. /*
  242. * Sanity test on the routed PIRQ pin
  243. *
  244. * If they don't match, show a warning to tell
  245. * there might be something wrong with the PIRQ
  246. * routing information in the device tree.
  247. */
  248. if (slot->irq[pr.pin - 1].link !=
  249. pirq_linkno_to_reg(priv, pr.pirq))
  250. debug("WARNING: Inconsistent PIRQ routing information\n");
  251. continue;
  252. }
  253. } else {
  254. slot = slot_base + irq_entries++;
  255. }
  256. debug("writing INT%c\n", 'A' + pr.pin - 1);
  257. fill_irq_info(priv, slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf),
  258. pr.pin, pr.pirq);
  259. }
  260. rt->size = irq_entries * sizeof(struct irq_info) + 32;
  261. /* Fix up the table checksum */
  262. rt->checksum = table_compute_checksum(rt, rt->size);
  263. gd->arch.pirq_routing_table = rt;
  264. return 0;
  265. }
  266. static void irq_enable_sci(struct udevice *dev)
  267. {
  268. struct irq_router *priv = dev_get_priv(dev);
  269. if (priv->actl_8bit) {
  270. /* Bit7 must be turned on to enable ACPI */
  271. dm_pci_write_config8(dev->parent, priv->actl_addr, 0x80);
  272. } else {
  273. /* Write 0 to enable SCI on IRQ9 */
  274. if (priv->config == PIRQ_VIA_PCI)
  275. dm_pci_write_config32(dev->parent, priv->actl_addr, 0);
  276. else
  277. writel(0, (uintptr_t)priv->ibase + priv->actl_addr);
  278. }
  279. }
  280. int irq_router_probe(struct udevice *dev)
  281. {
  282. int ret;
  283. ret = create_pirq_routing_table(dev);
  284. if (ret) {
  285. debug("Failed to create pirq routing table\n");
  286. return ret;
  287. }
  288. /* Route PIRQ */
  289. pirq_route_irqs(dev, gd->arch.pirq_routing_table->slots,
  290. get_irq_slot_count(gd->arch.pirq_routing_table));
  291. if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE))
  292. irq_enable_sci(dev);
  293. return 0;
  294. }
  295. static const struct udevice_id irq_router_ids[] = {
  296. { .compatible = "intel,irq-router", .data = X86_IRQT_BASE },
  297. { }
  298. };
  299. U_BOOT_DRIVER(irq_router_drv) = {
  300. .name = "intel_irq",
  301. .id = UCLASS_IRQ,
  302. .of_match = irq_router_ids,
  303. .probe = irq_router_probe,
  304. .priv_auto = sizeof(struct irq_router),
  305. };