Kconfig 33 KB

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  1. menu "x86 architecture"
  2. depends on X86
  3. config SYS_ARCH
  4. default "x86"
  5. choice
  6. prompt "Run U-Boot in 32/64-bit mode"
  7. default X86_RUN_32BIT
  8. help
  9. U-Boot can be built as a 32-bit binary which runs in 32-bit mode
  10. even on 64-bit machines. In this case SPL is not used, and U-Boot
  11. runs directly from the reset vector (via 16-bit start-up).
  12. Alternatively it can be run as a 64-bit binary, thus requiring a
  13. 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit
  14. start-up) then jumps to U-Boot in 64-bit mode.
  15. For now, 32-bit mode is recommended, as 64-bit is still
  16. experimental and is missing a lot of features.
  17. config X86_RUN_32BIT
  18. bool "32-bit"
  19. help
  20. Build U-Boot as a 32-bit binary with no SPL. This is the currently
  21. supported normal setup. U-Boot will stay in 32-bit mode even on
  22. 64-bit machines. When booting a 64-bit kernel, U-Boot will switch
  23. to 64-bit just before starting the kernel. Only the bottom 4GB of
  24. memory can be accessed through normal means, although
  25. arch_phys_memset() can be used for basic access to other memory.
  26. config X86_RUN_64BIT
  27. bool "64-bit"
  28. select X86_64
  29. select SPL
  30. select SPL_SEPARATE_BSS
  31. help
  32. Build U-Boot as a 64-bit binary with a 32-bit SPL. This is
  33. experimental and many features are missing. U-Boot SPL starts up,
  34. runs through the 16-bit and 32-bit init, then switches to 64-bit
  35. mode and jumps to U-Boot proper.
  36. endchoice
  37. config X86_64
  38. bool
  39. config SPL_X86_64
  40. bool
  41. depends on SPL
  42. choice
  43. prompt "Mainboard vendor"
  44. default VENDOR_EMULATION
  45. config VENDOR_ADVANTECH
  46. bool "advantech"
  47. config VENDOR_CONGATEC
  48. bool "congatec"
  49. config VENDOR_COREBOOT
  50. bool "coreboot"
  51. config VENDOR_DFI
  52. bool "dfi"
  53. config VENDOR_EFI
  54. bool "efi"
  55. config VENDOR_EMULATION
  56. bool "emulation"
  57. config VENDOR_GOOGLE
  58. bool "Google"
  59. config VENDOR_INTEL
  60. bool "Intel"
  61. endchoice
  62. # subarchitectures-specific options below
  63. config INTEL_MID
  64. bool "Intel MID platform support"
  65. select REGMAP
  66. select SYSCON
  67. help
  68. Select to build a U-Boot capable of supporting Intel MID
  69. (Mobile Internet Device) platform systems which do not have
  70. the PCI legacy interfaces.
  71. If you are building for a PC class system say N here.
  72. Intel MID platforms are based on an Intel processor and
  73. chipset which consume less power than most of the x86
  74. derivatives.
  75. # board-specific options below
  76. source "board/advantech/Kconfig"
  77. source "board/congatec/Kconfig"
  78. source "board/coreboot/Kconfig"
  79. source "board/dfi/Kconfig"
  80. source "board/efi/Kconfig"
  81. source "board/emulation/Kconfig"
  82. source "board/google/Kconfig"
  83. source "board/intel/Kconfig"
  84. # platform-specific options below
  85. source "arch/x86/cpu/apollolake/Kconfig"
  86. source "arch/x86/cpu/baytrail/Kconfig"
  87. source "arch/x86/cpu/braswell/Kconfig"
  88. source "arch/x86/cpu/broadwell/Kconfig"
  89. source "arch/x86/cpu/coreboot/Kconfig"
  90. source "arch/x86/cpu/ivybridge/Kconfig"
  91. source "arch/x86/cpu/efi/Kconfig"
  92. source "arch/x86/cpu/qemu/Kconfig"
  93. source "arch/x86/cpu/quark/Kconfig"
  94. source "arch/x86/cpu/queensbay/Kconfig"
  95. source "arch/x86/cpu/slimbootloader/Kconfig"
  96. source "arch/x86/cpu/tangier/Kconfig"
  97. # architecture-specific options below
  98. config AHCI
  99. default y
  100. config SYS_MALLOC_F_LEN
  101. default 0x800
  102. config RAMBASE
  103. hex
  104. default 0x100000
  105. config XIP_ROM_SIZE
  106. hex
  107. depends on X86_RESET_VECTOR
  108. default ROM_SIZE
  109. config CPU_ADDR_BITS
  110. int
  111. default 36
  112. config HPET_ADDRESS
  113. hex
  114. default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
  115. config SMM_TSEG
  116. bool
  117. default n
  118. config SMM_TSEG_SIZE
  119. hex
  120. config X86_RESET_VECTOR
  121. bool
  122. default n
  123. select BINMAN
  124. # The following options control where the 16-bit and 32-bit init lies
  125. # If SPL is enabled then it normally holds this init code, and U-Boot proper
  126. # is normally a 64-bit build.
  127. #
  128. # The 16-bit init refers to the reset vector and the small amount of code to
  129. # get the processor into 32-bit mode. It may be in SPL or in U-Boot proper,
  130. # or missing altogether if U-Boot is started from EFI or coreboot.
  131. #
  132. # The 32-bit init refers to processor init, running binary blobs including
  133. # FSP, setting up interrupts and anything else that needs to be done in
  134. # 32-bit code. It is normally in the same place as 16-bit init if that is
  135. # enabled (i.e. they are both in SPL, or both in U-Boot proper).
  136. config X86_16BIT_INIT
  137. bool
  138. depends on X86_RESET_VECTOR
  139. default y if X86_RESET_VECTOR && !SPL
  140. help
  141. This is enabled when 16-bit init is in U-Boot proper
  142. config SPL_X86_16BIT_INIT
  143. bool
  144. depends on X86_RESET_VECTOR
  145. default y if X86_RESET_VECTOR && SPL && !TPL
  146. help
  147. This is enabled when 16-bit init is in SPL
  148. config TPL_X86_16BIT_INIT
  149. bool
  150. depends on X86_RESET_VECTOR
  151. default y if X86_RESET_VECTOR && TPL
  152. help
  153. This is enabled when 16-bit init is in TPL
  154. config X86_32BIT_INIT
  155. bool
  156. depends on X86_RESET_VECTOR
  157. default y if X86_RESET_VECTOR && !SPL
  158. help
  159. This is enabled when 32-bit init is in U-Boot proper
  160. config SPL_X86_32BIT_INIT
  161. bool
  162. depends on X86_RESET_VECTOR
  163. default y if X86_RESET_VECTOR && SPL
  164. help
  165. This is enabled when 32-bit init is in SPL
  166. config USE_EARLY_BOARD_INIT
  167. bool
  168. config RESET_SEG_START
  169. hex
  170. depends on X86_RESET_VECTOR
  171. default 0xffff0000
  172. config RESET_VEC_LOC
  173. hex
  174. depends on X86_RESET_VECTOR
  175. default 0xfffffff0
  176. config SYS_X86_START16
  177. hex
  178. depends on X86_RESET_VECTOR
  179. default 0xfffff800
  180. config HAVE_X86_FIT
  181. bool
  182. help
  183. Enable inclusion of an Intel Firmware Interface Table (FIT) into the
  184. image. This table is supposed to point to microcode and the like. So
  185. far it is just a fixed table with the minimum set of headers, so that
  186. it is actually present.
  187. config X86_LOAD_FROM_32_BIT
  188. bool "Boot from a 32-bit program"
  189. help
  190. Define this to boot U-Boot from a 32-bit program which sets
  191. the GDT differently. This can be used to boot directly from
  192. any stage of coreboot, for example, bypassing the normal
  193. payload-loading feature.
  194. config BOARD_ROMSIZE_KB_512
  195. bool
  196. config BOARD_ROMSIZE_KB_1024
  197. bool
  198. config BOARD_ROMSIZE_KB_2048
  199. bool
  200. config BOARD_ROMSIZE_KB_4096
  201. bool
  202. config BOARD_ROMSIZE_KB_8192
  203. bool
  204. config BOARD_ROMSIZE_KB_16384
  205. bool
  206. choice
  207. prompt "ROM chip size"
  208. depends on X86_RESET_VECTOR
  209. default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
  210. default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
  211. default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
  212. default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
  213. default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
  214. default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
  215. help
  216. Select the size of the ROM chip you intend to flash U-Boot on.
  217. The build system will take care of creating a u-boot.rom file
  218. of the matching size.
  219. config UBOOT_ROMSIZE_KB_512
  220. bool "512 KB"
  221. help
  222. Choose this option if you have a 512 KB ROM chip.
  223. config UBOOT_ROMSIZE_KB_1024
  224. bool "1024 KB (1 MB)"
  225. help
  226. Choose this option if you have a 1024 KB (1 MB) ROM chip.
  227. config UBOOT_ROMSIZE_KB_2048
  228. bool "2048 KB (2 MB)"
  229. help
  230. Choose this option if you have a 2048 KB (2 MB) ROM chip.
  231. config UBOOT_ROMSIZE_KB_4096
  232. bool "4096 KB (4 MB)"
  233. help
  234. Choose this option if you have a 4096 KB (4 MB) ROM chip.
  235. config UBOOT_ROMSIZE_KB_8192
  236. bool "8192 KB (8 MB)"
  237. help
  238. Choose this option if you have a 8192 KB (8 MB) ROM chip.
  239. config UBOOT_ROMSIZE_KB_16384
  240. bool "16384 KB (16 MB)"
  241. help
  242. Choose this option if you have a 16384 KB (16 MB) ROM chip.
  243. endchoice
  244. # Map the config names to an integer (KB).
  245. config UBOOT_ROMSIZE_KB
  246. int
  247. default 512 if UBOOT_ROMSIZE_KB_512
  248. default 1024 if UBOOT_ROMSIZE_KB_1024
  249. default 2048 if UBOOT_ROMSIZE_KB_2048
  250. default 4096 if UBOOT_ROMSIZE_KB_4096
  251. default 8192 if UBOOT_ROMSIZE_KB_8192
  252. default 16384 if UBOOT_ROMSIZE_KB_16384
  253. # Map the config names to a hex value (bytes).
  254. config ROM_SIZE
  255. hex
  256. default 0x80000 if UBOOT_ROMSIZE_KB_512
  257. default 0x100000 if UBOOT_ROMSIZE_KB_1024
  258. default 0x200000 if UBOOT_ROMSIZE_KB_2048
  259. default 0x400000 if UBOOT_ROMSIZE_KB_4096
  260. default 0x800000 if UBOOT_ROMSIZE_KB_8192
  261. default 0xc00000 if UBOOT_ROMSIZE_KB_12288
  262. default 0x1000000 if UBOOT_ROMSIZE_KB_16384
  263. config HAVE_INTEL_ME
  264. bool "Platform requires Intel Management Engine"
  265. help
  266. Newer higher-end devices have an Intel Management Engine (ME)
  267. which is a very large binary blob (typically 1.5MB) which is
  268. required for the platform to work. This enforces a particular
  269. SPI flash format. You will need to supply the me.bin file in
  270. your board directory.
  271. config X86_RAMTEST
  272. bool "Perform a simple RAM test after SDRAM initialisation"
  273. help
  274. If there is something wrong with SDRAM then the platform will
  275. often crash within U-Boot or the kernel. This option enables a
  276. very simple RAM test that quickly checks whether the SDRAM seems
  277. to work correctly. It is not exhaustive but can save time by
  278. detecting obvious failures.
  279. config FLASH_DESCRIPTOR_FILE
  280. string "Flash descriptor binary filename"
  281. depends on HAVE_INTEL_ME || FSP_VERSION2
  282. default "descriptor.bin"
  283. help
  284. The filename of the file to use as flash descriptor in the
  285. board directory.
  286. config INTEL_ME_FILE
  287. string "Intel Management Engine binary filename"
  288. depends on HAVE_INTEL_ME
  289. default "me.bin"
  290. help
  291. The filename of the file to use as Intel Management Engine in the
  292. board directory.
  293. config USE_HOB
  294. bool "Use HOB (Hand-Off Block)"
  295. help
  296. Select this option to access HOB (Hand-Off Block) data structures
  297. and parse HOBs. This HOB infra structure can be reused with
  298. different solutions across different platforms.
  299. config HAVE_FSP
  300. bool "Add an Firmware Support Package binary"
  301. depends on !EFI
  302. select USE_HOB
  303. select HAS_ROM
  304. help
  305. Select this option to add an Firmware Support Package binary to
  306. the resulting U-Boot image. It is a binary blob which U-Boot uses
  307. to set up SDRAM and other chipset specific initialization.
  308. Note: Without this binary U-Boot will not be able to set up its
  309. SDRAM so will not boot.
  310. config USE_CAR
  311. bool "Use Cache-As-RAM (CAR) to get temporary RAM at start-up"
  312. default y if !HAVE_FSP
  313. help
  314. Select this option if your board uses CAR init code, typically in a
  315. car.S file, to get some initial memory for code execution. This is
  316. common with Intel CPUs which don't use FSP.
  317. choice
  318. prompt "FSP version"
  319. depends on HAVE_FSP
  320. default FSP_VERSION1
  321. help
  322. Selects the FSP version to use. Intel has published several versions
  323. of the FSP External Architecture Specification and this allows
  324. selection of the version number used by a particular SoC.
  325. config FSP_VERSION1
  326. bool "FSP version 1.x"
  327. help
  328. This covers versions 1.0 and 1.1a. See here for details:
  329. https://github.com/IntelFsp/fsp/wiki
  330. config FSP_VERSION2
  331. bool "FSP version 2.x"
  332. help
  333. This covers versions 2.0 and 2.1. See here for details:
  334. https://github.com/IntelFsp/fsp/wiki
  335. endchoice
  336. config FSP_FILE
  337. string "Firmware Support Package binary filename"
  338. depends on FSP_VERSION1
  339. default "fsp.bin"
  340. help
  341. The filename of the file to use as Firmware Support Package binary
  342. in the board directory.
  343. config FSP_ADDR
  344. hex "Firmware Support Package binary location"
  345. depends on FSP_VERSION1
  346. default 0xfffc0000
  347. help
  348. FSP is not Position Independent Code (PIC) and the whole FSP has to
  349. be rebased if it is placed at a location which is different from the
  350. perferred base address specified during the FSP build. Use Intel's
  351. Binary Configuration Tool (BCT) to do the rebase.
  352. The default base address of 0xfffc0000 indicates that the binary must
  353. be located at offset 0xc0000 from the beginning of a 1MB flash device.
  354. if FSP_VERSION2
  355. config FSP_FILE_T
  356. string "Firmware Support Package binary filename (Temp RAM)"
  357. default "fsp_t.bin"
  358. help
  359. The filename of the file to use for the temporary-RAM init phase from
  360. the Firmware Support Package binary. Put this in the board directory.
  361. It is used to set up an initial area of RAM which can be used for the
  362. stack and other purposes, while bringing up the main system DRAM.
  363. config FSP_ADDR_T
  364. hex "Firmware Support Package binary location (Temp RAM)"
  365. default 0xffff8000
  366. help
  367. FSP is not Position-Independent Code (PIC) and FSP components have to
  368. be rebased if placed at a location which is different from the
  369. perferred base address specified during the FSP build. Use Intel's
  370. Binary Configuration Tool (BCT) to do the rebase.
  371. config FSP_FILE_M
  372. string "Firmware Support Package binary filename (Memory Init)"
  373. default "fsp_m.bin"
  374. help
  375. The filename of the file to use for the RAM init phase from the
  376. Firmware Support Package binary. Put this in the board directory.
  377. It is used to set up the main system DRAM and runs in SPL, once
  378. temporary RAM (CAR) is working.
  379. config FSP_FILE_S
  380. string "Firmware Support Package binary filename (Silicon Init)"
  381. default "fsp_s.bin"
  382. help
  383. The filename of the file to use for the Silicon init phase from the
  384. Firmware Support Package binary. Put this in the board directory.
  385. It is used to set up the silicon to work correctly and must be
  386. executed after DRAM is running.
  387. config IFWI_INPUT_FILE
  388. string "Filename containing FIT (Firmware Interface Table) with IFWI"
  389. default "fitimage.bin"
  390. help
  391. The IFWI is obtained by running a tool on this file to extract the
  392. IFWI. Put this in the board directory. The IFWI contains U-Boot TPL,
  393. microcode and other internal items.
  394. endif
  395. config FSP_TEMP_RAM_ADDR
  396. hex
  397. depends on FSP_VERSION1
  398. default 0x2000000
  399. help
  400. Stack top address which is used in fsp_init() after DRAM is ready and
  401. CAR is disabled.
  402. config FSP_SYS_MALLOC_F_LEN
  403. hex
  404. depends on FSP_VERSION1
  405. default 0x100000
  406. help
  407. Additional size of malloc() pool before relocation.
  408. config FSP_USE_UPD
  409. bool
  410. depends on FSP_VERSION1
  411. default y
  412. help
  413. Most FSPs use UPD data region for some FSP customization. But there
  414. are still some FSPs that might not even have UPD. For such FSPs,
  415. override this to n in their platform Kconfig files.
  416. config FSP_BROKEN_HOB
  417. bool
  418. depends on FSP_VERSION1
  419. help
  420. Indicate some buggy FSPs that does not report memory used by FSP
  421. itself as reserved in the resource descriptor HOB. Select this to
  422. tell U-Boot to do some additional work to ensure U-Boot relocation
  423. do not overwrite the important boot service data which is used by
  424. FSP, otherwise the subsequent call to fsp_notify() will fail.
  425. config ENABLE_MRC_CACHE
  426. bool "Enable MRC cache"
  427. depends on !EFI && !SYS_COREBOOT
  428. help
  429. Enable this feature to cause MRC data to be cached in NV storage
  430. to be used for speeding up boot time on future reboots and/or
  431. power cycles.
  432. For platforms that use Intel FSP for the memory initialization,
  433. please check FSP output HOB via U-Boot command 'fsp hob' to see
  434. if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp1/fsp_hob.h).
  435. If such GUID does not exist, MRC cache is not available on such
  436. platform (eg: Intel Queensbay), which means selecting this option
  437. here does not make any difference.
  438. config HAVE_MRC
  439. bool "Add a System Agent binary"
  440. select HAS_ROM
  441. depends on !HAVE_FSP
  442. help
  443. Select this option to add a System Agent binary to
  444. the resulting U-Boot image. MRC stands for Memory Reference Code.
  445. It is a binary blob which U-Boot uses to set up SDRAM.
  446. Note: Without this binary U-Boot will not be able to set up its
  447. SDRAM so will not boot.
  448. config CACHE_MRC_BIN
  449. bool
  450. depends on HAVE_MRC
  451. default n
  452. help
  453. Enable caching for the memory reference code binary. This uses an
  454. MTRR (memory type range register) to turn on caching for the section
  455. of SPI flash that contains the memory reference code. This makes
  456. SDRAM init run faster.
  457. config CACHE_MRC_SIZE_KB
  458. int
  459. depends on HAVE_MRC
  460. default 512
  461. help
  462. Sets the size of the cached area for the memory reference code.
  463. This ends at the end of SPI flash (address 0xffffffff) and is
  464. measured in KB. Typically this is set to 512, providing for 0.5MB
  465. of cached space.
  466. config DCACHE_RAM_BASE
  467. hex
  468. depends on HAVE_MRC
  469. help
  470. Sets the base of the data cache area in memory space. This is the
  471. start address of the cache-as-RAM (CAR) area and the address varies
  472. depending on the CPU. Once CAR is set up, read/write memory becomes
  473. available at this address and can be used temporarily until SDRAM
  474. is working.
  475. config DCACHE_RAM_SIZE
  476. hex
  477. depends on HAVE_MRC
  478. default 0x40000
  479. help
  480. Sets the total size of the data cache area in memory space. This
  481. sets the size of the cache-as-RAM (CAR) area. Note that much of the
  482. CAR space is required by the MRC. The CAR space available to U-Boot
  483. is normally at the start and typically extends to 1/4 or 1/2 of the
  484. available size.
  485. config DCACHE_RAM_MRC_VAR_SIZE
  486. hex
  487. depends on HAVE_MRC
  488. help
  489. This is the amount of CAR (Cache as RAM) reserved for use by the
  490. memory reference code. This depends on the implementation of the
  491. memory reference code and must be set correctly or the board will
  492. not boot.
  493. config HAVE_REFCODE
  494. bool "Add a Reference Code binary"
  495. help
  496. Select this option to add a Reference Code binary to the resulting
  497. U-Boot image. This is an Intel binary blob that handles system
  498. initialisation, in this case the PCH and System Agent.
  499. Note: Without this binary (on platforms that need it such as
  500. broadwell) U-Boot will be missing some critical setup steps.
  501. Various peripherals may fail to work.
  502. config HAVE_MICROCODE
  503. bool "Board requires a microcode binary"
  504. default y if !FSP_VERSION2
  505. help
  506. Enable this if the board requires microcode to be loaded on boot.
  507. Typically this is handed by the FSP for modern boards, but for
  508. some older boards, it must be programmed by U-Boot, and that form
  509. part of the image.
  510. config SMP
  511. bool "Enable Symmetric Multiprocessing"
  512. default n
  513. help
  514. Enable use of more than one CPU in U-Boot and the Operating System
  515. when loaded. Each CPU will be started up and information can be
  516. obtained using the 'cpu' command. If this option is disabled, then
  517. only one CPU will be enabled regardless of the number of CPUs
  518. available.
  519. config SMP_AP_WORK
  520. bool
  521. depends on SMP
  522. help
  523. Allow APs to do other work after initialisation instead of going
  524. to sleep.
  525. config MAX_CPUS
  526. int "Maximum number of CPUs permitted"
  527. depends on SMP
  528. default 4
  529. help
  530. When using multi-CPU chips it is possible for U-Boot to start up
  531. more than one CPU. The stack memory used by all of these CPUs is
  532. pre-allocated so at present U-Boot wants to know the maximum
  533. number of CPUs that may be present. Set this to at least as high
  534. as the number of CPUs in your system (it uses about 4KB of RAM for
  535. each CPU).
  536. config AP_STACK_SIZE
  537. hex
  538. depends on SMP
  539. default 0x1000
  540. help
  541. Each additional CPU started by U-Boot requires its own stack. This
  542. option sets the stack size used by each CPU and directly affects
  543. the memory used by this initialisation process. Typically 4KB is
  544. enough space.
  545. config CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
  546. bool
  547. help
  548. This option indicates that the turbo mode setting is not package
  549. scoped. i.e. turbo_enable() needs to be called on not just the
  550. bootstrap processor (BSP).
  551. config HAVE_VGA_BIOS
  552. bool "Add a VGA BIOS image"
  553. help
  554. Select this option if you have a VGA BIOS image that you would
  555. like to add to your ROM.
  556. config VGA_BIOS_FILE
  557. string "VGA BIOS image filename"
  558. depends on HAVE_VGA_BIOS
  559. default "vga.bin"
  560. help
  561. The filename of the VGA BIOS image in the board directory.
  562. config VGA_BIOS_ADDR
  563. hex "VGA BIOS image location"
  564. depends on HAVE_VGA_BIOS
  565. default 0xfff90000
  566. help
  567. The location of VGA BIOS image in the SPI flash. For example, base
  568. address of 0xfff90000 indicates that the image will be put at offset
  569. 0x90000 from the beginning of a 1MB flash device.
  570. config HAVE_VBT
  571. bool "Add a Video BIOS Table (VBT) image"
  572. depends on HAVE_FSP
  573. help
  574. Select this option if you have a Video BIOS Table (VBT) image that
  575. you would like to add to your ROM. This is normally required if you
  576. are using an Intel FSP firmware that is complaint with spec 1.1 or
  577. later to initialize the integrated graphics device (IGD).
  578. Video BIOS Table, or VBT, provides platform and board specific
  579. configuration information to the driver that is not discoverable
  580. or available through other means. By other means the most used
  581. method here is to read EDID table from the attached monitor, over
  582. Display Data Channel (DDC) using two pin I2C serial interface. VBT
  583. configuration is related to display hardware and is available via
  584. the ACPI OpRegion or, on older systems, in the PCI ROM (Option ROM).
  585. config VBT_FILE
  586. string "Video BIOS Table (VBT) image filename"
  587. depends on HAVE_VBT
  588. default "vbt.bin"
  589. help
  590. The filename of the file to use as Video BIOS Table (VBT) image
  591. in the board directory.
  592. config VBT_ADDR
  593. hex "Video BIOS Table (VBT) image location"
  594. depends on HAVE_VBT
  595. default 0xfff90000
  596. help
  597. The location of Video BIOS Table (VBT) image in the SPI flash. For
  598. example, base address of 0xfff90000 indicates that the image will
  599. be put at offset 0x90000 from the beginning of a 1MB flash device.
  600. config VIDEO_FSP
  601. bool "Enable FSP framebuffer driver support"
  602. depends on HAVE_VBT && DM_VIDEO
  603. help
  604. Turn on this option to enable a framebuffer driver when U-Boot is
  605. using Video BIOS Table (VBT) image for FSP firmware to initialize
  606. the integrated graphics device.
  607. config ROM_TABLE_ADDR
  608. hex
  609. default 0xf0000
  610. help
  611. All x86 tables happen to like the address range from 0x0f0000
  612. to 0x100000. We use 0xf0000 as the starting address to store
  613. those tables, including PIRQ routing table, Multi-Processor
  614. table and ACPI table.
  615. config ROM_TABLE_SIZE
  616. hex
  617. default 0x10000
  618. config HAVE_ITSS
  619. bool "Enable ITSS"
  620. help
  621. Select this to include the driver for the Interrupt Timer
  622. Subsystem (ITSS) which is found on several Intel devices.
  623. config HAVE_P2SB
  624. bool "Enable P2SB"
  625. depends on P2SB
  626. help
  627. Select this to include the driver for the Primary to
  628. Sideband Bridge (P2SB) which is found on several Intel
  629. devices.
  630. menu "System tables"
  631. depends on !EFI && !SYS_COREBOOT
  632. config GENERATE_PIRQ_TABLE
  633. bool "Generate a PIRQ table"
  634. default n
  635. help
  636. Generate a PIRQ routing table for this board. The PIRQ routing table
  637. is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
  638. at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
  639. It specifies the interrupt router information as well how all the PCI
  640. devices' interrupt pins are wired to PIRQs.
  641. config GENERATE_SFI_TABLE
  642. bool "Generate a SFI (Simple Firmware Interface) table"
  643. help
  644. The Simple Firmware Interface (SFI) provides a lightweight method
  645. for platform firmware to pass information to the operating system
  646. via static tables in memory. Kernel SFI support is required to
  647. boot on SFI-only platforms. If you have ACPI tables then these are
  648. used instead.
  649. U-Boot writes this table in write_sfi_table() just before booting
  650. the OS.
  651. For more information, see http://simplefirmware.org
  652. config GENERATE_MP_TABLE
  653. bool "Generate an MP (Multi-Processor) table"
  654. default n
  655. help
  656. Generate an MP (Multi-Processor) table for this board. The MP table
  657. provides a way for the operating system to support for symmetric
  658. multiprocessing as well as symmetric I/O interrupt handling with
  659. the local APIC and I/O APIC.
  660. config GENERATE_ACPI_TABLE
  661. bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
  662. default n
  663. select QFW if QEMU
  664. help
  665. The Advanced Configuration and Power Interface (ACPI) specification
  666. provides an open standard for device configuration and management
  667. by the operating system. It defines platform-independent interfaces
  668. for configuration and power management monitoring.
  669. config ACPI_GNVS_EXTERNAL
  670. bool
  671. help
  672. Put the GNVS (Global Non-Volatile Sleeping) table separate from the
  673. DSDT and add a pointer to the table from the DSDT. This allows
  674. U-Boot to better control the address of the GNVS.
  675. endmenu
  676. config HAVE_ACPI_RESUME
  677. bool "Enable ACPI S3 resume"
  678. select ENABLE_MRC_CACHE
  679. help
  680. Select this to enable ACPI S3 resume. S3 is an ACPI-defined sleeping
  681. state where all system context is lost except system memory. U-Boot
  682. is responsible for restoring the machine state as it was before sleep.
  683. It needs restore the memory controller, without overwriting memory
  684. which is not marked as reserved. For the peripherals which lose their
  685. registers, U-Boot needs to write the original value. When everything
  686. is done, U-Boot needs to find out the wakeup vector provided by OSes
  687. and jump there.
  688. config S3_VGA_ROM_RUN
  689. bool "Re-run VGA option ROMs on S3 resume"
  690. depends on HAVE_ACPI_RESUME
  691. help
  692. Execute VGA option ROMs in U-Boot when resuming from S3. Normally
  693. this is needed when graphics console is being used in the kernel.
  694. Turning it off can reduce some resume time, but be aware that your
  695. graphics console won't work without VGA options ROMs. Set it to N
  696. if your kernel is only on a serial console.
  697. config STACK_SIZE_RESUME
  698. hex
  699. depends on HAVE_ACPI_RESUME
  700. default 0x1000
  701. help
  702. Estimated U-Boot's runtime stack size that needs to be reserved
  703. during an ACPI S3 resume.
  704. config MAX_PIRQ_LINKS
  705. int
  706. default 8
  707. help
  708. This variable specifies the number of PIRQ interrupt links which are
  709. routable. On most older chipsets, this is 4, PIRQA through PIRQD.
  710. Some newer chipsets offer more than four links, commonly up to PIRQH.
  711. config IRQ_SLOT_COUNT
  712. int
  713. default 128
  714. help
  715. U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
  716. which in turns forms a table of exact 4KiB. The default value 128
  717. should be enough for most boards. If this does not fit your board,
  718. change it according to your needs.
  719. config PCIE_ECAM_BASE
  720. hex
  721. default 0xe0000000
  722. help
  723. This is the memory-mapped address of PCI configuration space, which
  724. is only available through the Enhanced Configuration Access
  725. Mechanism (ECAM) with PCI Express. It can be set up almost
  726. anywhere. Before it is set up, it is possible to access PCI
  727. configuration space through I/O access, but memory access is more
  728. convenient. Using this, PCI can be scanned and configured. This
  729. should be set to a region that does not conflict with memory
  730. assigned to PCI devices - i.e. the memory and prefetch regions, as
  731. passed to pci_set_region().
  732. config PCIE_ECAM_SIZE
  733. hex
  734. default 0x10000000
  735. help
  736. This is the size of memory-mapped address of PCI configuration space,
  737. which is only available through the Enhanced Configuration Access
  738. Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
  739. so a default 0x10000000 size covers all of the 256 buses which is the
  740. maximum number of PCI buses as defined by the PCI specification.
  741. config I8259_PIC
  742. bool "Enable Intel 8259 compatible interrupt controller"
  743. default y
  744. help
  745. Intel 8259 ISA compatible chipset incorporates two 8259 (master and
  746. slave) interrupt controllers. Include this to have U-Boot set up
  747. the interrupt correctly.
  748. config APIC
  749. bool "Enable Intel Advanced Programmable Interrupt Controller"
  750. default y
  751. help
  752. The (A)dvanced (P)rogrammable (I)nterrupt (C)ontroller is responsible
  753. for catching interrupts and distributing them to one or more CPU
  754. cores. In most cases there are some LAPICs (local) for each core and
  755. one I/O APIC. This conjunction is found on most modern x86 systems.
  756. config PINCTRL_ICH6
  757. bool
  758. help
  759. Intel ICH6 compatible chipset pinctrl driver. It needs to work
  760. together with the ICH6 compatible gpio driver.
  761. config I8254_TIMER
  762. bool
  763. default y
  764. help
  765. Intel 8254 timer contains three counters which have fixed uses.
  766. Include this to have U-Boot set up the timer correctly.
  767. config SEABIOS
  768. bool "Support booting SeaBIOS"
  769. help
  770. SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
  771. It can run in an emulator or natively on X86 hardware with the use
  772. of coreboot/U-Boot. By turning on this option, U-Boot prepares
  773. all the configuration tables that are necessary to boot SeaBIOS.
  774. Check http://www.seabios.org/SeaBIOS for details.
  775. config HIGH_TABLE_SIZE
  776. hex "Size of configuration tables which reside in high memory"
  777. default 0x10000
  778. depends on SEABIOS
  779. help
  780. SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
  781. configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
  782. puts a copy of configuration tables in high memory region which
  783. is reserved on the stack before relocation. The region size is
  784. determined by this option.
  785. Increse it if the default size does not fit the board's needs.
  786. This is most likely due to a large ACPI DSDT table is used.
  787. config INTEL_CAR_CQOS
  788. bool "Support Intel Cache Quality of Service"
  789. help
  790. Cache Quality of Service allows more fine-grained control of cache
  791. usage. As result, it is possible to set up a portion of L2 cache for
  792. CAR and use the remainder for actual caching.
  793. #
  794. # Each bit in QOS mask controls this many bytes. This is calculated as:
  795. # (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS
  796. #
  797. config CACHE_QOS_SIZE_PER_BIT
  798. hex
  799. depends on INTEL_CAR_CQOS
  800. default 0x20000 # 128 KB
  801. config X86_OFFSET_U_BOOT
  802. hex "Offset of U-Boot in ROM image"
  803. depends on HAVE_SYS_TEXT_BASE
  804. default SYS_TEXT_BASE
  805. config X86_OFFSET_SPL
  806. hex "Offset of SPL in ROM image"
  807. depends on SPL && X86
  808. default SPL_TEXT_BASE
  809. config ACPI_GPE
  810. bool "Support ACPI general-purpose events"
  811. help
  812. Enable a driver for ACPI GPEs to allow peripherals to send interrupts
  813. via ACPI to the OS. In U-Boot this is only used when U-Boot itself
  814. needs access to these interrupts. This can happen when it uses a
  815. peripheral that is set up to use GPEs and so cannot use the normal
  816. GPIO mechanism for polling an input.
  817. See https://queue.acm.org/blogposting.cfm?id=18977 for more info
  818. config SPL_ACPI_GPE
  819. bool "Support ACPI general-purpose events in SPL"
  820. help
  821. Enable a driver for ACPI GPEs to allow peripherals to send interrupts
  822. via ACPI to the OS. In U-Boot this is only used when U-Boot itself
  823. needs access to these interrupts. This can happen when it uses a
  824. peripheral that is set up to use GPEs and so cannot use the normal
  825. GPIO mechanism for polling an input.
  826. See https://queue.acm.org/blogposting.cfm?id=18977 for more info
  827. config TPL_ACPI_GPE
  828. bool "Support ACPI general-purpose events in TPL"
  829. help
  830. Enable a driver for ACPI GPEs to allow peripherals to send interrupts
  831. via ACPI to the OS. In U-Boot this is only used when U-Boot itself
  832. needs access to these interrupts. This can happen when it uses a
  833. peripheral that is set up to use GPEs and so cannot use the normal
  834. GPIO mechanism for polling an input.
  835. See https://queue.acm.org/blogposting.cfm?id=18977 for more info
  836. config SA_PCIEX_LENGTH
  837. hex
  838. default 0x10000000 if (PCIEX_LENGTH_256MB)
  839. default 0x8000000 if (PCIEX_LENGTH_128MB)
  840. default 0x4000000 if (PCIEX_LENGTH_64MB)
  841. default 0x10000000
  842. help
  843. This option allows you to select length of PCIEX region.
  844. config PCIEX_LENGTH_256MB
  845. bool
  846. config PCIEX_LENGTH_128MB
  847. bool
  848. config PCIEX_LENGTH_64MB
  849. bool
  850. config INTEL_SOC
  851. bool
  852. help
  853. This is enabled on Intel SoCs that can support various advanced
  854. features such as power management (requiring asm/arch/pm.h), system
  855. agent (asm/arch/systemagent.h) and an I/O map for ACPI
  856. (asm/arch/iomap.h).
  857. This cannot be selected in a defconfig file. It must be enabled by a
  858. 'select' in the SoC's Kconfig.
  859. if INTEL_SOC
  860. config INTEL_ACPIGEN
  861. bool "Support ACPI table generation for Intel SoCs"
  862. depends on ACPIGEN
  863. help
  864. This option adds some functions used for programmatic generation of
  865. ACPI tables on Intel SoCs. This provides features for writing CPU
  866. information such as P states and T stages. Also included is a way
  867. to create a GNVS table and set it up.
  868. config INTEL_GMA_ACPI
  869. bool "Generate ACPI table for Intel GMA graphics"
  870. help
  871. The Intel GMA graphics driver in Linux expects an ACPI table
  872. which describes the layout of the registers and the display
  873. connected to the device. Enable this option to create this
  874. table so that graphics works correctly.
  875. config INTEL_GENERIC_WIFI
  876. bool "Enable generation of ACPI tables for Intel WiFi"
  877. help
  878. Select this option to provide code to a build generic WiFi ACPI table
  879. for Intel WiFi devices. This is not a WiFi driver and offers no
  880. network functionality. It is only here to generate the ACPI tables
  881. required by Linux.
  882. config INTEL_GMA_SWSMISCI
  883. bool
  884. help
  885. Select this option for Atom-based platforms which use the SWSMISCI
  886. register (0xe0) rather than the SWSCI register (0xe8).
  887. endif # INTEL_SOC
  888. config COREBOOT_SYSINFO
  889. bool "Support reading coreboot sysinfo"
  890. default y if SYS_COREBOOT
  891. help
  892. Select this option to read the coreboot sysinfo table on start-up,
  893. if present. This is written by coreboot before it exits and provides
  894. various pieces of information about the running system, including
  895. display, memory and build information. It is stored in
  896. struct sysinfo_t after parsing by get_coreboot_info().
  897. config SPL_COREBOOT_SYSINFO
  898. bool "Support reading coreboot sysinfo"
  899. depends on SPL
  900. default y if COREBOOT_SYSINFO
  901. help
  902. Select this option to read the coreboot sysinfo table in SPL,
  903. if present. This is written by coreboot before it exits and provides
  904. various pieces of information about the running system, including
  905. display, memory and build information. It is stored in
  906. struct sysinfo_t after parsing by get_coreboot_info().
  907. endmenu