test.dts 27 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476
  1. /dts-v1/;
  2. #include <dt-bindings/gpio/gpio.h>
  3. #include <dt-bindings/gpio/sandbox-gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. #include <dt-bindings/pinctrl/sandbox-pinmux.h>
  6. #include <dt-bindings/mux/mux.h>
  7. / {
  8. model = "sandbox";
  9. compatible = "sandbox";
  10. #address-cells = <1>;
  11. #size-cells = <1>;
  12. aliases {
  13. console = &uart0;
  14. eth0 = "/eth@10002000";
  15. eth2 = &swp_0;
  16. eth3 = &eth_3;
  17. eth4 = &dsa_eth0;
  18. eth5 = &eth_5;
  19. gpio1 = &gpio_a;
  20. gpio2 = &gpio_b;
  21. gpio3 = &gpio_c;
  22. i2c0 = "/i2c@0";
  23. mmc0 = "/mmc0";
  24. mmc1 = "/mmc1";
  25. pci0 = &pci0;
  26. pci1 = &pci1;
  27. pci2 = &pci2;
  28. remoteproc0 = &rproc_1;
  29. remoteproc1 = &rproc_2;
  30. rtc0 = &rtc_0;
  31. rtc1 = &rtc_1;
  32. spi0 = "/spi@0";
  33. testfdt6 = "/e-test";
  34. testbus3 = "/some-bus";
  35. testfdt0 = "/some-bus/c-test@0";
  36. testfdt12 = "/some-bus/c-test@1";
  37. testfdt3 = "/b-test";
  38. testfdt5 = "/some-bus/c-test@5";
  39. testfdt8 = "/a-test";
  40. testfdtm1 = &testfdtm1;
  41. fdt-dummy0 = "/translation-test@8000/dev@0,0";
  42. fdt-dummy1 = "/translation-test@8000/dev@1,100";
  43. fdt-dummy2 = "/translation-test@8000/dev@2,200";
  44. fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
  45. fdt-dummy4 = "/translation-test@8000/xlatebus@4,400/devs/dev@19";
  46. usb0 = &usb_0;
  47. usb1 = &usb_1;
  48. usb2 = &usb_2;
  49. axi0 = &axi;
  50. osd0 = "/osd";
  51. };
  52. audio: audio-codec {
  53. compatible = "sandbox,audio-codec";
  54. #sound-dai-cells = <1>;
  55. };
  56. buttons {
  57. compatible = "gpio-keys";
  58. btn1 {
  59. gpios = <&gpio_a 3 0>;
  60. label = "button1";
  61. };
  62. btn2 {
  63. gpios = <&gpio_a 4 0>;
  64. label = "button2";
  65. };
  66. };
  67. buttons2 {
  68. compatible = "adc-keys";
  69. io-channels = <&adc 3>;
  70. keyup-threshold-microvolt = <3000000>;
  71. button-up {
  72. label = "button3";
  73. linux,code = <KEY_F3>;
  74. press-threshold-microvolt = <1500000>;
  75. };
  76. button-down {
  77. label = "button4";
  78. linux,code = <KEY_F4>;
  79. press-threshold-microvolt = <1000000>;
  80. };
  81. button-enter {
  82. label = "button5";
  83. linux,code = <KEY_F5>;
  84. press-threshold-microvolt = <500000>;
  85. };
  86. };
  87. cros_ec: cros-ec {
  88. reg = <0 0>;
  89. compatible = "google,cros-ec-sandbox";
  90. /*
  91. * This describes the flash memory within the EC. Note
  92. * that the STM32L flash erases to 0, not 0xff.
  93. */
  94. flash {
  95. image-pos = <0x08000000>;
  96. size = <0x20000>;
  97. erase-value = <0>;
  98. /* Information for sandbox */
  99. ro {
  100. image-pos = <0>;
  101. size = <0xf000>;
  102. };
  103. wp-ro {
  104. image-pos = <0xf000>;
  105. size = <0x1000>;
  106. used = <0x884>;
  107. compress = "lz4";
  108. uncomp-size = <0xcf8>;
  109. hash {
  110. algo = "sha256";
  111. value = [00 01 02 03 04 05 06 07
  112. 08 09 0a 0b 0c 0d 0e 0f
  113. 10 11 12 13 14 15 16 17
  114. 18 19 1a 1b 1c 1d 1e 1f];
  115. };
  116. };
  117. rw {
  118. image-pos = <0x10000>;
  119. size = <0x10000>;
  120. };
  121. };
  122. };
  123. dsi_host: dsi_host {
  124. compatible = "sandbox,dsi-host";
  125. };
  126. a-test {
  127. reg = <0 1>;
  128. compatible = "denx,u-boot-fdt-test";
  129. ping-expect = <0>;
  130. ping-add = <0>;
  131. u-boot,dm-pre-reloc;
  132. test-gpios = <&gpio_a 1>, <&gpio_a 4>,
  133. <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
  134. <0>, <&gpio_a 12>;
  135. test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
  136. <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
  137. <&gpio_b 7 GPIO_IN 3 2 1>,
  138. <&gpio_b 8 GPIO_OUT 3 2 1>,
  139. <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
  140. test3-gpios =
  141. <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
  142. <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
  143. <&gpio_c 2 GPIO_OUT>,
  144. <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
  145. <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
  146. <&gpio_c 5 GPIO_IN>,
  147. <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
  148. <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
  149. test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
  150. test5-gpios = <&gpio_a 19>;
  151. int-value = <1234>;
  152. uint-value = <(-1234)>;
  153. int64-value = /bits/ 64 <0x1111222233334444>;
  154. int-array = <5678 9123 4567>;
  155. str-value = "test string";
  156. interrupts-extended = <&irq 3 0>;
  157. acpi,name = "GHIJ";
  158. phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
  159. mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
  160. <&muxcontroller0 2>, <&muxcontroller0 3>,
  161. <&muxcontroller1>;
  162. mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
  163. mux-syscon = <&syscon3>;
  164. display-timings {
  165. timing0: 240x320 {
  166. clock-frequency = <6500000>;
  167. hactive = <240>;
  168. vactive = <320>;
  169. hfront-porch = <6>;
  170. hback-porch = <7>;
  171. hsync-len = <1>;
  172. vback-porch = <5>;
  173. vfront-porch = <8>;
  174. vsync-len = <2>;
  175. hsync-active = <1>;
  176. vsync-active = <0>;
  177. de-active = <1>;
  178. pixelclk-active = <1>;
  179. interlaced;
  180. doublescan;
  181. doubleclk;
  182. };
  183. timing1: 480x800 {
  184. clock-frequency = <9000000>;
  185. hactive = <480>;
  186. vactive = <800>;
  187. hfront-porch = <10>;
  188. hback-porch = <59>;
  189. hsync-len = <12>;
  190. vback-porch = <15>;
  191. vfront-porch = <17>;
  192. vsync-len = <16>;
  193. hsync-active = <0>;
  194. vsync-active = <1>;
  195. de-active = <0>;
  196. pixelclk-active = <0>;
  197. };
  198. timing2: 800x480 {
  199. clock-frequency = <33500000>;
  200. hactive = <800>;
  201. vactive = <480>;
  202. hback-porch = <89>;
  203. hfront-porch = <164>;
  204. vback-porch = <23>;
  205. vfront-porch = <10>;
  206. hsync-len = <11>;
  207. vsync-len = <13>;
  208. };
  209. };
  210. };
  211. junk {
  212. reg = <1 1>;
  213. compatible = "not,compatible";
  214. };
  215. no-compatible {
  216. reg = <2 1>;
  217. };
  218. backlight: backlight {
  219. compatible = "pwm-backlight";
  220. enable-gpios = <&gpio_a 1>;
  221. power-supply = <&ldo_1>;
  222. pwms = <&pwm 0 1000>;
  223. default-brightness-level = <5>;
  224. brightness-levels = <0 16 32 64 128 170 202 234 255>;
  225. };
  226. bind-test {
  227. compatible = "simple-bus";
  228. bind-test-child1 {
  229. compatible = "sandbox,phy";
  230. #phy-cells = <1>;
  231. };
  232. bind-test-child2 {
  233. compatible = "simple-bus";
  234. };
  235. };
  236. b-test {
  237. reg = <3 1>;
  238. compatible = "denx,u-boot-fdt-test";
  239. ping-expect = <3>;
  240. ping-add = <3>;
  241. mux-controls = <&muxcontroller0 0>;
  242. mux-control-names = "mux0";
  243. };
  244. phy_provider0: gen_phy@0 {
  245. compatible = "sandbox,phy";
  246. #phy-cells = <1>;
  247. };
  248. phy_provider1: gen_phy@1 {
  249. compatible = "sandbox,phy";
  250. #phy-cells = <0>;
  251. broken;
  252. };
  253. phy_provider2: gen_phy@2 {
  254. compatible = "sandbox,phy";
  255. #phy-cells = <0>;
  256. };
  257. gen_phy_user: gen_phy_user {
  258. compatible = "simple-bus";
  259. phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
  260. phy-names = "phy1", "phy2", "phy3";
  261. };
  262. gen_phy_user1: gen_phy_user1 {
  263. compatible = "simple-bus";
  264. phys = <&phy_provider0 0>, <&phy_provider2>;
  265. phy-names = "phy1", "phy2";
  266. };
  267. some-bus {
  268. #address-cells = <1>;
  269. #size-cells = <0>;
  270. compatible = "denx,u-boot-test-bus";
  271. reg = <3 1>;
  272. ping-expect = <4>;
  273. ping-add = <4>;
  274. c-test@5 {
  275. compatible = "denx,u-boot-fdt-test";
  276. reg = <5>;
  277. ping-expect = <5>;
  278. ping-add = <5>;
  279. };
  280. c-test@0 {
  281. compatible = "denx,u-boot-fdt-test";
  282. reg = <0>;
  283. ping-expect = <6>;
  284. ping-add = <6>;
  285. };
  286. c-test@1 {
  287. compatible = "denx,u-boot-fdt-test";
  288. reg = <1>;
  289. ping-expect = <7>;
  290. ping-add = <7>;
  291. };
  292. };
  293. d-test {
  294. reg = <3 1>;
  295. ping-expect = <6>;
  296. ping-add = <6>;
  297. compatible = "google,another-fdt-test";
  298. };
  299. e-test {
  300. reg = <3 1>;
  301. ping-expect = <6>;
  302. ping-add = <6>;
  303. compatible = "google,another-fdt-test";
  304. };
  305. f-test {
  306. compatible = "denx,u-boot-fdt-test";
  307. };
  308. g-test {
  309. compatible = "denx,u-boot-fdt-test";
  310. };
  311. h-test {
  312. compatible = "denx,u-boot-fdt-test1";
  313. };
  314. i-test {
  315. compatible = "mediatek,u-boot-fdt-test";
  316. #address-cells = <1>;
  317. #size-cells = <0>;
  318. subnode@0 {
  319. reg = <0>;
  320. };
  321. subnode@1 {
  322. reg = <1>;
  323. };
  324. subnode@2 {
  325. reg = <2>;
  326. };
  327. };
  328. devres-test {
  329. compatible = "denx,u-boot-devres-test";
  330. };
  331. another-test {
  332. reg = <0 2>;
  333. compatible = "denx,u-boot-fdt-test";
  334. test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
  335. test5-gpios = <&gpio_a 19>;
  336. };
  337. mmio-bus@0 {
  338. #address-cells = <1>;
  339. #size-cells = <1>;
  340. compatible = "denx,u-boot-test-bus";
  341. dma-ranges = <0x10000000 0x00000000 0x00040000>;
  342. subnode@0 {
  343. compatible = "denx,u-boot-fdt-test";
  344. };
  345. };
  346. mmio-bus@1 {
  347. #address-cells = <1>;
  348. #size-cells = <1>;
  349. compatible = "denx,u-boot-test-bus";
  350. subnode@0 {
  351. compatible = "denx,u-boot-fdt-test";
  352. };
  353. };
  354. acpi_test1: acpi-test {
  355. compatible = "denx,u-boot-acpi-test";
  356. acpi-ssdt-test-data = "ab";
  357. acpi-dsdt-test-data = "hi";
  358. child {
  359. compatible = "denx,u-boot-acpi-test";
  360. };
  361. };
  362. acpi_test2: acpi-test2 {
  363. compatible = "denx,u-boot-acpi-test";
  364. acpi-ssdt-test-data = "cd";
  365. acpi-dsdt-test-data = "jk";
  366. };
  367. clocks {
  368. clk_fixed: clk-fixed {
  369. compatible = "fixed-clock";
  370. #clock-cells = <0>;
  371. clock-frequency = <1234>;
  372. };
  373. clk_fixed_factor: clk-fixed-factor {
  374. compatible = "fixed-factor-clock";
  375. #clock-cells = <0>;
  376. clock-div = <3>;
  377. clock-mult = <2>;
  378. clocks = <&clk_fixed>;
  379. };
  380. osc {
  381. compatible = "fixed-clock";
  382. #clock-cells = <0>;
  383. clock-frequency = <20000000>;
  384. };
  385. };
  386. clk_sandbox: clk-sbox {
  387. compatible = "sandbox,clk";
  388. #clock-cells = <1>;
  389. assigned-clocks = <&clk_sandbox 3>;
  390. assigned-clock-rates = <321>;
  391. };
  392. clk-test {
  393. compatible = "sandbox,clk-test";
  394. clocks = <&clk_fixed>,
  395. <&clk_sandbox 1>,
  396. <&clk_sandbox 0>,
  397. <&clk_sandbox 3>,
  398. <&clk_sandbox 2>;
  399. clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
  400. };
  401. ccf: clk-ccf {
  402. compatible = "sandbox,clk-ccf";
  403. };
  404. eth@10002000 {
  405. compatible = "sandbox,eth";
  406. reg = <0x10002000 0x1000>;
  407. fake-host-hwaddr = [00 00 66 44 22 00];
  408. };
  409. eth_5: eth@10003000 {
  410. compatible = "sandbox,eth";
  411. reg = <0x10003000 0x1000>;
  412. fake-host-hwaddr = [00 00 66 44 22 11];
  413. };
  414. eth_3: sbe5 {
  415. compatible = "sandbox,eth";
  416. reg = <0x10005000 0x1000>;
  417. fake-host-hwaddr = [00 00 66 44 22 33];
  418. };
  419. eth@10004000 {
  420. compatible = "sandbox,eth";
  421. reg = <0x10004000 0x1000>;
  422. fake-host-hwaddr = [00 00 66 44 22 22];
  423. };
  424. dsa_eth0: dsa-test-eth {
  425. compatible = "sandbox,eth";
  426. reg = <0x10006000 0x1000>;
  427. fake-host-hwaddr = [00 00 66 44 22 66];
  428. };
  429. dsa-test {
  430. compatible = "sandbox,dsa";
  431. ports {
  432. #address-cells = <1>;
  433. #size-cells = <0>;
  434. swp_0: port@0 {
  435. reg = <0>;
  436. label = "lan0";
  437. phy-mode = "rgmii-rxid";
  438. fixed-link {
  439. speed = <100>;
  440. full-duplex;
  441. };
  442. };
  443. swp_1: port@1 {
  444. reg = <1>;
  445. label = "lan1";
  446. phy-mode = "rgmii-txid";
  447. fixed-link {
  448. speed = <100>;
  449. full-duplex;
  450. };
  451. };
  452. port@2 {
  453. reg = <2>;
  454. ethernet = <&dsa_eth0>;
  455. fixed-link {
  456. speed = <1000>;
  457. full-duplex;
  458. };
  459. };
  460. };
  461. };
  462. firmware {
  463. sandbox_firmware: sandbox-firmware {
  464. compatible = "sandbox,firmware";
  465. };
  466. sandbox-scmi-agent@0 {
  467. compatible = "sandbox,scmi-agent";
  468. #address-cells = <1>;
  469. #size-cells = <0>;
  470. clk_scmi0: protocol@14 {
  471. reg = <0x14>;
  472. #clock-cells = <1>;
  473. };
  474. reset_scmi0: protocol@16 {
  475. reg = <0x16>;
  476. #reset-cells = <1>;
  477. };
  478. protocol@17 {
  479. reg = <0x17>;
  480. regulators {
  481. #address-cells = <1>;
  482. #size-cells = <0>;
  483. regul0_scmi0: reg@0 {
  484. reg = <0>;
  485. regulator-name = "sandbox-voltd0";
  486. regulator-min-microvolt = <1100000>;
  487. regulator-max-microvolt = <3300000>;
  488. };
  489. regul1_scmi0: reg@1 {
  490. reg = <0x1>;
  491. regulator-name = "sandbox-voltd1";
  492. regulator-min-microvolt = <1800000>;
  493. };
  494. };
  495. };
  496. };
  497. sandbox-scmi-agent@1 {
  498. compatible = "sandbox,scmi-agent";
  499. #address-cells = <1>;
  500. #size-cells = <0>;
  501. clk_scmi1: protocol@14 {
  502. reg = <0x14>;
  503. #clock-cells = <1>;
  504. };
  505. protocol@10 {
  506. reg = <0x10>;
  507. };
  508. };
  509. };
  510. pinctrl-gpio {
  511. compatible = "sandbox,pinctrl-gpio";
  512. gpio_a: base-gpios {
  513. compatible = "sandbox,gpio";
  514. gpio-controller;
  515. #gpio-cells = <1>;
  516. gpio-bank-name = "a";
  517. sandbox,gpio-count = <20>;
  518. hog_input_active_low {
  519. gpio-hog;
  520. input;
  521. gpios = <10 GPIO_ACTIVE_LOW>;
  522. };
  523. hog_input_active_high {
  524. gpio-hog;
  525. input;
  526. gpios = <11 GPIO_ACTIVE_HIGH>;
  527. };
  528. hog_output_low {
  529. gpio-hog;
  530. output-low;
  531. gpios = <12 GPIO_ACTIVE_HIGH>;
  532. };
  533. hog_output_high {
  534. gpio-hog;
  535. output-high;
  536. gpios = <13 GPIO_ACTIVE_HIGH>;
  537. };
  538. };
  539. gpio_b: extra-gpios {
  540. compatible = "sandbox,gpio";
  541. gpio-controller;
  542. #gpio-cells = <5>;
  543. gpio-bank-name = "b";
  544. sandbox,gpio-count = <10>;
  545. };
  546. gpio_c: pinmux-gpios {
  547. compatible = "sandbox,gpio";
  548. gpio-controller;
  549. #gpio-cells = <2>;
  550. gpio-bank-name = "c";
  551. sandbox,gpio-count = <10>;
  552. };
  553. };
  554. i2c@0 {
  555. #address-cells = <1>;
  556. #size-cells = <0>;
  557. reg = <0 1>;
  558. compatible = "sandbox,i2c";
  559. clock-frequency = <100000>;
  560. eeprom@2c {
  561. reg = <0x2c>;
  562. compatible = "i2c-eeprom";
  563. sandbox,emul = <&emul_eeprom>;
  564. partitions {
  565. compatible = "fixed-partitions";
  566. #address-cells = <1>;
  567. #size-cells = <1>;
  568. bootcount_i2c: bootcount@10 {
  569. reg = <10 2>;
  570. };
  571. };
  572. };
  573. rtc_0: rtc@43 {
  574. reg = <0x43>;
  575. compatible = "sandbox-rtc";
  576. sandbox,emul = <&emul0>;
  577. };
  578. rtc_1: rtc@61 {
  579. reg = <0x61>;
  580. compatible = "sandbox-rtc";
  581. sandbox,emul = <&emul1>;
  582. };
  583. i2c_emul: emul {
  584. reg = <0xff>;
  585. compatible = "sandbox,i2c-emul-parent";
  586. emul_eeprom: emul-eeprom {
  587. compatible = "sandbox,i2c-eeprom";
  588. sandbox,filename = "i2c.bin";
  589. sandbox,size = <256>;
  590. };
  591. emul0: emul0 {
  592. compatible = "sandbox,i2c-rtc-emul";
  593. };
  594. emul1: emull {
  595. compatible = "sandbox,i2c-rtc-emul";
  596. };
  597. };
  598. sandbox_pmic: sandbox_pmic {
  599. reg = <0x40>;
  600. sandbox,emul = <&emul_pmic0>;
  601. };
  602. mc34708: pmic@41 {
  603. reg = <0x41>;
  604. sandbox,emul = <&emul_pmic1>;
  605. };
  606. };
  607. bootcount@0 {
  608. compatible = "u-boot,bootcount-rtc";
  609. rtc = <&rtc_1>;
  610. offset = <0x13>;
  611. };
  612. bootcount {
  613. compatible = "u-boot,bootcount-i2c-eeprom";
  614. i2c-eeprom = <&bootcount_i2c>;
  615. };
  616. adc: adc@0 {
  617. compatible = "sandbox,adc";
  618. #io-channel-cells = <1>;
  619. vdd-supply = <&buck2>;
  620. vss-microvolts = <0>;
  621. };
  622. irq: irq {
  623. compatible = "sandbox,irq";
  624. interrupt-controller;
  625. #interrupt-cells = <2>;
  626. };
  627. lcd {
  628. u-boot,dm-pre-reloc;
  629. compatible = "sandbox,lcd-sdl";
  630. xres = <1366>;
  631. yres = <768>;
  632. };
  633. leds {
  634. compatible = "gpio-leds";
  635. iracibble {
  636. gpios = <&gpio_a 1 0>;
  637. label = "sandbox:red";
  638. };
  639. martinet {
  640. gpios = <&gpio_a 2 0>;
  641. label = "sandbox:green";
  642. };
  643. default_on {
  644. gpios = <&gpio_a 5 0>;
  645. label = "sandbox:default_on";
  646. default-state = "on";
  647. };
  648. default_off {
  649. gpios = <&gpio_a 6 0>;
  650. /* label intentionally omitted */
  651. default-state = "off";
  652. };
  653. };
  654. mbox: mbox {
  655. compatible = "sandbox,mbox";
  656. #mbox-cells = <1>;
  657. };
  658. mbox-test {
  659. compatible = "sandbox,mbox-test";
  660. mboxes = <&mbox 100>, <&mbox 1>;
  661. mbox-names = "other", "test";
  662. };
  663. cpus {
  664. timebase-frequency = <2000000>;
  665. cpu-test1 {
  666. timebase-frequency = <3000000>;
  667. compatible = "sandbox,cpu_sandbox";
  668. u-boot,dm-pre-reloc;
  669. };
  670. cpu-test2 {
  671. compatible = "sandbox,cpu_sandbox";
  672. u-boot,dm-pre-reloc;
  673. };
  674. cpu-test3 {
  675. compatible = "sandbox,cpu_sandbox";
  676. u-boot,dm-pre-reloc;
  677. };
  678. };
  679. chipid: chipid {
  680. compatible = "sandbox,soc";
  681. };
  682. i2s: i2s {
  683. compatible = "sandbox,i2s";
  684. #sound-dai-cells = <1>;
  685. sandbox,silent; /* Don't emit sounds while testing */
  686. };
  687. nop-test_0 {
  688. compatible = "sandbox,nop_sandbox1";
  689. nop-test_1 {
  690. compatible = "sandbox,nop_sandbox2";
  691. bind = "True";
  692. };
  693. nop-test_2 {
  694. compatible = "sandbox,nop_sandbox2";
  695. bind = "False";
  696. };
  697. };
  698. misc-test {
  699. compatible = "sandbox,misc_sandbox";
  700. };
  701. mmc2 {
  702. compatible = "sandbox,mmc";
  703. };
  704. mmc1 {
  705. compatible = "sandbox,mmc";
  706. };
  707. mmc0 {
  708. compatible = "sandbox,mmc";
  709. };
  710. pch {
  711. compatible = "sandbox,pch";
  712. };
  713. pci0: pci@0 {
  714. compatible = "sandbox,pci";
  715. device_type = "pci";
  716. bus-range = <0x00 0xff>;
  717. #address-cells = <3>;
  718. #size-cells = <2>;
  719. ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
  720. 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
  721. pci@0,0 {
  722. compatible = "pci-generic";
  723. reg = <0x0000 0 0 0 0>;
  724. sandbox,emul = <&swap_case_emul0_0>;
  725. };
  726. pci@1,0 {
  727. compatible = "pci-generic";
  728. /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
  729. reg = <0x02000814 0 0 0 0
  730. 0x01000810 0 0 0 0>;
  731. sandbox,emul = <&swap_case_emul0_1>;
  732. };
  733. p2sb-pci@2,0 {
  734. compatible = "sandbox,p2sb";
  735. reg = <0x02001010 0 0 0 0>;
  736. sandbox,emul = <&p2sb_emul>;
  737. adder {
  738. intel,p2sb-port-id = <3>;
  739. compatible = "sandbox,adder";
  740. };
  741. };
  742. pci@1e,0 {
  743. compatible = "sandbox,pmc";
  744. reg = <0xf000 0 0 0 0>;
  745. sandbox,emul = <&pmc_emul1e>;
  746. acpi-base = <0x400>;
  747. gpe0-dwx-mask = <0xf>;
  748. gpe0-dwx-shift-base = <4>;
  749. gpe0-dw = <6 7 9>;
  750. gpe0-sts = <0x20>;
  751. gpe0-en = <0x30>;
  752. };
  753. pci@1f,0 {
  754. compatible = "pci-generic";
  755. /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
  756. reg = <0x0100f810 0 0 0 0>;
  757. sandbox,emul = <&swap_case_emul0_1f>;
  758. };
  759. };
  760. pci-emul0 {
  761. compatible = "sandbox,pci-emul-parent";
  762. swap_case_emul0_0: emul0@0,0 {
  763. compatible = "sandbox,swap-case";
  764. };
  765. swap_case_emul0_1: emul0@1,0 {
  766. compatible = "sandbox,swap-case";
  767. use-ea;
  768. };
  769. swap_case_emul0_1f: emul0@1f,0 {
  770. compatible = "sandbox,swap-case";
  771. };
  772. p2sb_emul: emul@2,0 {
  773. compatible = "sandbox,p2sb-emul";
  774. };
  775. pmc_emul1e: emul@1e,0 {
  776. compatible = "sandbox,pmc-emul";
  777. };
  778. };
  779. pci1: pci@1 {
  780. compatible = "sandbox,pci";
  781. device_type = "pci";
  782. bus-range = <0x00 0xff>;
  783. #address-cells = <3>;
  784. #size-cells = <2>;
  785. ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
  786. 0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
  787. 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
  788. sandbox,dev-info = <0x08 0x00 0x1234 0x5678
  789. 0x0c 0x00 0x1234 0x5678
  790. 0x10 0x00 0x1234 0x5678>;
  791. pci@10,0 {
  792. reg = <0x8000 0 0 0 0>;
  793. };
  794. };
  795. pci2: pci@2 {
  796. compatible = "sandbox,pci";
  797. device_type = "pci";
  798. bus-range = <0x00 0xff>;
  799. #address-cells = <3>;
  800. #size-cells = <2>;
  801. ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
  802. 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
  803. sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
  804. pci@1f,0 {
  805. compatible = "pci-generic";
  806. reg = <0xf800 0 0 0 0>;
  807. sandbox,emul = <&swap_case_emul2_1f>;
  808. };
  809. };
  810. pci-emul2 {
  811. compatible = "sandbox,pci-emul-parent";
  812. swap_case_emul2_1f: emul2@1f,0 {
  813. compatible = "sandbox,swap-case";
  814. };
  815. };
  816. pci_ep: pci_ep {
  817. compatible = "sandbox,pci_ep";
  818. };
  819. probing {
  820. compatible = "simple-bus";
  821. test1 {
  822. compatible = "denx,u-boot-probe-test";
  823. };
  824. test2 {
  825. compatible = "denx,u-boot-probe-test";
  826. };
  827. test3 {
  828. compatible = "denx,u-boot-probe-test";
  829. };
  830. test4 {
  831. compatible = "denx,u-boot-probe-test";
  832. first-syscon = <&syscon0>;
  833. second-sys-ctrl = <&another_system_controller>;
  834. third-syscon = <&syscon2>;
  835. };
  836. };
  837. pwrdom: power-domain {
  838. compatible = "sandbox,power-domain";
  839. #power-domain-cells = <1>;
  840. };
  841. power-domain-test {
  842. compatible = "sandbox,power-domain-test";
  843. power-domains = <&pwrdom 2>;
  844. };
  845. pwm: pwm {
  846. compatible = "sandbox,pwm";
  847. #pwm-cells = <2>;
  848. };
  849. pwm2 {
  850. compatible = "sandbox,pwm";
  851. #pwm-cells = <2>;
  852. };
  853. ram {
  854. compatible = "sandbox,ram";
  855. };
  856. reset@0 {
  857. compatible = "sandbox,warm-reset";
  858. };
  859. reset@1 {
  860. compatible = "sandbox,reset";
  861. };
  862. resetc: reset-ctl {
  863. compatible = "sandbox,reset-ctl";
  864. #reset-cells = <1>;
  865. };
  866. reset-ctl-test {
  867. compatible = "sandbox,reset-ctl-test";
  868. resets = <&resetc 100>, <&resetc 2>;
  869. reset-names = "other", "test";
  870. };
  871. rng {
  872. compatible = "sandbox,sandbox-rng";
  873. };
  874. rproc_1: rproc@1 {
  875. compatible = "sandbox,test-processor";
  876. remoteproc-name = "remoteproc-test-dev1";
  877. };
  878. rproc_2: rproc@2 {
  879. compatible = "sandbox,test-processor";
  880. internal-memory-mapped;
  881. remoteproc-name = "remoteproc-test-dev2";
  882. };
  883. panel {
  884. compatible = "simple-panel";
  885. backlight = <&backlight 0 100>;
  886. };
  887. smem@0 {
  888. compatible = "sandbox,smem";
  889. };
  890. sound {
  891. compatible = "sandbox,sound";
  892. cpu {
  893. sound-dai = <&i2s 0>;
  894. };
  895. codec {
  896. sound-dai = <&audio 0>;
  897. };
  898. };
  899. spi@0 {
  900. #address-cells = <1>;
  901. #size-cells = <0>;
  902. reg = <0 1>;
  903. compatible = "sandbox,spi";
  904. cs-gpios = <0>, <0>, <&gpio_a 0>;
  905. spi.bin@0 {
  906. reg = <0>;
  907. compatible = "spansion,m25p16", "jedec,spi-nor";
  908. spi-max-frequency = <40000000>;
  909. sandbox,filename = "spi.bin";
  910. };
  911. spi.bin@1 {
  912. reg = <1>;
  913. compatible = "spansion,m25p16", "jedec,spi-nor";
  914. spi-max-frequency = <50000000>;
  915. sandbox,filename = "spi.bin";
  916. spi-cpol;
  917. spi-cpha;
  918. };
  919. };
  920. syscon0: syscon@0 {
  921. compatible = "sandbox,syscon0";
  922. reg = <0x10 16>;
  923. };
  924. another_system_controller: syscon@1 {
  925. compatible = "sandbox,syscon1";
  926. reg = <0x20 5
  927. 0x28 6
  928. 0x30 7
  929. 0x38 8>;
  930. };
  931. syscon2: syscon@2 {
  932. compatible = "simple-mfd", "syscon";
  933. reg = <0x40 5
  934. 0x48 6
  935. 0x50 7
  936. 0x58 8>;
  937. };
  938. syscon3: syscon@3 {
  939. compatible = "simple-mfd", "syscon";
  940. reg = <0x000100 0x10>;
  941. muxcontroller0: a-mux-controller {
  942. compatible = "mmio-mux";
  943. #mux-control-cells = <1>;
  944. mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
  945. <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
  946. <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
  947. idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
  948. u-boot,mux-autoprobe;
  949. };
  950. };
  951. muxcontroller1: emul-mux-controller {
  952. compatible = "mux-emul";
  953. #mux-control-cells = <0>;
  954. u-boot,mux-autoprobe;
  955. idle-state = <0xabcd>;
  956. };
  957. testfdtm0 {
  958. compatible = "denx,u-boot-fdtm-test";
  959. };
  960. testfdtm1: testfdtm1 {
  961. compatible = "denx,u-boot-fdtm-test";
  962. };
  963. testfdtm2 {
  964. compatible = "denx,u-boot-fdtm-test";
  965. };
  966. timer@0 {
  967. compatible = "sandbox,timer";
  968. clock-frequency = <1000000>;
  969. };
  970. timer@1 {
  971. compatible = "sandbox,timer";
  972. sandbox,timebase-frequency-fallback;
  973. };
  974. tpm2 {
  975. compatible = "sandbox,tpm2";
  976. };
  977. uart0: serial {
  978. compatible = "sandbox,serial";
  979. u-boot,dm-pre-reloc;
  980. };
  981. usb_0: usb@0 {
  982. compatible = "sandbox,usb";
  983. status = "disabled";
  984. hub {
  985. compatible = "sandbox,usb-hub";
  986. #address-cells = <1>;
  987. #size-cells = <0>;
  988. flash-stick {
  989. reg = <0>;
  990. compatible = "sandbox,usb-flash";
  991. };
  992. };
  993. };
  994. usb_1: usb@1 {
  995. compatible = "sandbox,usb";
  996. hub {
  997. compatible = "usb-hub";
  998. usb,device-class = <9>;
  999. #address-cells = <1>;
  1000. #size-cells = <0>;
  1001. hub-emul {
  1002. compatible = "sandbox,usb-hub";
  1003. #address-cells = <1>;
  1004. #size-cells = <0>;
  1005. flash-stick@0 {
  1006. reg = <0>;
  1007. compatible = "sandbox,usb-flash";
  1008. sandbox,filepath = "testflash.bin";
  1009. };
  1010. flash-stick@1 {
  1011. reg = <1>;
  1012. compatible = "sandbox,usb-flash";
  1013. sandbox,filepath = "testflash1.bin";
  1014. };
  1015. flash-stick@2 {
  1016. reg = <2>;
  1017. compatible = "sandbox,usb-flash";
  1018. sandbox,filepath = "testflash2.bin";
  1019. };
  1020. keyb@3 {
  1021. reg = <3>;
  1022. compatible = "sandbox,usb-keyb";
  1023. };
  1024. };
  1025. usbstor@1 {
  1026. reg = <1>;
  1027. };
  1028. usbstor@3 {
  1029. reg = <3>;
  1030. };
  1031. };
  1032. };
  1033. usb_2: usb@2 {
  1034. compatible = "sandbox,usb";
  1035. status = "disabled";
  1036. };
  1037. spmi: spmi@0 {
  1038. compatible = "sandbox,spmi";
  1039. #address-cells = <0x1>;
  1040. #size-cells = <0x1>;
  1041. ranges;
  1042. pm8916@0 {
  1043. compatible = "qcom,spmi-pmic";
  1044. reg = <0x0 0x1>;
  1045. #address-cells = <0x1>;
  1046. #size-cells = <0x1>;
  1047. ranges;
  1048. spmi_gpios: gpios@c000 {
  1049. compatible = "qcom,pm8916-gpio";
  1050. reg = <0xc000 0x400>;
  1051. gpio-controller;
  1052. gpio-count = <4>;
  1053. #gpio-cells = <2>;
  1054. gpio-bank-name="spmi";
  1055. };
  1056. };
  1057. };
  1058. wdt0: wdt@0 {
  1059. compatible = "sandbox,wdt";
  1060. };
  1061. axi: axi@0 {
  1062. compatible = "sandbox,axi";
  1063. #address-cells = <0x1>;
  1064. #size-cells = <0x1>;
  1065. store@0 {
  1066. compatible = "sandbox,sandbox_store";
  1067. reg = <0x0 0x400>;
  1068. };
  1069. };
  1070. chosen {
  1071. #address-cells = <1>;
  1072. #size-cells = <1>;
  1073. setting = "sunrise ohoka";
  1074. other-node = "/some-bus/c-test@5";
  1075. int-values = <0x1937 72993>;
  1076. u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
  1077. chosen-test {
  1078. compatible = "denx,u-boot-fdt-test";
  1079. reg = <9 1>;
  1080. };
  1081. };
  1082. translation-test@8000 {
  1083. compatible = "simple-bus";
  1084. reg = <0x8000 0x4000>;
  1085. #address-cells = <0x2>;
  1086. #size-cells = <0x1>;
  1087. ranges = <0 0x0 0x8000 0x1000
  1088. 1 0x100 0x9000 0x1000
  1089. 2 0x200 0xA000 0x1000
  1090. 3 0x300 0xB000 0x1000
  1091. 4 0x400 0xC000 0x1000
  1092. >;
  1093. dma-ranges = <0 0x000 0x10000000 0x1000
  1094. 1 0x100 0x20000000 0x1000
  1095. >;
  1096. dev@0,0 {
  1097. compatible = "denx,u-boot-fdt-dummy";
  1098. reg = <0 0x0 0x1000>;
  1099. reg-names = "sandbox-dummy-0";
  1100. };
  1101. dev@1,100 {
  1102. compatible = "denx,u-boot-fdt-dummy";
  1103. reg = <1 0x100 0x1000>;
  1104. };
  1105. dev@2,200 {
  1106. compatible = "denx,u-boot-fdt-dummy";
  1107. reg = <2 0x200 0x1000>;
  1108. };
  1109. noxlatebus@3,300 {
  1110. compatible = "simple-bus";
  1111. reg = <3 0x300 0x1000>;
  1112. #address-cells = <0x1>;
  1113. #size-cells = <0x0>;
  1114. dev@42 {
  1115. compatible = "denx,u-boot-fdt-dummy";
  1116. reg = <0x42>;
  1117. };
  1118. };
  1119. xlatebus@4,400 {
  1120. compatible = "sandbox,zero-size-cells-bus";
  1121. reg = <4 0x400 0x1000>;
  1122. #address-cells = <1>;
  1123. #size-cells = <1>;
  1124. ranges = <0 4 0x400 0x1000>;
  1125. devs {
  1126. #address-cells = <1>;
  1127. #size-cells = <0>;
  1128. dev@19 {
  1129. compatible = "denx,u-boot-fdt-dummy";
  1130. reg = <0x19>;
  1131. };
  1132. };
  1133. };
  1134. };
  1135. osd {
  1136. compatible = "sandbox,sandbox_osd";
  1137. };
  1138. sandbox_tee {
  1139. compatible = "sandbox,tee";
  1140. };
  1141. sandbox_virtio1 {
  1142. compatible = "sandbox,virtio1";
  1143. };
  1144. sandbox_virtio2 {
  1145. compatible = "sandbox,virtio2";
  1146. };
  1147. sandbox_scmi {
  1148. compatible = "sandbox,scmi-devices";
  1149. clocks = <&clk_scmi0 7>, <&clk_scmi0 3>, <&clk_scmi1 1>;
  1150. resets = <&reset_scmi0 3>;
  1151. regul0-supply = <&regul0_scmi0>;
  1152. regul1-supply = <&regul1_scmi0>;
  1153. };
  1154. pinctrl {
  1155. compatible = "sandbox,pinctrl";
  1156. pinctrl-names = "default", "alternate";
  1157. pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
  1158. pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
  1159. pinctrl_gpios: gpios {
  1160. gpio0 {
  1161. pins = "P5";
  1162. function = "GPIO";
  1163. bias-pull-up;
  1164. input-disable;
  1165. };
  1166. gpio1 {
  1167. pins = "P6";
  1168. function = "GPIO";
  1169. output-high;
  1170. drive-open-drain;
  1171. };
  1172. gpio2 {
  1173. pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
  1174. bias-pull-down;
  1175. input-enable;
  1176. };
  1177. gpio3 {
  1178. pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
  1179. bias-disable;
  1180. };
  1181. };
  1182. pinctrl_i2c: i2c {
  1183. groups {
  1184. groups = "I2C_UART";
  1185. function = "I2C";
  1186. };
  1187. pins {
  1188. pins = "P0", "P1";
  1189. drive-open-drain;
  1190. };
  1191. };
  1192. pinctrl_i2s: i2s {
  1193. groups = "SPI_I2S";
  1194. function = "I2S";
  1195. };
  1196. pinctrl_spi: spi {
  1197. groups = "SPI_I2S";
  1198. function = "SPI";
  1199. cs {
  1200. pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
  1201. <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
  1202. };
  1203. };
  1204. };
  1205. hwspinlock@0 {
  1206. compatible = "sandbox,hwspinlock";
  1207. };
  1208. dma: dma {
  1209. compatible = "sandbox,dma";
  1210. #dma-cells = <1>;
  1211. dmas = <&dma 0>, <&dma 1>, <&dma 2>;
  1212. dma-names = "m2m", "tx0", "rx0";
  1213. };
  1214. /*
  1215. * keep mdio-mux ahead of mdio so that the mux is removed first at the
  1216. * end of the test. If parent mdio is removed first, clean-up of the
  1217. * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
  1218. * active at the end of the test. That it turn doesn't allow the mdio
  1219. * class to be destroyed, triggering an error.
  1220. */
  1221. mdio-mux-test {
  1222. compatible = "sandbox,mdio-mux";
  1223. #address-cells = <1>;
  1224. #size-cells = <0>;
  1225. mdio-parent-bus = <&mdio>;
  1226. mdio-ch-test@0 {
  1227. reg = <0>;
  1228. };
  1229. mdio-ch-test@1 {
  1230. reg = <1>;
  1231. };
  1232. };
  1233. mdio: mdio-test {
  1234. compatible = "sandbox,mdio";
  1235. };
  1236. pm-bus-test {
  1237. compatible = "simple-pm-bus";
  1238. clocks = <&clk_sandbox 4>;
  1239. power-domains = <&pwrdom 1>;
  1240. };
  1241. resetc2: syscon-reset {
  1242. compatible = "syscon-reset";
  1243. #reset-cells = <1>;
  1244. regmap = <&syscon0>;
  1245. offset = <1>;
  1246. mask = <0x27FFFFFF>;
  1247. assert-high = <0>;
  1248. };
  1249. syscon-reset-test {
  1250. compatible = "sandbox,misc_sandbox";
  1251. resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
  1252. reset-names = "valid", "no_mask", "out_of_range";
  1253. };
  1254. sysinfo {
  1255. compatible = "sandbox,sysinfo-sandbox";
  1256. };
  1257. some_regmapped-bus {
  1258. #address-cells = <0x1>;
  1259. #size-cells = <0x1>;
  1260. ranges = <0x0 0x0 0x10>;
  1261. compatible = "simple-bus";
  1262. regmap-test_0 {
  1263. reg = <0 0x10>;
  1264. compatible = "sandbox,regmap_test";
  1265. };
  1266. };
  1267. };
  1268. #include "sandbox_pmic.dtsi"
  1269. #include "cros-ec-keyboard.dtsi"