starfive_visionfive.c 5.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2021-2023 StarFive Technology Co., Ltd.
  4. * Author: yanhong <yanhong.wang@starfivetech.com>
  5. *
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/jh7110-regs.h>
  10. #include <cpu_func.h>
  11. #include <dm/uclass.h>
  12. #include <dm/device.h>
  13. #include <env.h>
  14. #include <inttypes.h>
  15. #include <misc.h>
  16. #include <linux/bitops.h>
  17. #include <asm/arch/gpio.h>
  18. #define SYS_IOMUX_DOEN(gpio, oen) \
  19. clrsetbits_le32(SYS_IOMUX_BASE+GPIO_OFFSET(gpio), \
  20. GPIO_DOEN_MASK << GPIO_SHIFT(gpio), \
  21. (oen) << GPIO_SHIFT(gpio))
  22. #define SYS_IOMUX_DOUT(gpio, gpo) \
  23. clrsetbits_le32(SYS_IOMUX_BASE + GPIO_DOUT + GPIO_OFFSET(gpio),\
  24. GPIO_DOUT_MASK << GPIO_SHIFT(gpio),\
  25. ((gpo) & GPIO_DOUT_MASK) << GPIO_SHIFT(gpio))
  26. #define SYS_IOMUX_DIN(gpio, gpi)\
  27. clrsetbits_le32(SYS_IOMUX_BASE + GPIO_DIN + GPIO_OFFSET(gpi),\
  28. GPIO_DIN_MASK << GPIO_SHIFT(gpi),\
  29. ((gpio+2) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi))
  30. #define SYS_IOMUX_COMPLEX(gpio, gpi, gpo, oen) do {\
  31. SYS_IOMUX_DOEN(gpio, oen);\
  32. SYS_IOMUX_DOUT(gpio, gpo);\
  33. SYS_IOMUX_DIN(gpio, gpi); }while(0)
  34. #define SYS_CLOCK_ENABLE(clk) \
  35. setbits_le32(SYS_CRG_BASE + clk, CLK_ENABLE_MASK)
  36. static void sys_reset_clear(ulong assert, ulong status, u32 rst)
  37. {
  38. volatile u32 value;
  39. clrbits_le32(SYS_CRG_BASE + assert, BIT(rst));
  40. do{
  41. value = in_le32(SYS_CRG_BASE + status);
  42. }while((value & BIT(rst)) != BIT(rst));
  43. }
  44. static void jh7110_timer_init(void)
  45. {
  46. SYS_CLOCK_ENABLE(TIMER_CLK_APB_SHIFT);
  47. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER0_SHIFT);
  48. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER1_SHIFT);
  49. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER2_SHIFT);
  50. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER3_SHIFT);
  51. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  52. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_APB_SHIFT);
  53. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  54. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER0_SHIFT);
  55. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  56. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER1_SHIFT);
  57. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  58. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER2_SHIFT);
  59. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  60. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER3_SHIFT);
  61. }
  62. static void jh7110_gmac_init(int id)
  63. {
  64. switch (id) {
  65. case 0:
  66. clrsetbits_le32(AON_SYSCON_BASE + AON_SYSCFG_12,
  67. GMAC5_0_SEL_I_MASK,
  68. BIT(GMAC5_0_SEL_I_SHIFT) & GMAC5_0_SEL_I_MASK);
  69. break;
  70. case 1:
  71. clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_144,
  72. GMAC5_1_SEL_I_MASK,
  73. BIT(GMAC5_1_SEL_I_SHIFT) & GMAC5_1_SEL_I_MASK);
  74. break;
  75. default:
  76. break;
  77. }
  78. }
  79. static void jh7110_usb_init(void)
  80. {
  81. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  82. USB_MODE_STRAP_MASK,
  83. (2<<USB_MODE_STRAP_SHIFT) & USB_MODE_STRAP_MASK);
  84. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  85. USB_OTG_SUSPENDM_BYPS_MASK,
  86. BIT(USB_OTG_SUSPENDM_BYPS_SHIFT)
  87. & USB_OTG_SUSPENDM_BYPS_MASK);
  88. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  89. USB_OTG_SUSPENDM_MASK,
  90. BIT(USB_OTG_SUSPENDM_SHIFT) & USB_OTG_SUSPENDM_MASK);
  91. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  92. USB_PLL_EN_MASK,
  93. BIT(USB_PLL_EN_SHIFT) & USB_PLL_EN_MASK);
  94. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  95. USB_REFCLK_MODE_MASK,
  96. BIT(USB_REFCLK_MODE_SHIFT) & USB_REFCLK_MODE_MASK);
  97. clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24,
  98. PDRSTN_SPLIT_MASK,
  99. BIT(PDRSTN_SPLIT_SHIFT) & PDRSTN_SPLIT_MASK);
  100. clrsetbits_le32(SYS_IOMUX_BASE + SYS_IOMUX_32,
  101. IOMUX_USB_MASK,
  102. BIT(IOMUX_USB_SHIFT) & IOMUX_USB_MASK);
  103. }
  104. static void jh7110_mmc_init(int id)
  105. {
  106. if (id == 0) {
  107. SYS_IOMUX_DOEN(62, LOW);
  108. SYS_IOMUX_DOUT(62, 19);
  109. } else {
  110. SYS_IOMUX_DOEN(10, LOW);
  111. SYS_IOMUX_DOUT(10, 55);
  112. SYS_IOMUX_COMPLEX(9, 44, 57, 19);
  113. SYS_IOMUX_COMPLEX(11, 45, 58, 20);
  114. SYS_IOMUX_COMPLEX(12, 46, 59, 21);
  115. SYS_IOMUX_COMPLEX(7, 47, 60, 22);
  116. SYS_IOMUX_COMPLEX(8, 48, 61, 23);
  117. }
  118. }
  119. /*enable U74-mc hart1~hart4 prefetcher*/
  120. static void enable_prefetcher(void)
  121. {
  122. u32 hart;
  123. u32 *reg;
  124. #define L2_PREFETCHER_BASE_ADDR 0x2030000
  125. #define L2_PREFETCHER_OFFSET 0x2000
  126. /*hart1~hart4*/
  127. for (hart = 1; hart < 5; hart++) {
  128. reg = (u32 *)((u64)(L2_PREFETCHER_BASE_ADDR
  129. + hart*L2_PREFETCHER_OFFSET));
  130. mb(); /* memory barrier */
  131. setbits_le32(reg, 0x1);
  132. mb(); /* memory barrier */
  133. }
  134. }
  135. int board_init(void)
  136. {
  137. enable_caches();
  138. /*enable hart1-hart4 prefetcher*/
  139. // enable_prefetcher();
  140. jh7110_gmac_init(0);
  141. jh7110_gmac_init(1);
  142. jh7110_timer_init();
  143. jh7110_usb_init();
  144. jh7110_mmc_init(0);
  145. jh7110_mmc_init(1);
  146. return 0;
  147. }
  148. #ifdef CONFIG_MISC_INIT_R
  149. int misc_init_r(void)
  150. {
  151. char mac[6] = {0x66, 0x34, 0xb0, 0x6c, 0xde, 0xad };
  152. #if CONFIG_IS_ENABLED(STARFIVE_OTP)
  153. struct udevice *dev;
  154. char buf[8];
  155. int ret;
  156. #define MACADDR_OFFSET 0x8
  157. ret = uclass_get_device_by_driver(UCLASS_MISC,
  158. DM_DRIVER_GET(starfive_otp), &dev);
  159. if (ret) {
  160. debug("%s: could not find otp device\n", __func__);
  161. goto err;
  162. }
  163. ret = misc_read(dev, MACADDR_OFFSET, buf, sizeof(buf));
  164. if (ret != sizeof(buf))
  165. printf("%s: error reading mac from OTP\n", __func__);
  166. else
  167. if (buf[0] != 0xff)
  168. memcpy(mac, buf, 6);
  169. err:
  170. #endif
  171. eth_env_set_enetaddr("ethaddr", mac);
  172. return 0;
  173. }
  174. #endif