spl.c 1.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
  4. * Author: yanhong <yanhong.wang@starfivetech.com>
  5. *
  6. */
  7. #include <dm.h>
  8. #include <log.h>
  9. #include <asm/csr.h>
  10. #define CSR_U74_FEATURE_DISABLE 0x7c1
  11. int spl_soc_init(void)
  12. {
  13. int ret;
  14. struct udevice *dev;
  15. /* DDR init */
  16. ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  17. if (ret) {
  18. debug("DRAM init failed: %d\n", ret);
  19. return ret;
  20. }
  21. /*flash init*/
  22. ret = uclass_get_device(UCLASS_SPI_FLASH, 0, &dev);
  23. if (ret) {
  24. debug("SPI init failed: %d\n", ret);
  25. return ret;
  26. }
  27. return 0;
  28. }
  29. void harts_early_init(void)
  30. {
  31. /*
  32. * Feature Disable CSR
  33. *
  34. * Clear feature disable CSR to '0' to turn on all features for
  35. * each core. This operation must be in M-mode.
  36. */
  37. if (CONFIG_IS_ENABLED(RISCV_MMODE))
  38. csr_write(CSR_U74_FEATURE_DISABLE, 0);
  39. #ifdef CONFIG_SPL_BUILD
  40. /*clear L2 LIM memory
  41. * set __bss_end to 0x81e0000 region to zero
  42. */
  43. __asm__ __volatile__ (
  44. "la t1, __bss_end\n"
  45. "li t2, 0x81e0000\n"
  46. "spl_clear_l2im:\n"
  47. "addi t1, t1, 8\n"
  48. "sd zero, 0(t1)\n"
  49. "blt t1, t2, spl_clear_l2im\n");
  50. #endif
  51. }