tpm-v2.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Defines APIs and structures that allow software to interact with a
  4. * TPM2 device
  5. *
  6. * Copyright (c) 2020 Linaro
  7. * Copyright (c) 2018 Bootlin
  8. *
  9. * https://trustedcomputinggroup.org/resource/tss-overview-common-structures-specification/
  10. *
  11. * Author: Miquel Raynal <miquel.raynal@bootlin.com>
  12. */
  13. #ifndef __TPM_V2_H
  14. #define __TPM_V2_H
  15. #include <tpm-common.h>
  16. #define TPM2_DIGEST_LEN 32
  17. #define TPM2_SHA1_DIGEST_SIZE 20
  18. #define TPM2_SHA256_DIGEST_SIZE 32
  19. #define TPM2_SHA384_DIGEST_SIZE 48
  20. #define TPM2_SHA512_DIGEST_SIZE 64
  21. #define TPM2_SM3_256_DIGEST_SIZE 32
  22. #define TPM2_MAX_PCRS 32
  23. #define TPM2_PCR_SELECT_MAX ((TPM2_MAX_PCRS + 7) / 8)
  24. #define TPM2_MAX_CAP_BUFFER 1024
  25. #define TPM2_MAX_TPM_PROPERTIES ((TPM2_MAX_CAP_BUFFER - sizeof(u32) /* TPM2_CAP */ - \
  26. sizeof(u32)) / sizeof(struct tpms_tagged_property))
  27. /*
  28. * We deviate from this draft of the specification by increasing the value of
  29. * TPM2_NUM_PCR_BANKS from 3 to 16 to ensure compatibility with TPM2
  30. * implementations that have enabled a larger than typical number of PCR
  31. * banks. This larger value for TPM2_NUM_PCR_BANKS is expected to be included
  32. * in a future revision of the specification.
  33. */
  34. #define TPM2_NUM_PCR_BANKS 16
  35. /* Definition of (UINT32) TPM2_CAP Constants */
  36. #define TPM2_CAP_PCRS 0x00000005U
  37. #define TPM2_CAP_TPM_PROPERTIES 0x00000006U
  38. /* Definition of (UINT32) TPM2_PT Constants */
  39. #define TPM2_PT_GROUP (u32)(0x00000100)
  40. #define TPM2_PT_FIXED (u32)(TPM2_PT_GROUP * 1)
  41. #define TPM2_PT_MANUFACTURER (u32)(TPM2_PT_FIXED + 5)
  42. #define TPM2_PT_PCR_COUNT (u32)(TPM2_PT_FIXED + 18)
  43. #define TPM2_PT_MAX_COMMAND_SIZE (u32)(TPM2_PT_FIXED + 30)
  44. #define TPM2_PT_MAX_RESPONSE_SIZE (u32)(TPM2_PT_FIXED + 31)
  45. /* event types */
  46. #define EV_POST_CODE ((u32)0x00000001)
  47. #define EV_NO_ACTION ((u32)0x00000003)
  48. #define EV_SEPARATOR ((u32)0x00000004)
  49. #define EV_S_CRTM_CONTENTS ((u32)0x00000007)
  50. #define EV_S_CRTM_VERSION ((u32)0x00000008)
  51. #define EV_CPU_MICROCODE ((u32)0x00000009)
  52. #define EV_TABLE_OF_DEVICES ((u32)0x0000000B)
  53. /* TPMS_TAGGED_PROPERTY Structure */
  54. struct tpms_tagged_property {
  55. u32 property;
  56. u32 value;
  57. } __packed;
  58. /* TPMS_PCR_SELECTION Structure */
  59. struct tpms_pcr_selection {
  60. u16 hash;
  61. u8 size_of_select;
  62. u8 pcr_select[TPM2_PCR_SELECT_MAX];
  63. } __packed;
  64. /* TPML_PCR_SELECTION Structure */
  65. struct tpml_pcr_selection {
  66. u32 count;
  67. struct tpms_pcr_selection selection[TPM2_NUM_PCR_BANKS];
  68. } __packed;
  69. /* TPML_TAGGED_TPM_PROPERTY Structure */
  70. struct tpml_tagged_tpm_property {
  71. u32 count;
  72. struct tpms_tagged_property tpm_property[TPM2_MAX_TPM_PROPERTIES];
  73. } __packed;
  74. /* TPMU_CAPABILITIES Union */
  75. union tpmu_capabilities {
  76. /*
  77. * Non exhaustive. Only added the structs needed for our
  78. * current code
  79. */
  80. struct tpml_pcr_selection assigned_pcr;
  81. struct tpml_tagged_tpm_property tpm_properties;
  82. } __packed;
  83. /* TPMS_CAPABILITY_DATA Structure */
  84. struct tpms_capability_data {
  85. u32 capability;
  86. union tpmu_capabilities data;
  87. } __packed;
  88. /**
  89. * SHA1 Event Log Entry Format
  90. *
  91. * @pcr_index: PCRIndex event extended to
  92. * @event_type: Type of event (see EFI specs)
  93. * @digest: Value extended into PCR index
  94. * @event_size: Size of event
  95. * @event: Event data
  96. */
  97. struct tcg_pcr_event {
  98. u32 pcr_index;
  99. u32 event_type;
  100. u8 digest[TPM2_SHA1_DIGEST_SIZE];
  101. u32 event_size;
  102. u8 event[];
  103. } __packed;
  104. /**
  105. * Definition of TPMU_HA Union
  106. */
  107. union tmpu_ha {
  108. u8 sha1[TPM2_SHA1_DIGEST_SIZE];
  109. u8 sha256[TPM2_SHA256_DIGEST_SIZE];
  110. u8 sm3_256[TPM2_SM3_256_DIGEST_SIZE];
  111. u8 sha384[TPM2_SHA384_DIGEST_SIZE];
  112. u8 sha512[TPM2_SHA512_DIGEST_SIZE];
  113. } __packed;
  114. /**
  115. * Definition of TPMT_HA Structure
  116. *
  117. * @hash_alg: Hash algorithm defined in enum tpm2_algorithms
  118. * @digest: Digest value for a given algorithm
  119. */
  120. struct tpmt_ha {
  121. u16 hash_alg;
  122. union tmpu_ha digest;
  123. } __packed;
  124. /**
  125. * Definition of TPML_DIGEST_VALUES Structure
  126. *
  127. * @count: Number of algorithms supported by hardware
  128. * @digests: struct for algorithm id and hash value
  129. */
  130. struct tpml_digest_values {
  131. u32 count;
  132. struct tpmt_ha digests[TPM2_NUM_PCR_BANKS];
  133. } __packed;
  134. /**
  135. * Crypto Agile Log Entry Format
  136. *
  137. * @pcr_index: PCRIndex event extended to
  138. * @event_type: Type of event
  139. * @digests: List of digestsextended to PCR index
  140. * @event_size: Size of the event data
  141. * @event: Event data
  142. */
  143. struct tcg_pcr_event2 {
  144. u32 pcr_index;
  145. u32 event_type;
  146. struct tpml_digest_values digests;
  147. u32 event_size;
  148. u8 event[];
  149. } __packed;
  150. /**
  151. * TPM2 Structure Tags for command/response buffers.
  152. *
  153. * @TPM2_ST_NO_SESSIONS: the command does not need an authentication.
  154. * @TPM2_ST_SESSIONS: the command needs an authentication.
  155. */
  156. enum tpm2_structures {
  157. TPM2_ST_NO_SESSIONS = 0x8001,
  158. TPM2_ST_SESSIONS = 0x8002,
  159. };
  160. /**
  161. * TPM2 type of boolean.
  162. */
  163. enum tpm2_yes_no {
  164. TPMI_YES = 1,
  165. TPMI_NO = 0,
  166. };
  167. /**
  168. * TPM2 startup values.
  169. *
  170. * @TPM2_SU_CLEAR: reset the internal state.
  171. * @TPM2_SU_STATE: restore saved state (if any).
  172. */
  173. enum tpm2_startup_types {
  174. TPM2_SU_CLEAR = 0x0000,
  175. TPM2_SU_STATE = 0x0001,
  176. };
  177. /**
  178. * TPM2 permanent handles.
  179. *
  180. * @TPM2_RH_OWNER: refers to the 'owner' hierarchy.
  181. * @TPM2_RS_PW: indicates a password.
  182. * @TPM2_RH_LOCKOUT: refers to the 'lockout' hierarchy.
  183. * @TPM2_RH_ENDORSEMENT: refers to the 'endorsement' hierarchy.
  184. * @TPM2_RH_PLATFORM: refers to the 'platform' hierarchy.
  185. */
  186. enum tpm2_handles {
  187. TPM2_RH_OWNER = 0x40000001,
  188. TPM2_RS_PW = 0x40000009,
  189. TPM2_RH_LOCKOUT = 0x4000000A,
  190. TPM2_RH_ENDORSEMENT = 0x4000000B,
  191. TPM2_RH_PLATFORM = 0x4000000C,
  192. };
  193. /**
  194. * TPM2 command codes used at the beginning of a buffer, gives the command.
  195. *
  196. * @TPM2_CC_STARTUP: TPM2_Startup().
  197. * @TPM2_CC_SELF_TEST: TPM2_SelfTest().
  198. * @TPM2_CC_CLEAR: TPM2_Clear().
  199. * @TPM2_CC_CLEARCONTROL: TPM2_ClearControl().
  200. * @TPM2_CC_HIERCHANGEAUTH: TPM2_HierarchyChangeAuth().
  201. * @TPM2_CC_PCR_SETAUTHPOL: TPM2_PCR_SetAuthPolicy().
  202. * @TPM2_CC_DAM_RESET: TPM2_DictionaryAttackLockReset().
  203. * @TPM2_CC_DAM_PARAMETERS: TPM2_DictionaryAttackParameters().
  204. * @TPM2_CC_GET_CAPABILITY: TPM2_GetCapibility().
  205. * @TPM2_CC_GET_RANDOM: TPM2_GetRandom().
  206. * @TPM2_CC_PCR_READ: TPM2_PCR_Read().
  207. * @TPM2_CC_PCR_EXTEND: TPM2_PCR_Extend().
  208. * @TPM2_CC_PCR_SETAUTHVAL: TPM2_PCR_SetAuthValue().
  209. */
  210. enum tpm2_command_codes {
  211. TPM2_CC_STARTUP = 0x0144,
  212. TPM2_CC_SELF_TEST = 0x0143,
  213. TPM2_CC_CLEAR = 0x0126,
  214. TPM2_CC_CLEARCONTROL = 0x0127,
  215. TPM2_CC_HIERCHANGEAUTH = 0x0129,
  216. TPM2_CC_PCR_SETAUTHPOL = 0x012C,
  217. TPM2_CC_DAM_RESET = 0x0139,
  218. TPM2_CC_DAM_PARAMETERS = 0x013A,
  219. TPM2_CC_NV_READ = 0x014E,
  220. TPM2_CC_GET_CAPABILITY = 0x017A,
  221. TPM2_CC_GET_RANDOM = 0x017B,
  222. TPM2_CC_PCR_READ = 0x017E,
  223. TPM2_CC_PCR_EXTEND = 0x0182,
  224. TPM2_CC_PCR_SETAUTHVAL = 0x0183,
  225. };
  226. /**
  227. * TPM2 return codes.
  228. */
  229. enum tpm2_return_codes {
  230. TPM2_RC_SUCCESS = 0x0000,
  231. TPM2_RC_BAD_TAG = 0x001E,
  232. TPM2_RC_FMT1 = 0x0080,
  233. TPM2_RC_HASH = TPM2_RC_FMT1 + 0x0003,
  234. TPM2_RC_VALUE = TPM2_RC_FMT1 + 0x0004,
  235. TPM2_RC_SIZE = TPM2_RC_FMT1 + 0x0015,
  236. TPM2_RC_BAD_AUTH = TPM2_RC_FMT1 + 0x0022,
  237. TPM2_RC_HANDLE = TPM2_RC_FMT1 + 0x000B,
  238. TPM2_RC_VER1 = 0x0100,
  239. TPM2_RC_INITIALIZE = TPM2_RC_VER1 + 0x0000,
  240. TPM2_RC_FAILURE = TPM2_RC_VER1 + 0x0001,
  241. TPM2_RC_DISABLED = TPM2_RC_VER1 + 0x0020,
  242. TPM2_RC_AUTH_MISSING = TPM2_RC_VER1 + 0x0025,
  243. TPM2_RC_COMMAND_CODE = TPM2_RC_VER1 + 0x0043,
  244. TPM2_RC_AUTHSIZE = TPM2_RC_VER1 + 0x0044,
  245. TPM2_RC_AUTH_CONTEXT = TPM2_RC_VER1 + 0x0045,
  246. TPM2_RC_NEEDS_TEST = TPM2_RC_VER1 + 0x0053,
  247. TPM2_RC_WARN = 0x0900,
  248. TPM2_RC_TESTING = TPM2_RC_WARN + 0x000A,
  249. TPM2_RC_REFERENCE_H0 = TPM2_RC_WARN + 0x0010,
  250. TPM2_RC_LOCKOUT = TPM2_RC_WARN + 0x0021,
  251. };
  252. /**
  253. * TPM2 algorithms.
  254. */
  255. enum tpm2_algorithms {
  256. TPM2_ALG_SHA1 = 0x04,
  257. TPM2_ALG_XOR = 0x0A,
  258. TPM2_ALG_SHA256 = 0x0B,
  259. TPM2_ALG_SHA384 = 0x0C,
  260. TPM2_ALG_SHA512 = 0x0D,
  261. TPM2_ALG_NULL = 0x10,
  262. TPM2_ALG_SM3_256 = 0x12,
  263. };
  264. /* NV index attributes */
  265. enum tpm_index_attrs {
  266. TPMA_NV_PPWRITE = 1UL << 0,
  267. TPMA_NV_OWNERWRITE = 1UL << 1,
  268. TPMA_NV_AUTHWRITE = 1UL << 2,
  269. TPMA_NV_POLICYWRITE = 1UL << 3,
  270. TPMA_NV_COUNTER = 1UL << 4,
  271. TPMA_NV_BITS = 1UL << 5,
  272. TPMA_NV_EXTEND = 1UL << 6,
  273. TPMA_NV_POLICY_DELETE = 1UL << 10,
  274. TPMA_NV_WRITELOCKED = 1UL << 11,
  275. TPMA_NV_WRITEALL = 1UL << 12,
  276. TPMA_NV_WRITEDEFINE = 1UL << 13,
  277. TPMA_NV_WRITE_STCLEAR = 1UL << 14,
  278. TPMA_NV_GLOBALLOCK = 1UL << 15,
  279. TPMA_NV_PPREAD = 1UL << 16,
  280. TPMA_NV_OWNERREAD = 1UL << 17,
  281. TPMA_NV_AUTHREAD = 1UL << 18,
  282. TPMA_NV_POLICYREAD = 1UL << 19,
  283. TPMA_NV_NO_DA = 1UL << 25,
  284. TPMA_NV_ORDERLY = 1UL << 26,
  285. TPMA_NV_CLEAR_STCLEAR = 1UL << 27,
  286. TPMA_NV_READLOCKED = 1UL << 28,
  287. TPMA_NV_WRITTEN = 1UL << 29,
  288. TPMA_NV_PLATFORMCREATE = 1UL << 30,
  289. TPMA_NV_READ_STCLEAR = 1UL << 31,
  290. TPMA_NV_MASK_READ = TPMA_NV_PPREAD | TPMA_NV_OWNERREAD |
  291. TPMA_NV_AUTHREAD | TPMA_NV_POLICYREAD,
  292. TPMA_NV_MASK_WRITE = TPMA_NV_PPWRITE | TPMA_NV_OWNERWRITE |
  293. TPMA_NV_AUTHWRITE | TPMA_NV_POLICYWRITE,
  294. };
  295. enum {
  296. TPM_ACCESS_VALID = 1 << 7,
  297. TPM_ACCESS_ACTIVE_LOCALITY = 1 << 5,
  298. TPM_ACCESS_REQUEST_PENDING = 1 << 2,
  299. TPM_ACCESS_REQUEST_USE = 1 << 1,
  300. TPM_ACCESS_ESTABLISHMENT = 1 << 0,
  301. };
  302. enum {
  303. TPM_STS_FAMILY_SHIFT = 26,
  304. TPM_STS_FAMILY_MASK = 0x3 << TPM_STS_FAMILY_SHIFT,
  305. TPM_STS_FAMILY_TPM2 = 1 << TPM_STS_FAMILY_SHIFT,
  306. TPM_STS_RESE_TESTABLISMENT_BIT = 1 << 25,
  307. TPM_STS_COMMAND_CANCEL = 1 << 24,
  308. TPM_STS_BURST_COUNT_SHIFT = 8,
  309. TPM_STS_BURST_COUNT_MASK = 0xffff << TPM_STS_BURST_COUNT_SHIFT,
  310. TPM_STS_VALID = 1 << 7,
  311. TPM_STS_COMMAND_READY = 1 << 6,
  312. TPM_STS_GO = 1 << 5,
  313. TPM_STS_DATA_AVAIL = 1 << 4,
  314. TPM_STS_DATA_EXPECT = 1 << 3,
  315. TPM_STS_SELF_TEST_DONE = 1 << 2,
  316. TPM_STS_RESPONSE_RETRY = 1 << 1,
  317. };
  318. enum {
  319. TPM_CMD_COUNT_OFFSET = 2,
  320. TPM_CMD_ORDINAL_OFFSET = 6,
  321. TPM_MAX_BUF_SIZE = 1260,
  322. };
  323. /**
  324. * Issue a TPM2_Startup command.
  325. *
  326. * @dev TPM device
  327. * @mode TPM startup mode
  328. *
  329. * @return code of the operation
  330. */
  331. u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode);
  332. /**
  333. * Issue a TPM2_SelfTest command.
  334. *
  335. * @dev TPM device
  336. * @full_test Asking to perform all tests or only the untested ones
  337. *
  338. * @return code of the operation
  339. */
  340. u32 tpm2_self_test(struct udevice *dev, enum tpm2_yes_no full_test);
  341. /**
  342. * Issue a TPM2_Clear command.
  343. *
  344. * @dev TPM device
  345. * @handle Handle
  346. * @pw Password
  347. * @pw_sz Length of the password
  348. *
  349. * @return code of the operation
  350. */
  351. u32 tpm2_clear(struct udevice *dev, u32 handle, const char *pw,
  352. const ssize_t pw_sz);
  353. /**
  354. * Issue a TPM2_PCR_Extend command.
  355. *
  356. * @dev TPM device
  357. * @index Index of the PCR
  358. * @algorithm Algorithm used, defined in 'enum tpm2_algorithms'
  359. * @digest Value representing the event to be recorded
  360. * @digest_len len of the hash
  361. *
  362. * @return code of the operation
  363. */
  364. u32 tpm2_pcr_extend(struct udevice *dev, u32 index, u32 algorithm,
  365. const u8 *digest, u32 digest_len);
  366. /**
  367. * Issue a TPM2_PCR_Read command.
  368. *
  369. * @dev TPM device
  370. * @idx Index of the PCR
  371. * @idx_min_sz Minimum size in bytes of the pcrSelect array
  372. * @data Output buffer for contents of the named PCR
  373. * @updates Optional out parameter: number of updates for this PCR
  374. *
  375. * @return code of the operation
  376. */
  377. u32 tpm2_pcr_read(struct udevice *dev, u32 idx, unsigned int idx_min_sz,
  378. void *data, unsigned int *updates);
  379. /**
  380. * Issue a TPM2_GetCapability command. This implementation is limited
  381. * to query property index that is 4-byte wide.
  382. *
  383. * @dev TPM device
  384. * @capability Partition of capabilities
  385. * @property Further definition of capability, limited to be 4 bytes wide
  386. * @buf Output buffer for capability information
  387. * @prop_count Size of output buffer
  388. *
  389. * @return code of the operation
  390. */
  391. u32 tpm2_get_capability(struct udevice *dev, u32 capability, u32 property,
  392. void *buf, size_t prop_count);
  393. /**
  394. * Issue a TPM2_DictionaryAttackLockReset command.
  395. *
  396. * @dev TPM device
  397. * @pw Password
  398. * @pw_sz Length of the password
  399. *
  400. * @return code of the operation
  401. */
  402. u32 tpm2_dam_reset(struct udevice *dev, const char *pw, const ssize_t pw_sz);
  403. /**
  404. * Issue a TPM2_DictionaryAttackParameters command.
  405. *
  406. * @dev TPM device
  407. * @pw Password
  408. * @pw_sz Length of the password
  409. * @max_tries Count of authorizations before lockout
  410. * @recovery_time Time before decrementation of the failure count
  411. * @lockout_recovery Time to wait after a lockout
  412. *
  413. * @return code of the operation
  414. */
  415. u32 tpm2_dam_parameters(struct udevice *dev, const char *pw,
  416. const ssize_t pw_sz, unsigned int max_tries,
  417. unsigned int recovery_time,
  418. unsigned int lockout_recovery);
  419. /**
  420. * Issue a TPM2_HierarchyChangeAuth command.
  421. *
  422. * @dev TPM device
  423. * @handle Handle
  424. * @newpw New password
  425. * @newpw_sz Length of the new password
  426. * @oldpw Old password
  427. * @oldpw_sz Length of the old password
  428. *
  429. * @return code of the operation
  430. */
  431. int tpm2_change_auth(struct udevice *dev, u32 handle, const char *newpw,
  432. const ssize_t newpw_sz, const char *oldpw,
  433. const ssize_t oldpw_sz);
  434. /**
  435. * Issue a TPM_PCR_SetAuthPolicy command.
  436. *
  437. * @dev TPM device
  438. * @pw Platform password
  439. * @pw_sz Length of the password
  440. * @index Index of the PCR
  441. * @digest New key to access the PCR
  442. *
  443. * @return code of the operation
  444. */
  445. u32 tpm2_pcr_setauthpolicy(struct udevice *dev, const char *pw,
  446. const ssize_t pw_sz, u32 index, const char *key);
  447. /**
  448. * Issue a TPM_PCR_SetAuthValue command.
  449. *
  450. * @dev TPM device
  451. * @pw Platform password
  452. * @pw_sz Length of the password
  453. * @index Index of the PCR
  454. * @digest New key to access the PCR
  455. * @key_sz Length of the new key
  456. *
  457. * @return code of the operation
  458. */
  459. u32 tpm2_pcr_setauthvalue(struct udevice *dev, const char *pw,
  460. const ssize_t pw_sz, u32 index, const char *key,
  461. const ssize_t key_sz);
  462. /**
  463. * Issue a TPM2_GetRandom command.
  464. *
  465. * @dev TPM device
  466. * @param data output buffer for the random bytes
  467. * @param count size of output buffer
  468. *
  469. * @return return code of the operation
  470. */
  471. u32 tpm2_get_random(struct udevice *dev, void *data, u32 count);
  472. #endif /* __TPM_V2_H */