cgtqmx8.h 5.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017-2018 NXP
  4. * Copyright 2018 congatec AG
  5. *
  6. */
  7. #ifndef __CGTQMX8_H
  8. #define __CGTQMX8_H
  9. #include <linux/sizes.h>
  10. #include <asm/arch/imx-regs.h>
  11. #ifdef CONFIG_SPL_BUILD
  12. #define CONFIG_SPL_TEXT_BASE 0x0
  13. #define CONFIG_SPL_MAX_SIZE (124 * 1024)
  14. #define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
  15. #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
  16. #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
  17. #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
  18. #define CONFIG_SPL_STACK 0x013E000
  19. #define CONFIG_SPL_BSS_START_ADDR 0x00128000
  20. #define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
  21. #define CONFIG_SYS_SPL_MALLOC_START 0x00120000
  22. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
  23. #define CONFIG_SERIAL_LPUART_BASE 0x5a060000
  24. #define CONFIG_MALLOC_F_ADDR 0x00120000
  25. #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
  26. #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
  27. #define CONFIG_OF_EMBED
  28. #endif
  29. #define CONFIG_REMAKE_ELF
  30. #define CONFIG_BOARD_EARLY_INIT_F
  31. /* Flat Device Tree Definitions */
  32. #define CONFIG_OF_BOARD_SETUP
  33. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  34. #define CONFIG_SYS_FSL_ESDHC_ADDR 0
  35. #define USDHC1_BASE_ADDR 0x5B010000
  36. #define USDHC2_BASE_ADDR 0x5B020000
  37. #define USDHC3_BASE_ADDR 0x5B030000
  38. #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
  39. #define CONFIG_ENV_OVERWRITE
  40. #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  41. /* Boot M4 */
  42. #define M4_BOOT_ENV \
  43. "m4_0_image=m4_0.bin\0" \
  44. "m4_1_image=m4_1.bin\0" \
  45. "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
  46. "loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \
  47. "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
  48. "m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \
  49. #ifdef CONFIG_NAND_BOOT
  50. #define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) "
  51. #else
  52. #define MFG_NAND_PARTITION ""
  53. #endif
  54. #define FEC0_RESET IMX_GPIO_NR(2, 5)
  55. #define FEC0_PDOMAIN "conn_enet0"
  56. #define CONFIG_MFG_ENV_SETTINGS \
  57. "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
  58. "rdinit=/linuxrc " \
  59. "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
  60. "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
  61. "g_mass_storage.iSerialNumber=\"\" "\
  62. MFG_NAND_PARTITION \
  63. "clk_ignore_unused "\
  64. "\0" \
  65. "initrd_addr=0x83800000\0" \
  66. "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
  67. /* Initial environment variables */
  68. #define CONFIG_EXTRA_ENV_SETTINGS \
  69. CONFIG_MFG_ENV_SETTINGS \
  70. M4_BOOT_ENV \
  71. "script=boot.scr\0" \
  72. "image=Image\0" \
  73. "panel=NULL\0" \
  74. "console=ttyLP0\0" \
  75. "fdt_addr=0x83000000\0" \
  76. "boot_fdt=try\0" \
  77. "fdt_file=imx8qm-cgt-qmx8.dtb\0" \
  78. "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
  79. "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
  80. "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
  81. "mmcautodetect=yes\0" \
  82. "mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} earlycon\0 " \
  83. "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
  84. "bootscript=echo Running bootscript from mmc ...; " \
  85. "source\0" \
  86. "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
  87. "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
  88. "mmcboot=echo Booting from mmc ...; " \
  89. "run mmcargs; " \
  90. "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  91. "if run loadfdt; then " \
  92. "booti ${loadaddr} - ${fdt_addr}; " \
  93. "else " \
  94. "echo WARN: Cannot load the DT; " \
  95. "fi; " \
  96. "else " \
  97. "echo wait for boot; " \
  98. "fi;\0" \
  99. "netargs=setenv bootargs console=${console},${baudrate} " \
  100. "root=/dev/nfs " \
  101. "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp rw earlycon\0" \
  102. "netboot=echo Booting from net ...; " \
  103. "run netargs; " \
  104. "if test ${ip_dyn} = yes; then " \
  105. "setenv get_cmd dhcp; " \
  106. "else " \
  107. "setenv get_cmd tftp; " \
  108. "fi; " \
  109. "${get_cmd} ${loadaddr} ${image}; " \
  110. "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  111. "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
  112. "booti ${loadaddr} - ${fdt_addr}; " \
  113. "else " \
  114. "echo WARN: Cannot load the DT; " \
  115. "fi; " \
  116. "else " \
  117. "booti; " \
  118. "fi;\0"
  119. #define CONFIG_BOOTCOMMAND \
  120. "mmc dev ${mmcdev}; if mmc rescan; then " \
  121. "if run loadbootscript; then " \
  122. "run bootscript; " \
  123. "else " \
  124. "if run loadimage; then " \
  125. "run mmcboot; " \
  126. "else run netboot; " \
  127. "fi; " \
  128. "fi; " \
  129. "else booti ${loadaddr} - ${fdt_addr}; fi"
  130. /* Link Definitions */
  131. #define CONFIG_LOADADDR 0x80280000
  132. #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  133. #define CONFIG_SYS_INIT_SP_ADDR 0x80200000
  134. #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
  135. #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
  136. #define CONFIG_SYS_FSL_USDHC_NUM 3
  137. /* Size of malloc() pool */
  138. #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
  139. #define CONFIG_SYS_SDRAM_BASE 0x80000000
  140. #define PHYS_SDRAM_1 0x80000000
  141. #define PHYS_SDRAM_2 0x880000000
  142. #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
  143. #define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */
  144. /* Serial */
  145. #define CONFIG_BAUDRATE 115200
  146. /* Generic Timer Definitions */
  147. #define COUNTER_FREQUENCY 8000000 /* 8MHz */
  148. /* Networking */
  149. #define CONFIG_FEC_MXC_PHYADDR -1
  150. #define CONFIG_FEC_XCV_TYPE RGMII
  151. #define FEC_QUIRK_ENET_MAC
  152. #endif /* __CGTQMX8_H */